KR960012586B1 - Method for manufacturing tft(thin film transistor) - Google Patents

Abstract

The method of manufacturing thin film transistor comprises the steps of : forming an active layer(10) after depositing and patterning a semiconductor material on a transparent substrate; forming a gate electrode pattern after depositing and patterning a gate insulating film(12) and a gate electrode(14) on the active layer(10); forming a source/a drain region(10c,10b) by ion-injection into the exposed active region; and forming an insulating film(20) by oxidizing the exposed active region through thermal oxidation.

Description

Manufacturing Method of Thin Film Transistor

1 is a cross-sectional structure diagram of a conventional thin film transistor.

2 is a cross-sectional view showing a manufacturing process of integrating a thin film transistor according to the present invention, as shown in FIGS. 2A to 2D.

The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor having a structure capable of reducing the leakage current between the source and the drain generated when the transistor is turned off.

Thin film transistors (hereinafter referred to as TFTs), which are commonly referred to as TFTs (Thin Film Transisters), are switch means for supplying voltages to pixels in liquid crystal display (LCD) devices, which are liquid crystal displays. A channel is connected between a data line and a pixel electrode providing a driving voltage to the liquid crystal, and a gate terminal is connected to a scan line for supplying a scan signal. Accordingly, the TFT is manufactured by using a semiconductor material, such as polycrystalline silicon or amorphous silicon, laminated on a transparent substrate on which a liquid crystal display device is manufactured. That is, after laminating polycrystalline silicon or amorphous silicon that acts as an active layer on a transparent substrate such as glass or quartz, an active layer pattern is formed, and an upper portion of the center of the active layer pattern is formed. After the gate electrode is formed, the source and drain regions are self-aligned by doping the remaining active layer regions except for the channel region under the gate electrode using an ion implantation method using the gate electrode as a mask. Formed. As such a technique, a technique for forming a source-drain region in a self-aligned manner by ion implanting a gate electrode with a mask is disclosed in detail in US Patent No. 4,597,160, issued in 1986.

However, a TFT having a source-drain region self-aligning has a problem in that an off current is large as the channel region under the gate electrode and the source and drain regions are adjacent to each other. The off current is a leakage current flowing between the source and drain terminals by an electric field formed between the drain terminal (or source terminal) having a constant voltage and the gate terminal when the voltage applied to the gate terminal of the TFT is turned off. For example, electric charges accumulate and flow from the source region connected to the pixel electrode side having a constant potential to the drain region through the channel region and eventually leak to the data line.

In order to solve this problem, a so-called offset resistance type structure in which the channel region and the source-drain region are spaced apart from each other has been proposed, which is illustrated in FIG.

1 shows the structure of a TFT fabricated to have an offset resistance. Referring to the configuration of FIG. 1, the active layer 1 is patterned on a transparent substrate, and has a gate insulating film 3 and a gate electrode 5 thereon. The left side and the right side of the active layer 1 are doped to act as the source region 1b and the drain region 1c, respectively. The active layer except for the source region 1b and the drain region 1c, that is, the active layer between the source region and the drain region, is undoped, of which the active layer located below the gate insulating film 3 is the channel region 1a. The resistance of the undoped active layer between each of the channel region 1a, the source region 1b and the drain region 1c acts as an offset resistance, thereby reducing the off current.

However, the TFT of the offset resistance structure shown in FIG. 1 has the advantage that the off current is reduced by forming the offset resistance. However, a separate photolithography process is required to manufacture the offset resistance structure. In comparison, the process is complicated and manufacturing costs are increased.

It is therefore an object of the present invention to provide a TFT manufacturing method which can reduce off current.

Another object of the present invention is to provide a method for manufacturing a TFT that is simple in processing and can sufficiently secure a separation distance between a gate electrode and a source or drain region.

In order to achieve the above object, the present invention forms a gate electrode and a source-drain region and thermally oxidizes the gate electrode, thereby securing a separation distance between the source-drain region and the gate electrode, as well as the electrical properties of the oxide film therebetween. It is characterized in that the manufacturing method of the TFT to reduce the off current by using the characteristic.

In addition, the present invention is characterized in that the method of manufacturing a TFT comprising the step of forming an insulating film spacer on the side of the gate electrode and ion implantation, and the step of removing the insulating film spacer and thermal oxidation.

Hereinafter, in order to provide a general understanding of the present invention, preferred embodiments of the TFT manufacturing process according to the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a preferred embodiment according to the present invention, which is composed of Figs. 2A to 2B, which sequentially show a cross-sectional structure in which TFTs are integrated according to a series of processes.

Referring to FIG. 2A, amorphous silicon (or polycrystalline silicon) is laminated on a transparent substrate, for example, glass, to a thickness of 1000 Å, and then patterned by a conventional photolithography process to form an active layer 10, and the active layer 10 An insulating film / conductive film / insulating film having a thickness of 1000 Å is sequentially stacked on the upper portion, and then patterned by a conventional photolithography method, where the gate insulating film 12, the gate electrode 14, and the protective insulating film 16 are sequentially stacked. A gate electrode pattern is formed. In the present embodiment, the gate electrode 14 is formed of polycrystalline silicon and doped with n-type impurities to increase the conductivity of the polycrystalline silicon.

Referring to FIG. 2B, an insulating film spacer having a length of about 3000 하면 on the side surface of the gate electrode pattern is formed by thickly depositing an insulating film on the structure shown in FIG. 2A and then etching back by using an anisotropic etching method. A manufacturing process is shown in which a spacer 18 is formed, followed by ion implantation of n-type impurities (such as phosphorus) at a dose of 10 ²⁰ ions / cm ² . In this case, it should be noted that ion implantation does not occur between the active layer under the gate electrode that operates as a channel region and the active layer under the spacer 18 that operates as an offset resistor. The ion implanted active layer is operated as a source-drain region, respectively. If the ion implanted at the time of ion implantation is a P-type impurity, it becomes a P-MOS TFT, and if it is an N-type impurity, it becomes an N-MOS TFT.

Referring to FIG. 2C, a manufacturing process in which the insulating film spacer 18 is removed by a wet etching method is illustrated. At this time, the active layer 10 is divided into a doped source region 10c and a drain region 10b and an undoped undoped region 10a. The active layer positioned below the gate electrode 14 of the undoped region 10a serves as a channel region, and the undoped active layer positioned between each of the channel region, the source region, and the drain region has a respective offset resistance. Will work.

Referring to FIG. 3D, there is shown a cross-sectional structure in which an insulating layer 20 having a thickness of 1000 시켜 is formed by oxidizing an exposed active layer by an oxidation process, for example, a wet oxidation method. At this time, since the exposed portion (that is, the region acting as the offset resistance) among the doped source-drain regions 10b and 10c and the undoped undoped region have different oxidation conditions, the doped region is more oxidized. Proceeding, both ends of the lower end of the gate electrode are also oxidized to some extent to form the structure shown in FIG. 2d. As a result, the distance between the gate electrode 14 and the source-drain region is further increased, which results in a thicker gate insulating film. Therefore, the electric field formed on the side of the gate electrode to which the turn-off voltage is applied from the source region having the constant potential is reduced. In addition, the channel region and the source-drain region under the gate insulating layer have a geometric structure not positioned on the horizontal line. Therefore, the resistance component of the undoped region between the channel region and the source-drain region may be used as an offset resistor. .

As a result, when the voltage is not supplied to the gate electrode, the electric field from the drain or source region having a constant potential to the gate electrode side is reduced. In addition, an offset resistance is also secured, thereby obtaining a structure of a TFT capable of minimizing off current.

In the above-described embodiment, in order to form the offset resistance structure, as shown in FIG. 2B, ion implantation was performed after forming the insulating film spacer on the side of the gate electrode pattern, but the process of manufacturing the insulating film spacer was omitted immediately. An ion implantation process can also be performed.

In addition, the same result can be obtained when a protective insulating film is formed by forming a gate electrode thickly and oxidizing the gate electrode by a final oxidation process without forming a protective insulating film over the gate electrode.

Claims (4)

In the method of manufacturing a thin film transistor, a first process of forming an active layer by laminating and patterning a semiconductor material on a transparent substrate, and forming a gate electrode pattern by laminating and patterning a gate insulating film and a gate electrode on top of the active layer A second step, a third step of forming a source-drain region by ion implantation into an exposed portion of the active layer, and a fourth step of forming an insulating film by oxidizing the exposed area of the active layer through a thermal oxidation process. A method of manufacturing a thin film transistor, characterized in that. In the method of manufacturing a thin film transistor, a first process of forming an active layer by laminating and patterning a semiconductor material on a transparent substrate, and forming a gate electrode pattern by laminating and patterning a gate insulating film and a gate electrode on top of the active layer A second process, a third process of forming insulating film spacers on sidewalls of the gate electrode, a fourth process of ion-implanting the active layer with the gate electrode pattern and the insulating film spacers as a mask to form a source-drain region, And a fifth process of oxidizing the exposed region of the active layer through a thermal oxidation process. The method of claim 2, wherein after the fourth process is completed, the insulating film spacer is removed and the fifth process is performed. The method of claim 2, wherein the thermal oxidation process is a wet oxidation method.