JP3325356B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used as a switch of an active matrix liquid crystal display or the like and a method of manufacturing the same.

[0002]

FIG. 9 shows, for example, Japanese Patent Publication No. 3-38755.
Of the related art, a conventional LDD (Lightly
FIG. 3 is a cross-sectional view illustrating a thin film transistor having a Doped Drain structure. In the figure, 1 is an insulating substrate, 2 is Si formed on the insulating substrate 1 and acting as a channel.
The thin film 3 is a low-concentration impurity region obtained by doping the Si thin film 2 with an impurity such as phosphorus or boron at a low concentration. 5 is a channel region made of the Si thin film 2, 6 is a gate insulating film formed on the Si thin film 2, 7 is a gate electrode formed on the gate insulating film 6, and 8 and 9 are source electrodes made of metal, respectively. Then, the contact hole 10 formed in the gate insulating film 6 is filled with a drain electrode and the source / drain region 4 is connected.

FIGS. 10A to 10G are cross-sectional views of a manufacturing process for explaining a method of manufacturing the thin film transistor shown in FIG.

First, as shown in FIG. 10A, a Si thin film 2 serving as a channel is formed on an insulating substrate 1, and then, as shown in FIG. 10B, a gate insulating film 6 made of SiO _{2 is} formed. Is formed by, for example, a thermal oxidation method or a sputtering method.

Next, as shown in FIG. 10C, a doped Si thin film doped with, for example, phosphorus is formed on the gate insulating film 6 by a method such as low pressure CVD, and the doped Si thin film is patterned. As a result, after the gate electrode 7 is formed, as shown in FIG. 10 (d), for example, phosphorus is ion-implanted at a low concentration into the Si thin film 2 using the gate electrode 7 as a mask. And a channel region 5 are formed.

Next, as shown in FIG. 10E, a photoresist 13 wider than the gate electrode 7 is patterned on the gate electrode 7, and as shown in FIG. 10F, the photoresist 13 is masked. The source / drain region 4 is formed by ion-implanting, for example, phosphorus into the low-concentration impurity region 3 formed in the Si thin film 2 at a high concentration to form the source / drain region 4 and the channel region 5. A low concentration impurity region 3 sandwiched is formed.

Next, as shown in FIG. 10G, the gate electrode insulating film 6 on the source / drain region 4 is formed.
After a contact hole 10 is formed, a thin metal film is formed inside and outside the contact hole 10 and patterned to form a source electrode 8 and a drain electrode 9, whereby the thin film transistor having the LDD structure shown in FIG. 9 is manufactured.

If the low-concentration ion implantation step shown in FIG. 10D is omitted, the low-concentration impurity region 3 is a region where impurity doping is not intentionally performed, and a thin film transistor having an offset structure can be manufactured.

In the thin film transistor constructed and manufactured as described above, the voltage applied between the source electrode 8 and the gate electrode 7 is controlled with the voltage applied between the source electrode 8 and the drain electrode 9. As a result, the source electrode 8
Since the drain current flowing between the gate electrode and the drain electrode 9 can be controlled, it can be used as, for example, a switching element of an active matrix liquid crystal display using this operation principle.

When used as a switching element in an active matrix liquid crystal display, the drain current when the thin film transistor is off needs to be at least equal to or less than the leakage current due to liquid crystal per pixel. It is important to reduce the drain current.

In order to increase the drain current at the time of ON, the Si thin film 2 serving as a channel is made of a polycrystalline Si thin film. In this case, field enhanced emission due to crystal grain boundaries and crystal defects existing in the polycrystalline Si thin film
Current is generated, and the drain current at the time of off increases, which is a particular problem. This increase in the drain current at the time of off is caused by the polycrystalline S
Number of dangling bonds present in i thin film and drain region 4
It is generally said that it is proportional to the electric field strength in the vicinity.

In order to reduce the drain current at the time of off,
In the conventional thin film transistor shown in FIG. 9, a low concentration impurity region 3 doped with an impurity at a low concentration is formed, the width of a depletion layer formed between the channel region 5 and the source / drain region 4 is increased, and the vicinity of the drain is reduced. Has an LDD structure that reduces the electric field strength of the semiconductor device.

[0013]

Since the conventional thin film transistor having the LDD structure is constructed as described above, if the low-concentration impurity region 3 is made longer in order to reduce the electric field intensity near the source / drain region 4, Although the off-state drain current can be reduced, the resistance of the low-concentration impurity region 3 increases at the same time, and the on-state drain current of the thin film transistor decreases. For this reason, it has been difficult to keep the drain current at the time of ON high and to reduce the drain current at the time of OFF.

In the manufacturing process shown in FIG. 10 (e), if the alignment between the gate electrode 7 and the photoresist 13 is misaligned, the length of the low-concentration impurity region 3 varies, so that the off-state drain current varies and Variation also occurs in the drain current at the time of ON. In particular, when a thin film transistor is used as a switching element of an active matrix liquid crystal display, a large number of thin film transistors are formed over the entire surface of the active matrix liquid crystal display because variation in switching characteristics of the thin film transistor causes non-uniform display characteristics. For all the thin film transistors, high-precision alignment between the gate electrode 7 and the photoresist 13 is required.

Furthermore, in a thin film transistor having a so-called offset structure in which the low-concentration impurity region 3 is not doped with an impurity, the drain current at the time of off can be reduced more effectively, but the resistance of the low-concentration impurity region 3 is lower than that of the LDD structure. As the length further increases, if the length of the low-concentration impurity region 3 becomes slightly too long, the drain current at the time of ON is sharply reduced. Therefore, the length of the low-concentration impurity region 3 must be controlled with high precision, but this control is extremely difficult.

As described above, in the thin film transistor having the conventional structure, it is difficult to reduce the drain current at the time of off without reducing the drain current at the time of on. However, it has been difficult to form a large number of thin film transistors having uniform switching characteristics on a large-sized device such as an active matrix liquid crystal display in which one device exceeds a few inches in size.

The present invention has been made in order to solve the conventional problems as described above, and does not require a high-precision exposure technique, and does not reduce the drain current at the on-state without reducing the drain current at the on-state. It is intended to provide a thin film transistor and a method for manufacturing the thin film transistor, which can reduce the amount of light.

[0018]

According to a first aspect of the present invention, there is provided a thin film transistor comprising an insulating substrate, a first Si thin film formed on the insulating substrate, and a thin film transistor in contact with the first Si thin film. A gate insulating film formed, a gate electrode formed on the gate insulating film, a channel region on the first Si thin film, and source / drain regions doped with high-concentration impurities on both sides of the channel region. Wherein the gate electrode is an auxiliary gate electrode made of a second Si thin film doped with a conductivity type opposite to the conductivity type of the source / drain region, and a p-type or n-type impurity is It is composed of a main gate electrode comprising a third Si thin film or a metal thin film which is heavily doped than the auxiliary gate electrode, the source
The gate main electrode with respect to the inner end of the drain region;
At a position farther than the vicinity of the auxiliary gate electrode
There is something.

According to a second aspect of the invention, there is provided the thin film transistor according to the first aspect, wherein the auxiliary gate electrode is provided in contact with the gate insulating film, and the main gate electrode is laminated on the auxiliary gate electrode. The width is smaller than the width of the auxiliary gate electrode.

According to a third aspect of the invention, there is provided a method of manufacturing a thin film transistor, comprising: a first Si thin film having a channel region and source / drain regions formed on both sides of the channel region; A method of manufacturing a thin film transistor having a gate insulating film formed by the above method, an auxiliary gate electrode and a main gate electrode formed on the gate insulating film, wherein a source / drain region is formed on the gate insulating film.
A second Si thin film doped with a conductivity type opposite to the
P-type or n-type impurities have a higher concentration than the second Si thin film
A step of continuously forming a doped third Si thin film or metal thin film, a step of patterning the third Si thin film or metal thin film to form a main gate electrode, and a step of forming a main gate electrode wider than the main gate electrode. Patterning the second Si thin film using a photoresist as a mask to form an auxiliary gate electrode; and implanting impurities into the first Si thin film using the photoresist as a mask to form source / drain regions. Things.

The thin film transistor according to the invention of claim 4, in the thin film transistor of claim 2, wherein, to form a region obtained by <br/> diffused impurity of the same conductivity type as the main gate electrode in the auxiliary gate electrode Things.

According to a fifth aspect of the invention, there is provided a method of manufacturing a thin film transistor, comprising: a first Si thin film having a channel region and source / drain regions formed on both sides of the channel region; A method of manufacturing a thin film transistor having a gate insulating film formed by the above method, an auxiliary gate electrode and a main gate electrode formed on the gate insulating film, wherein a source / drain region is formed on the gate insulating film.
The second Si thin film and the p-type or n-type impurity doped to the opposite conductivity type to the region are more concentrated than the second Si thin film.
Forming a continuously doped third Si thin film or metal thin film, and isotropic etching using a photoresist having the shape of an auxiliary gate electrode formed on the third Si thin film or metal thin film as a mask Forming the auxiliary gate electrode by anisotropic etching using the photoresist as a mask; and implanting an impurity into the first Si thin film using the photoresist as a mask to form a source / drain. Forming a region.

According to a sixth aspect of the present invention, there is provided the thin film transistor according to the first aspect, wherein the main gate electrode is narrower than the channel region width, is provided in contact with the gate insulating film, and the auxiliary gate electrode is the main gate electrode. It is provided in contact with the gate insulating film outside the electrode.

According to a seventh aspect of the invention, there is provided a method of manufacturing a thin film transistor, comprising: a first Si thin film having a channel region and source / drain regions formed on both sides of the channel region; In the method for manufacturing a thin film transistor having a gate insulating film formed by the above method, an auxiliary gate electrode and a main gate electrode formed on the gate insulating film, a p-type or n-type
Stacking a third Si thin film or metal thin film doped with a pure substance at a high concentration, and patterning the third Si thin film or metal thin film to form a main gate electrode; Source on gate insulating film
The impurity of the conductivity type opposite to that of the drain region is the third Si thin film
Stacking a second Si thin film doped at a lower concentration than the film, and forming the auxiliary gate electrode by patterning the second Si thin film using a photoresist wider than the main gate electrode as a mask; Implanting impurities into the first Si thin film using the photoresist as a mask to form source / drain regions.

[0025]

The method for manufacturing a thin film transistor according to the invention of claim 8, the first Si thin film forming the source and drain regions on both sides of the channel region and the channel region, in contact the first Si thin film A method of manufacturing a thin film transistor having a gate insulating film formed by the above method, an auxiliary gate electrode and a main gate electrode formed on the gate insulating film, wherein a source / drain region is formed on the gate insulating film.
Stacking a second Si thin film doped with a conductivity type opposite to that of the region , and removing at least a portion of the second Si thin film above a central portion in the width direction of the channel region by etching; p-type or n-type impurities
Laminating a third Si thin film or a metal thin film doped at a higher concentration than the Si thin film at least over the entire surface above the channel region; and using the photoresist as a mask, the second Si thin film and the third Si thin film or the metal thin film. Forming the auxiliary gate electrode and the main gate electrode by patterning the substrate, and implanting impurities into the first Si thin film using the photoresist or the main gate electrode as a mask to form source / drain regions. Things.

According to a ninth aspect of the present invention, there is provided a thin film transistor comprising: an insulating substrate; a first Si thin film formed on the insulating substrate; and a gate insulating film formed in contact with the first Si thin film. A thin film transistor comprising: a gate electrode formed on the gate insulating film; and a channel region and source / drain regions doped with high-concentration impurities on both sides of the channel region in the first Si thin film. A gate electrode comprising a second Si thin film, an auxiliary gate electrode in which the second Si thin film is doped with a conductivity type opposite to the conductivity type of the source / drain region, and a center in the width direction of the auxiliary gate electrode; complement in the area of the part
The main gate electrode is formed by implanting impurities of the same conductivity type as the auxiliary gate electrode at a higher concentration than the impurity concentration of the auxiliary gate electrode.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising the steps of: forming a first Si having a channel region and source / drain regions on both sides of the channel region;
The method of manufacturing a thin film transistor comprising a thin film, a gate insulating film formed in contact with the first Si thin film, and an auxiliary gate electrode and a main gate electrode formed on the gate insulating film. Laminating a second Si thin film on an insulating film, forming the second Si thin film in the shape of the gate electrode using the first photoresist as a mask, and thereafter using the first photoresist as a mask forming a first Si film above the source and drain regions regions by implanting impurities into said first photoresist is removed, the area of the center in the width direction of the gate electrode of the second photoresist as a mask Auxiliary
The same conductivity type impurity with the gate electrode is injected, the gate
A widthwise end portion of the electrode auxiliary gate electrode and the medium
Forming a main gate electrode which is a central portion .

[0029] In the thin film transistor according to the eleventh aspect of the present invention, in the thin film transistor according to the first, second, fourth, sixth, eighth, or tenth aspect, the gate electrode comprising the main gate electrode and the auxiliary gate electrode is at least above the channel region. Two are formed.

[0030]

According to the present invention, claims 1, 2, 4, 6, 8, 1 are provided.
In the thin film transistors 0 and 12, the gate electrode is composed of a main gate electrode for supplying an external signal, and an auxiliary gate electrode which becomes a storage layer when turned on and becomes a depletion layer when turned off. The drain current at the time of off-state is reduced without causing a decrease in the drain current.

If the width of the portion of the auxiliary gate electrode that does not overlap with the main gate electrode is slightly larger than the width of the depletion layer formed in the auxiliary gate electrode at the time of turning off, the effect of reducing the drain current at the time of turning off can be obtained. Has no significant effect. Therefore, the superposition of the main gate electrode and the auxiliary gate electrode does not have to be performed with higher accuracy than in the past.

[0032] Further, according to the present invention,
According to the manufacturing methods of thin film transistors 9 and 11,
Source and drain regions can be formed in a self-aligned manner with respect to the auxiliary gate electrode.

According to the method of manufacturing a thin film transistor according to the fifth aspect of the present invention, it is not necessary to increase the number of masks even if an auxiliary gate electrode is provided.

According to the thin film transistor of the twelfth aspect of the present invention, since a plurality of gate electrodes composed of the main gate electrode and the auxiliary gate electrode are provided, the drain current in the off state is further reduced.

[0035]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the accompanying drawings. In the following description of the drawings, the same portions as those in FIG. 9 are denoted by the same reference numerals.

FIG. 1 is a sectional view showing the structure of one embodiment of the thin film transistor of the present invention. In FIG. 1, a Si thin film 2 acting as a channel is laminated on an insulating substrate 1,
The channel region 5 and the channel region 5 are formed on the Si thin film 2.
The source / drain region 4 is formed on both sides of the substrate by implanting impurities such as phosphorus and arsenic at a high concentration to form an n-type Si thin film. On the gate insulating film 6 formed so as to cover the Si thin film 2, an auxiliary gate electrode 11 obtained by doping a small amount of impurities which becomes p-type into the polycrystalline Si thin film, for example, boron of 10 ¹⁶ cm ⁻³ is formed in the channel region. 5 are formed with the same width. Further, on the auxiliary gate electrode 11, for example, 10
^A main gate electrode 12 made of a polycrystalline Si thin film doped with boron at ²⁰ cm ^-3 is formed.
2, a gate signal is supplied from outside. Further, a contact hole 10 is formed in the gate insulating film 6, and a source electrode 8 and a drain electrode 9, which are metal thin films, are formed in the contact hole 10 so as to make contact with the source / drain regions 4, respectively. It is configured.

Next, the operation of the thin film transistor will be described. First, when the thin film transistor is turned on, that is, when a positive voltage is applied to the main gate electrode 12 with respect to the potential of the source electrode 8, the auxiliary gate electrode 11
Since the storage layer is formed on the gate insulating film 6 side, the auxiliary gate electrode 11 functions as a gate electrode for the channel region 5 between the source / drain regions 4. For this reason, in the case of the ON operation, the thin film transistor does not have an extra resistance component between the channel region 5 and the source / drain region 4 and the drain current at the time of ON does not decrease.

On the other hand, when the thin film transistor is in the off operation, that is, when a negative voltage is applied to the main gate electrode 12 with respect to the potential of the source electrode 8, the auxiliary gate electrode 11 has a gate insulating film 6 side. A depletion layer is formed. If the impurity concentration of the auxiliary gate electrode 11 is set so that the extension of the depletion layer is larger than the thickness of the auxiliary gate electrode 11, the depletion layer in the auxiliary gate electrode 11 at this time Spread throughout. The depletion of the auxiliary gate electrode 11 is equivalent to an increase in the thickness of the gate insulating film 6 in the operation of the thin film transistor. Therefore, when turned off, the auxiliary gate electrode 11 operates as a thin film transistor in which the gate insulating film 6 is added. For this reason, the electric field intensity between the channel region 5 and the source / drain region 4 can be reduced as compared with the case of a gate insulating film having the same thickness, and as a result, the drain current at the time of off can be reduced.

As described above, in the thin film transistor of the present invention, the drain current at the time of off-state can be reduced without lowering the drain current at the time of on-state. Furthermore, in the thin film transistor of the present invention, the entire width of the auxiliary gate electrode 11 functions as a gate electrode to prevent a decrease in the drain current at the time of ON, regardless of the width of the main gate electrode 12 at the time of ON, whereas the auxiliary gate electrode 11 If the width of the portion not overlapping the main gate electrode 12 is slightly larger than the width of the depletion layer formed in the auxiliary gate electrode 11, even if the width slightly varies, there is no significant change in the effect of reducing the drain current at the time of off. . Therefore, in the thin film transistor of the present invention, the main gate electrode 12 and the auxiliary gate electrode 11
It is not necessary to perform the superposition with high accuracy as compared with the related art.

Embodiment 2 FIG. Next, an embodiment of the method for manufacturing a thin film transistor according to the present invention will be described with reference to the manufacturing process sectional views shown in FIGS.

First, as shown in FIG. 2A, a Si thin film 2 serving as a channel is formed on an insulating substrate 1, and then, as shown in FIG. 2B, a gate insulating film 6 made of SiO ₂ is formed. 1200 ° by, for example, thermal oxidation or sputtering.
It is formed with a film thickness of. On the gate insulating film 6, for example, 10
A polycrystalline Si film 11a serving as an auxiliary gate electrode having a thickness of 500 ° doped with boron of ¹⁶ cm ^-3 and having a thickness of, for example, 10 ²⁰ c
As shown in FIG. 2C, a polycrystalline Si film 12a serving as a main gate electrode having a thickness of 2000 ° and doped with boron of m ⁻³ is laminated and formed. The main gate electrode 12 shown in FIG. 2D is formed by patterning the polycrystalline Si film 12a to be the main gate electrode by, for example, dry etching using SF ₆ gas using the photoresist 13 for the main gate electrode as a mask. I do.

Next, as shown in FIG. 2E, a photoresist 14 having a width of, for example, 2 μm on each side from both ends of the main gate electrode 12 is formed so that the main gate electrode 12 is substantially at the center. Using the photoresist 14 as a mask, the polycrystalline Si thin film 11a serving as an auxiliary gate electrode is selectively anisotropically formed with respect to the gate insulating film 6 by dry etching using a source gas obtained by adding O ₂ gas to SF ₆ gas, for example. Auxiliary etching is performed, the auxiliary gate electrode 11 is patterned, and the source / drain region 4 is formed by ion-implanting the auxiliary gate electrode 11 in a self-aligned manner using the same photoresist 14 as a mask. This source / drain region 4 is formed, for example, by 3 ×
This is performed by implanting 10 ¹⁵ cm ^-2 phosphorus or arsenic ions into the Si thin film 2 at an acceleration energy of 80 keV. Next, in order to remove the photoresist 14 and activate impurities in the source / drain regions 4, for example, at 700 ° C.
At 30 ° C. for 30 minutes.

Next, a contact hole 10 is formed in the gate insulating film 6 made of SiO ₂ by, for example, dry etching using CHF ₃ gas as shown in FIG.
A source electrode 8 and a drain electrode 9 are formed in the contact hole 9 by a metal thin film, and are electrically connected to the source / drain regions 4 respectively. Thus, the thin film transistor of the present invention having the sectional structure shown in FIG. 1 is manufactured.

The thin film transistor of the present invention manufactured by the manufacturing method of this embodiment has the source / drain region 4
Are formed in a self-aligned manner using the photoresist 14 for patterning the auxiliary gate electrode 11,
The pattern ends of the auxiliary gate electrode 11 and the source / drain region 4 can be matched. For this reason, the auxiliary gate electrode 11 does not overlap with the source / drain region 4, and the occurrence of a parasitic capacitance or a high-resistance parasitic resistance between the auxiliary gate electrode 11 and the source / drain region 4 is suppressed. Can be.

Embodiment 3 FIG. Next, another embodiment of the thin film transistor and the method of manufacturing the same according to the present invention will be described. FIG. 3A is a cross-sectional view showing a step in the course of the manufacturing process of the present invention, and FIG. 3B is a cross-sectional view showing the structure of the thin-film transistor of the present invention.

The thin film transistor shown in FIG. 3B has a structure in which a region 15 in which impurities in the main gate electrode 12 are diffused is added to the auxiliary gate electrode 11 of the thin film transistor of the first embodiment shown in FIG. .

In this manufacturing method, the photoresist 14 is removed after the step of FIG.
Heat treatment at a temperature of 50 ° C. for 1 hour. By this heat treatment,
At the same time as the activation of the impurities in the source / drain regions 4, boron, which is an impurity in the main gate electrode 12, diffuses into the auxiliary gate electrode 11, and as shown in FIG. A region 15 in which impurities are diffused can be formed. Next, the contact hole 10, the source electrode 8, and the drain electrode 9 are formed in the same manner as in Example 2, whereby the thin film transistor of FIG. 3B is obtained.

In the thin film transistor of this embodiment, the main gate electrode 12 is smaller than the auxiliary gate electrode 11 during the off operation.
The extent of the depletion layer in the region 15 in which the impurities therein are diffused is reduced. Therefore, the electric field intensity between the source / drain region 4 and the channel region 5 is weakened by the auxiliary gate electrode 11, and further, the negative gate is formed in the channel region 5 directly below the region 15 in the main gate electrode 12 where the impurity is diffused. A voltage can be applied effectively, and the drain current at the time of off can be effectively reduced.

In this embodiment, after the manufacturing process of FIG. 2E, a heat treatment for forming the region 15 in which the impurity of the main gate electrode is diffused is performed simultaneously with the activation of the impurity in the source / drain region 4. However, the thin film transistor shown in FIG. 3B can also be formed by performing a heat treatment for diffusion separately from the heat treatment for activation after the manufacturing process of FIG. 2D.

Embodiment 4 FIG. Next, another embodiment of the thin film transistor of the present invention will be described. FIG. 4C is a sectional view showing the structure of a thin film transistor according to another embodiment of the present invention. In this figure, a Si thin film 2 acting as a channel is laminated on an insulating substrate 1, and a channel region 5 and impurities on both sides of the channel region 5 are implanted into the Si thin film 2 at a high concentration to form an n-type Si thin film. Source / drain regions 4 are formed, and a gate insulating film 6 is formed on the Si thin film 2. A main gate electrode 12 for supplying a gate signal from the outside and an auxiliary gate electrode 11 are formed to cover the main gate electrode 12 on the gate insulating film 6 between the source / drain regions 4 made of an n-type Si thin film. Have been. The main gate electrode 12 is made of, for example, a polycrystalline Si film doped with boron at 10 ²⁰ cm ⁻³ , and is formed to be narrower than the space between the source / drain regions 4. The auxiliary gate electrode 11 is formed of a small amount of p-type impurities, for example, 10 ¹⁶
It is made of a polycrystalline Si thin film doped with boron of cm ⁻³ and is patterned to be wider than the main gate electrode 12. Both sides of the portion overlapping the main gate electrode 12 are formed so as to be in contact with the gate insulating film 6. ing. Further, a contact hole 10 is formed in the gate insulating film 6, and a source electrode 8 and a drain electrode 9, which are metal thin films, are formed in the contact hole 10 so as to make contact with the source / drain regions 4, respectively. It is configured.

Next, the operation of the thin film transistor will be described. First, when the thin film transistor is in the ON operation, a storage layer is formed on the side of the gate insulating film 6 of the auxiliary gate electrode 11 in contact with the gate insulating film 6, so that the auxiliary gate electrode 11 is
It functions as a normal gate electrode for the channel region 5 between the drain regions 4. For this reason, in the case of the ON operation, the thin film transistor does not have an extra resistance component between the channel region 5 and the source / drain region 4 and the drain current at the time of ON does not decrease.

On the other hand, when the thin film transistor is turned off, a depletion layer is formed at the interface between the auxiliary gate electrode 11 and the gate insulating film 6. At this time, the auxiliary gate electrode 1
1 is in contact with the gate insulating film 6 and the portion where the depletion layer is formed operates as if the gate insulating film 6 was thicker than the lower part of the main gate electrode 12. Therefore, the auxiliary gate electrode 11
Can weaken the electric field strength between the portion of the channel region 5 in contact with the gate insulating film 6 and the source / drain region 4. Furthermore, in the thin film transistor having this configuration,
The extent of the depletion layer in the main gate electrode 12 can be almost ignored. Therefore, a negative gate voltage can be effectively applied to the channel region 5 immediately below the main gate electrode 12, and as a result, the drain current at the time of off can be effectively reduced.

As described above, in the thin film transistor of the present invention, similarly to the thin film transistor described in the first embodiment, the drain current in the off state can be reduced without lowering the drain current in the on state. The superposition of the gate electrode 12 and the auxiliary gate electrode 11 does not need to be performed with higher precision than in the past. Further, the main gate electrode 12
Are in contact with the gate insulating film 6, the auxiliary gate electrode 1
Even if the film thickness of 1 is larger than the width of the depletion layer, no change occurs in the characteristics of the thin film transistor.

Embodiment 5 FIG. Next, a method of manufacturing a thin film transistor according to a fourth embodiment of the present invention will be described with reference to FIG.
A description will be given along the manufacturing process cross-sectional views of (a) to (c). In this description, steps similar to those in the second embodiment will be simplified, and this embodiment will be described focusing on a characteristic gate electrode forming step.

First, after the step shown in FIG. 2B described in the second embodiment, a polycrystalline 2,000-mm-thick main gate electrode doped with, for example, 10 ²⁰ cm ^-3 of boron is formed on the gate insulating film 6. An Si thin film (third Si thin film) 12a is stacked and formed. The polycrystalline Si thin film 12a serving as the main gate electrode is selectively etched and patterned with respect to the gate insulating film 6 by, for example, dry etching using SF ₆ gas using the photoresist 13 for the main gate electrode as a mask. The main gate electrode 12 shown in FIG.

Next, after laminating a polycrystalline Si thin film (second Si thin film) 11a serving as an auxiliary gate electrode, as shown in FIG. 4B, both sides of the main gate electrode 12 are wider by 2 μm on each side. Photoresist 14 is applied to main gate electrode 12
Is approximately in the center so that the polycrystalline Si
It is formed on the thin film 11a. Using this photoresist 14 as a mask, for example, polycrystalline Si serving as an auxiliary gate electrode is formed by dry etching in which O ₂ gas is added to SF ₆ gas.
The auxiliary gate electrode 11 is patterned by anisotropically etching the thin film 11 a selectively with respect to the gate insulating film 6.
Further, as shown in FIG.
Is used as a mask to ion-implant the auxiliary gate electrode 11 in a self-aligned manner to form the source / drain regions 4.

Next, a contact hole 10 is formed in the gate insulating film 6, a source electrode 8 and a drain electrode 9 are formed in the contact hole 10 by a thin metal film, and the present invention has a cross-sectional structure shown in FIG. A thin film transistor is manufactured.

According to the manufacturing method of this embodiment, Embodiment 2
Similarly, the source / drain region 4 has the auxiliary gate electrode 11
Can be formed in a self-aligned manner. The main gate electrode 12 and the auxiliary gate electrode 11 are formed of SiO _{2 of the} gate insulating film 6.
Can be manufactured with good reproducibility.

Embodiment 6 FIG. FIG. 5C is a sectional view showing the structure of a thin film transistor according to another embodiment of the present invention. As shown in this figure, a Si thin film 2 serving as a channel is stacked on an insulating substrate 1, and a channel region 5 and impurities on both sides of the channel region 5 are implanted into the Si thin film 2 at a high concentration to form an n-type film. Source and drain regions 4 are formed as Si thin films, and a gate insulating film 6 is formed on the Si thin film 2. On the gate insulating film 6 between the source / drain regions 4, an auxiliary gate electrode 11 and this auxiliary gate electrode 1
Main gate electrode 1 formed by ion implantation at the center of 1
6 are formed. The main gate electrode 16 formed by this ion implantation is formed in the auxiliary gate electrode 11 obtained by doping a polycrystalline Si film with a p-type impurity, for example, boron of 10 ¹⁶ cm ⁻³ at an acceleration voltage of, for example, 30 keV and 3 × 10 ¹⁵ c.
It is formed by ion implantation of m ^-2 boron ions. A contact hole 10 is formed in the gate insulating film 3, and a source electrode 8 and a drain electrode 9, which are thin metal films, are formed in the contact hole 10.
Each is configured to contact the source / drain region 4.

The thin-film transistor of the present invention is similar to that of the fourth embodiment.
As in the case of the thin film transistor described above, the drain current at the time of off can be reduced without reducing the drain current at the time of on. Further, the main gate electrode 16 is formed by ion implantation.
Can be formed, so that the steps of film formation and etching are not required.

Embodiment 7 FIG. Next, a method of manufacturing a thin film transistor according to a sixth embodiment of the present invention will be described with reference to FIG.
A description will be given along the manufacturing process cross-sectional views of (a) to (c). In this description, steps similar to those in the second embodiment will be simplified, and this embodiment will be described focusing on a characteristic gate electrode forming step.

[0062] First, after the step shown in FIG. 2 described in Example 2 (b), the auxiliary gate electrode having a thickness of 2000Å doped with boron of the gate insulating film 6 on the example 10 ¹⁶ cm ^-3 polycrystalline An Si thin film (second Si thin film) 11a is stacked and formed. Polycrystalline Si serving as this auxiliary gate electrode
Using the film 11a as a mask with the photoresist 13, for example, S
The auxiliary gate electrode 11 shown in FIG. 5A is formed by selectively anisotropically etching and patterning the gate insulating film 3 by dry etching in which O ₂ gas is added to F ₆ gas. Further, the source / drain regions 4 are formed by ion-implanting the auxiliary gate electrode 11 in a self-aligned manner using the same photoresist 13 as a mask.

Next, as shown in FIG. 5B, a photoresist 18 is formed on portions other than the inside of the auxiliary gate electrode 11 by 2 μm on each side from both ends from the center. Using this photoresist 18 as a mask, for example, boron
The main gate electrode 16 is formed by ion implantation at 3 × 10 ¹⁵ cm ⁻² at an acceleration voltage of eV.

Next, a contact hole 10 is formed in the gate insulating film 6, and a source electrode 8 and a drain electrode 9 made of a metal thin film are formed in the contact hole 10, thereby forming a book having a structural cross section shown in FIG. The thin film transistor of the invention is manufactured.

The thin film transistor of the present invention manufactured by the manufacturing method of this embodiment has a
The drain region 4 can be formed in a self-aligned manner with respect to the auxiliary gate electrode 11.

In this embodiment, the source / drain region 4 is formed, and then the main gate electrode 16 formed by ion implantation is formed. However, after the main gate electrode 16 formed by ion implantation is formed, the source / drain region 4 is formed. 4 may be formed.

Embodiment 8 FIG. FIG. 6C is a sectional view showing the structure of a thin film transistor according to another embodiment of the present invention. In FIG. 6C, an Si thin film 2 serving as a channel is laminated on an insulating substrate 1, and a channel region 5 and impurities on both sides of the channel region 5 are implanted into the Si thin film 2 at a high concentration to form an n-type. Source and drain regions 4 are formed as Si thin films, and a gate insulating film 6 is formed on the Si thin film 2. Gate insulating film 6 between source / drain regions 4 made of n-type Si thin film
On the main gate electrode 12, a main gate electrode 12 patterned so as to correspond to both outer ends of the auxiliary gate electrode 11 with a substantially central portion between the source and drain regions 4 removed is formed. Further, a contact hole 10 is formed in the gate insulating film 6, and a source electrode 8 and a drain electrode 9 made of a metal thin film are formed in the contact hole 10 so as to make contact with the source / drain region 4, respectively. It is configured.

The thin-film transistor of the present invention is similar to that of the fourth embodiment.
As in the case of the thin film transistor described above, the drain current at the time of off can be reduced without reducing the drain current at the time of on.

Embodiment 9 FIG. Next, an example of a method for manufacturing a thin film transistor according to an eighth embodiment of the present invention will be described with reference to FIG.
A description will be given along the manufacturing process cross-sectional views of (a) to (c). In this description, steps similar to those in the second embodiment will be simplified, and this embodiment will be described focusing on a characteristic gate electrode forming step.

Firstly, after the step shown in FIG. 2 described in Example 2 (b), the auxiliary gate electrode having a thickness of 1000Å doped with boron of the gate insulating film 6 on the example 10 ¹⁶ cm ^-3 polycrystalline An Si film (second Si thin film) 11a is stacked and formed. Part of the polycrystalline Si film 11a serving as the auxiliary gate electrode above the channel region 5 is selectively etched with respect to the gate insulating film 6 by, for example, dry etching using SF ₆ gas, as shown in FIG. The main gate electrode forming groove 17 is provided by patterning as shown. Next, a polycrystalline Si film (third Si thin film) serving as a main gate electrode is laminated on the polycrystalline Si film 11a serving as the auxiliary gate electrode and in the main gate electrode formation groove 17. Thereafter, using the photoresist 13 as a mask, for example, SF ₆ gas and O
_By dry etching using _two gases, a polycrystalline Si film (third Si thin film) serving as a main gate electrode and a polycrystalline Si film 11a serving as an auxiliary gate electrode are simultaneously selectively anisotropic with respect to the gate insulating film 6. The main gate electrode 12 and the auxiliary gate electrode 11 having the structure shown in FIG. Further, the source / drain regions 4 are formed by ion-implanting the auxiliary gate electrode 11 in a self-aligned manner using the same photoresist 13 as a mask.

Next, a contact hole 10 is formed in the gate insulating film 6, and a source electrode 8 and a drain electrode 9 made of a metal thin film are formed in the contact hole 10, thereby forming a book having a structural cross section shown in FIG. The thin film transistor of the invention is manufactured.

According to the manufacturing method of this embodiment, the second embodiment
Similarly, the source / drain region 4 has the auxiliary gate electrode 11
Can be formed in a self-aligned manner. Further, since the etching of the main gate electrode 12 is performed simultaneously with the etching of the auxiliary gate electrode 11, the structure of the thin film transistor of the present invention can be manufactured with good reproducibility.

In the above description of the first to eleventh embodiments, the case where the main gate electrode 12 is made of a polycrystalline Si film has been described. However, a metal thin film of Mo, Ta, W, Cr or the like may be used. The same effects as those of the thin film transistors of the embodiments described above can be obtained. In this case, the thin film transistor of the present invention can be manufactured in a similar manufacturing process by changing the etching of the main gate electrode 12 described in the embodiment of the manufacturing method to an etching method selected according to the metal thin film.

Embodiment 10 FIG. Next, another embodiment of the method of manufacturing the thin film transistor shown in the first embodiment and the third embodiment will be described with reference to the process sectional views of FIGS. 7A to 7C. In this description, the main gate electrode 12 is formed using a metal thin film such as Mo. Embodiment 2 or Embodiment 4
Steps similar to those described above are simplified, and this embodiment will be described focusing on a characteristic gate electrode forming step.

[0075] First, after the step shown in FIG. 2 described in Example 2 (b), the auxiliary gate electrode having a thickness of 500Å doped with boron of the gate insulating film 6 on the example 10 ¹⁶ cm ^-3 polycrystalline An Si film 11a and a metal thin film serving as a main gate electrode, for example, a Mo film are stacked. Next, photoresist 1
3 is used as a mask, and a Mo film serving as a main gate electrode is subjected to wet etching to make a polycrystalline Si film serving as an auxiliary gate electrode.
In this wet etching, the Mo film is side-etched to form the main gate electrode 12 narrower than the photoresist 13 by, for example, 2 μm on each side, as shown in FIG. 7A.

Next, as shown in FIG. 7B, using the same photoresist 13 as a mask, for example, O ₂ gas is added to SF ₆ gas.
Dry etching is performed with a source gas to which the gas is added, and the auxiliary gate electrode 11 is patterned by selectively anisotropically etching the polycrystalline Si thin film 11 a serving as the auxiliary gate electrode with respect to the gate insulating film 6. Further, FIG.
As shown in FIG. 5, the source / drain regions 4 are formed by ion-implanting the auxiliary gate electrode 11 in a self-aligned manner using the same photoresist 13 as a mask. Thereafter, through the same manufacturing process as in the second or fourth embodiment, the thin film transistor of the present invention having the same structure as that shown in FIG. 1 or FIG. 3B is manufactured.

According to the method of manufacturing a thin film transistor of this embodiment, the patterning of the main gate electrode 12 and the patterning of the auxiliary gate electrode 11 can be performed using the same photoresist 13, so that one mask can be reduced and
No alignment between the main gate electrode 12 and the auxiliary gate electrode 11 is required. At the same time, the source / drain regions 4 can be formed in a self-aligned manner with respect to the auxiliary gate electrode 11.

Although a metal thin film is used for the main gate electrode 12 in this embodiment, a polycrystalline Si film doped at a higher concentration than the auxiliary gate electrode 11 may be used.

Embodiment 11 FIG. Next, another embodiment of the thin film transistor of the present invention will be described. FIG. 8 is a sectional view showing the structure of a thin film transistor according to another embodiment of the present invention. The gate electrode structure including the main gate electrode 12 and the auxiliary gate electrode 11 described in the first embodiment between source / drain regions 4 is shown. Two are installed.

According to the thin film transistor of this embodiment,
The electric field strength between the channel region 5 and the source / drain region 4 can be reduced during the off operation without lowering the drain current at the on time, and the channel region 5 at the portion between the two main gate electrodes 12 has a resistance. As a component, the drain current at the time of off can be effectively reduced.

Although the gate electrode structure of the first embodiment is used in this embodiment, it goes without saying that the same effect can be obtained by using the gate electrode structure of another embodiment.

In the embodiment described above, the case where the conductivity type of the main gate electrode 12 is the same as the conductivity type of the auxiliary gate electrode 11 has been described. However, the conductivity type opposite to the auxiliary gate electrode 11 may be used. When the impurity concentration is higher than that of the auxiliary gate electrode 11, the same effect can be obtained. Furthermore, although the case of an n-type thin film transistor has been described, a p-type thin film transistor may be used, and if the conductivity type of the auxiliary gate electrode 11 is opposite to that of the source / drain region 4, the n-type thin film transistor may be used. The same effect as in the case is obtained. Further, in the embodiment, the thin film transistor using the polycrystalline Si film has been described.
A thin film transistor using an amorphous Si film may be used, and the same effect is obtained.

[0083]

As described above, the thin film transistor of the present invention is provided with the auxiliary gate electrode as the gate electrode.
There is an effect that the drain current at the time of off can be reduced without causing a decrease in the drain current at the time of on. Further, even if the main gate electrode and the auxiliary gate electrode are displaced from each other, the characteristics of the thin film transistor hardly change, so that there is an effect that it is not necessary to perform the mask alignment with high accuracy.

Further, according to the method of manufacturing a thin film transistor of the present invention, there is an effect that the source / drain region can be formed in a self-aligned manner with respect to the auxiliary gate electrode.

In the method of manufacturing a thin film transistor according to the fifth aspect of the present invention, in addition to the above-described operation, there is no need to increase the number of masks due to the provision of the auxiliary gate electrode, and the positions of the main gate electrode and the auxiliary gate electrode There is an effect that it can be manufactured without performing alignment.

In the thin film transistor according to the twelfth aspect of the present invention, there is an effect that the drain current in the off state can be more effectively reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process sectional view for explaining a method of manufacturing a thin film transistor according to Embodiment 2 of the present invention;

FIG. 3 is a sectional view for illustrating a method for manufacturing a thin film transistor according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a thin film transistor according to a fourth embodiment of the present invention and a method for manufacturing the fifth embodiment.

FIG. 5 is a cross-sectional view for describing a thin film transistor according to a sixth embodiment of the present invention and a method of manufacturing the seventh embodiment.

FIG. 6 is a cross-sectional view for explaining a thin-film transistor according to an eighth embodiment of the present invention and a method for manufacturing the ninth embodiment;

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the thin-film transistor according to the tenth embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining a thin film transistor and a method for manufacturing the same according to Embodiment 11 of the present invention;

FIG. 9 is a sectional view of a conventional thin film transistor.

FIG. 10 is a cross-sectional view illustrating a conventional thin film transistor and a method for manufacturing the same.

[Description of Signs] 1 Insulating substrate 2 First Si thin film 3 Low concentration impurity region 4 Source / drain region 5 Channel region 6 Gate insulating film 7 Gate electrode 8 Source electrode 9 Drain electrode 10 Contact hole 11 Auxiliary gate electrode 11a Auxiliary Polycrystalline Si film serving as a gate electrode (second S
i thin film) 12 main gate electrode 12a polycrystalline Si film (third Si film) to be a main gate electrode
13 Photoresist 14 Photoresist 15 Region in which impurities of main gate electrode are diffused 16 Main gate electrode formed by ion implantation 17 Main gate electrode formation groove 18 Photoresist

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yuichi Masutani 8-1-1, Tsukaguchi-Honmachi, Amagasaki-shi Mitsubishi Electric Corporation Materials and Devices Laboratory (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (11)

(57) [Claims] An insulating substrate, a first Si thin film formed on the insulating substrate, a gate insulating film formed in contact with the first Si thin film, and a gate insulating film formed on the gate insulating film A thin film transistor comprising a gate electrode, wherein a channel region is formed on the first Si thin film, and a source / drain region doped with a high concentration impurity on both sides of the channel region. An auxiliary gate electrode made of a second Si thin film doped with a conductivity type opposite to the above conductivity type, and a third Si thin film doped with a p-type or n-type impurity at a higher concentration than the auxiliary gate electrode, or A source / drain region comprising a main gate electrode made of a metal thin film;
The vicinity of the gate main electrode is
A thin film transistor, which is located at a position farther than a portion near an auxiliary gate electrode . 2. An auxiliary gate electrode is provided in contact with a gate insulating film, and a main gate electrode is laminated on the auxiliary gate electrode and formed to be narrower than the width of the auxiliary gate electrode. Item 2. The thin film transistor according to item 1. 3. A first Si thin film having a channel region and source / drain regions formed on both sides of the channel region.
In a method of manufacturing a thin film transistor including a gate insulating film formed in contact with the first Si thin film, an auxiliary gate electrode and a main gate electrode formed on the gate insulating film, a source electrode may be formed on the gate insulating film. Drain region
Second Si thin film and p doped with opposite conductivity type and
-Type or n-type impurities are doped at a higher concentration than the second Si thin film.
Forming in succession a second 3 Si thin film or metal thin film which is Doping, forming a main gate electrode by patterning the first 3 Si thin film or metal thin film, the wider than the main gate electrode Patterning the second Si thin film using a photoresist as a mask to form an auxiliary gate electrode; and implanting impurities into the first Si thin film using the photoresist as a mask to form source / drain regions. A method for manufacturing a thin film transistor. 4. The auxiliary gate electrode has the same structure as the main gate electrode.
Conductivity type claims second term thin film transistor according to impure was characterized by the formation of the regions obtained by diffusing the. 5. A first Si thin film having a channel region and source / drain regions formed on both sides of the channel region.
In a method of manufacturing a thin film transistor including a gate insulating film formed in contact with the first Si thin film, an auxiliary gate electrode and a main gate electrode formed on the gate insulating film, a source electrode may be formed on the gate insulating film. Drain region
The second Si thin film and the p-type or n-type impurities doped to the opposite conductivity type have a higher concentration than the second Si thin film.
Forming a third Si thin film or a metal thin film doped on the substrate, and isotropic etching using a photoresist having a shape of an auxiliary gate electrode formed on the third Si thin film or the metal thin film as a mask A step of forming the main gate electrode, a step of forming the auxiliary gate electrode by anisotropic etching using the photoresist as a mask, and a step of implanting impurities into the first Si thin film using the photoresist as a mask. Forming a thin film transistor. 6. The semiconductor device according to claim 1, wherein the main gate electrode is narrower than the channel region width and is provided in contact with the gate insulating film, and the auxiliary gate electrode is provided in contact with the gate insulating film outside the main gate electrode. Item 2. The thin film transistor according to item 1. 7. A first Si thin film having a channel region and source / drain regions formed on both sides of the channel region.
In a method of manufacturing a thin film transistor including a gate insulating film formed in contact with the first Si thin film, an auxiliary gate electrode and a main gate electrode formed on the gate insulating film, a p-type film is formed on the gate insulating film. Or n-type impurities
Stacking a third Si thin film or metal thin film in which a substance is doped at a high concentration, and patterning the third Si thin film or metal thin film to form a main gate electrode;
After that, the source / drain is formed on the main gate electrode and the gate insulating film.
The impurity of the conductivity type opposite to that of the rain region is the third Si thin film.
Laminating a second Si thin film doped at a lower concentration, patterning the second Si thin film using a photoresist wider than the main gate electrode as a mask, and forming the auxiliary gate electrode; Forming a source / drain region by injecting impurities into the first Si thin film using a photoresist as a mask. 8. A first Si thin film having a channel region and source / drain regions formed on both sides of the channel region.
In a method of manufacturing a thin film transistor including a gate insulating film formed in contact with the first Si thin film, an auxiliary gate electrode and a main gate electrode formed on the gate insulating film, a source electrode may be formed on the gate insulating film. Drain region
A second Si thin film doped with opposite conductivity type laminated with a step of removing by etching a portion of the upper central portion of at least the width direction of the channel region of the second Si thin film, p thereafter Or n-type impurities
Laminating a third Si thin film or a metal thin film doped at a higher concentration than the Si thin film at least over the entire surface above the channel region; and using the photoresist as a mask to remove the second Si thin film and the third Si thin film or the metal thin film. Patterning the auxiliary gate electrode and the main gate electrode, and implanting impurities into the first Si thin film using the photoresist or the main gate electrode as a mask to form source / drain regions. A method for manufacturing a thin film transistor, comprising: 9. An insulating substrate, a first Si thin film formed on the insulating substrate, a gate insulating film formed in contact with the first Si thin film, and a gate formed on the gate insulating film A thin film transistor comprising an electrode, wherein a channel region is formed on the first Si thin film, and a source / drain region doped with a high concentration impurity on both sides of the channel region. become a the second Si thin film on the source and drain regions of the conductivity type opposite to the conductivity type doped auxiliary gate electrode, the auxiliary gate region <br/> the center in the width direction of the auxiliary gate electrode A thin film transistor, comprising: a main gate electrode into which an impurity of the same conductivity type as the electrode is implanted at a higher concentration than the impurity concentration of the auxiliary gate electrode. 10. A first Si thin film having a channel region and source / drain regions formed on both sides of the channel region, a gate insulating film formed in contact with the first Si thin film, and a gate insulating film formed on the first Si thin film. A method of manufacturing a thin film transistor having a gate electrode composed of an auxiliary gate electrode and a main gate electrode formed in the step of: laminating a second Si thin film on the gate insulating film; Forming a source / drain region by implanting impurities into the first Si thin film using the first photoresist as a mask; removing the first photoresist, the auxiliary gate region of the center in the width direction of the gate electrode of the second photoresist as a mask
Inject impurities of the same conductivity type as the electrode and
Auxiliary gate electrode and center part at both ends in width direction
Forming a main gate electrode, the method comprising: 11. The semiconductor device according to claim 1, wherein at least two gate electrodes comprising a main gate electrode and an auxiliary gate electrode are formed above the channel region. 11. The thin film transistor according to item 8, or item 10.