JP3092186B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor formed on a transparent insulating substrate and effective for application to a liquid crystal display, an image scanner and the like.

[0002]

2. Description of the Related Art FIGS. 3A to 3D show a conventional general method of manufacturing an inverted staggered thin film transistor.
First, as shown in FIG. 3A, a semiconductor layer 302 serving as a gate electrode is formed on an insulating substrate 301 and patterned. After that, the gate insulating film 303 and the semiconductor layer 304 serving as an active region are stacked, and the result is shown in FIG. Next, after stacking and patterning a semiconductor layer to which a high-concentration impurity is added, a source region and a drain region 305 are formed.
An interlayer insulating film 306 is laminated, and a contact hole 3
07, and a source electrode terminal 308 and a drain electrode terminal 309 are formed to complete the process. This state is shown in FIG.
It is.

[0003] The thin film transistor thus formed is applied to a liquid crystal display device, a memory and the like.

[0004]

In the above-mentioned prior art, a semiconductor layer doped with a high concentration of impurities is used for forming the source and drain regions. However, when this method is used, the source and drain regions are not formed. The overlap of the gate electrodes
A parasitic capacitance is formed, and a high-speed thin film transistor cannot be realized. In addition, the characteristics of the formed thin film transistor vary due to misalignment of the mask and the like, and it has been difficult to form a uniform thin film transistor.

On the other hand, in the characteristics of the thin film transistor,
In order to achieve low power consumption and high speed, reduction of off-state current, that is, reduction of leak current has been an issue. As one of means for solving this, it is considered to provide a region where the gate electrode and the drain region do not overlap, that is, an offset region, on the drain side. However, in this case, since this offset region cannot be formed in a self-aligned manner, variations in characteristics and parasitic capacitance occur due to misalignment of the mask. Therefore, in the above-described conventional technique, it is difficult to form the offset region in a self-aligned manner in the inverted staggered thin film transistor.

In recent years, along with the high integration of thin film transistors, miniaturization and miniaturization of elements have been promoted. At this time, a problem is a short channel effect. Shortening the channel causes an increase in off-state current and a decrease in sub-threshold voltage. This has been an obstacle to miniaturization of the device.

The present invention solves the problem of a method of manufacturing an inverted staggered thin film transistor formed on such a transparent insulating substrate. The object of the present invention is to form source and drain regions. It is an object of the present invention to provide a highly reliable method for manufacturing a thin film transistor, in which the offset region is provided in a self-aligned manner, which can achieve high speed, high performance, and low power consumption.

[0008]

SUMMARY OF THE INVENTION The present invention comprises a step of forming a gate electrode on a substrate, a step of forming a gate insulating film on the gate electrode, and a step of forming a semiconductor layer on the gate insulating film. Forming a resist on the semiconductor layer by exposing from the back side of the substrate using a gate electrode as a mask, and implanting impurities obliquely into the semiconductor layer using the resist as a mask to form source / drain regions. And forming an offset region.

[0009]

FIG. 1 is a view showing one embodiment of the present invention in a method of manufacturing a thin film transistor in the order of manufacturing steps. First, as shown in FIG.
A semiconductor layer 102 to which a high-concentration impurity to be a gate electrode is added is laminated to a thickness of about 1000 to 3000
After patterning, a gate insulating film 103 is
The layers are laminated at a thickness of about 0 to 2000 mm. For the gate insulating film 103, a silicon dioxide film, a silicon nitride film, or the like is formed and used by a normal pressure CVD method, a low pressure CVD method, a plasma CVD method, an ECR plasma CVD method, an optical CVD method, or a combination thereof. You. Then, after laminating a semiconductor layer 104 over the entire surface of the gate insulating film 103 using a phosphine or disilane gas by a low pressure CVD method, a plasma CVD method, or the like, a positive resist 105 is applied, and a back side of the transparent insulating substrate 101 is formed. FIG. 1 (b) is obtained by performing the exposure and etching. Next, FIG.
As shown in (c), the impurity 1 is obliquely above the transparent insulating substrate 101 by using an ion implantation method such as an ion implantation method or an ion doping method.
06 to activate the impurity,
Source and drain regions 107 are formed. Thereafter, the positive resist 105 is removed, and the interlayer insulating film 10 is formed on the entire surface.
8 and then removing the interlayer insulating film 108 at the portion where the source and drain electrodes are to be formed to form a contact hole 109, and then forming a source electrode 110 and a drain electrode 111 at that portion, as shown in FIG. Complete. As the interlayer insulating film 108, a polyimide or the like may be used in addition to an insulating film formed by a method similar to the method used in forming the gate insulating film 103. In this embodiment, a semiconductor layer to which a high concentration impurity is added is used as the gate electrode layer 102. However, as another method, an ion implantation method In addition, there is a method in which an impurity is introduced into the stacked semiconductor layers to form a gate electrode.

FIG. 2 is a diagram showing current-voltage characteristics of a thin film transistor formed according to an embodiment of the present invention. The solid line A is the current-voltage characteristic of the thin film transistor formed according to the present invention, and the broken line B is the current-voltage characteristic of the thin film transistor formed according to the above-described conventional technique. Since the thin film transistor formed according to the present invention has an offset structure, the on-state current is slightly reduced, but the off-state current is further significantly reduced. Therefore, the on / off ratio was also improved.

The amount of offset depends on the thickness of the positive resist used as a mask when forming the source and drain regions, and the incident angle when ion-implanting impurities. The amount can be controlled freely. In recent years, high integration has been advanced and the size of a thin film transistor has been reduced. However, when a thin film transistor is formed by the method of the present invention, a thin impurity layer is formed between a source and drain region and a channel portion, The short channel effect can be reduced.

[0012]

As described briefly above, according to the method for manufacturing a thin film transistor of the present invention, many effects described above can be obtained.

1. Since the source and drain regions are formed in a self-aligned manner, there is no need to consider the misalignment of the mask and the like, and the variation in characteristics between the thin film transistors is extremely small.

2. Since the number of masks to be used is as small as three, it is advantageous for cost reduction.

3. The off-state current is small due to the offset structure, so that current can be easily held and power consumption can be reduced. Also, the on / off ratio increases,
Speeding up is also possible.

4. A resist is used as a mask used for forming the source and drain regions, and the offset amount can be controlled by changing the resist film thickness even when the angle at which impurities are implanted is constant.

5. When a resist is used as a mask used for forming the source and drain regions, and the film thickness of the resist is constant, the offset amount can be controlled by changing the angle at which impurities are implanted.

6. A thin impurity layer can be provided between the source and drain regions and the channel portion, whereby a short channel effect can be reduced, and thus, a thin film transistor can be miniaturized.

By the many effects described above, a high-speed, high-performance, low power consumption, and highly reliable thin film transistor can be constructed.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views of a thin film transistor shown in an embodiment of the present invention in each manufacturing process.

FIG. 2 is a diagram showing a comparison between current-voltage characteristics of a thin film transistor shown in an example of the present invention and current-voltage characteristics of a thin film transistor shown in the prior art of the present invention.

FIGS. 3A to 3C are cross-sectional views of a conventional inverted staggered thin film transistor for each manufacturing process.

[Explanation of symbols]

 101, 301: Transparent insulating substrate 102, 302 ... Gate electrode 103, 303 ... Gate insulating film 104, 304 ... Semiconductor layer 105 ... Positive resist 106 ... Impurities 107, 305 ..Source and drain regions 108 and 306 interlayer insulating films 109 and 307 contact holes 110 and 308 source electrodes 111 and 309 drain electrodes

Claims (1)

(57) [Claims] A step of forming a gate electrode on the substrate; a step of forming a gate insulating film on the gate electrode; and a step of forming a semiconductor layer on the gate insulating film.
A step of forming a resist on the semiconductor layer by performing exposure from the back side of the substrate using a gate electrode as a mask, and forming source / drain regions by obliquely implanting impurities into the semiconductor layer using the resist as a mask And forming an offset region.