JP2602589B2 - Method for manufacturing LDD transistor - Google Patents

Method for manufacturing LDD transistor

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Publication number
JP2602589B2
JP2602589B2 JP3158627A JP15862791A JP2602589B2 JP 2602589 B2 JP2602589 B2 JP 2602589B2 JP 3158627 A JP3158627 A JP 3158627A JP 15862791 A JP15862791 A JP 15862791A JP 2602589 B2 JP2602589 B2 JP 2602589B2
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Japan
Prior art keywords
film
forming
polycrystalline silicon
impurity layer
semiconductor substrate
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JP3158627A
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Japanese (ja)
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JPH04233238A (en
Inventor
政 錫 丘
Original Assignee
エル・ジー・セミコン・カンパニー・リミテッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明はＬＤＤ（ライトリー ド
ープト ドレイン（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒ
ａｉｎ））トランジスタの製造方法に関し、特に接合容
量及びボデーエフェクト並びに短チャネル効果を減少す
るのに適したＬＤＤトランジスタの製造方法に関する。BACKGROUND OF THE INVENTION This invention is LDD (lightly doped drain (L ightly D oped D r
It relates to a manufacturing method of ain)) transistor capacitor, a method of manufacturing a LDD transistor motor particularly suitable to reduce the junction capacitance and the body effect and the short channel effect.

【０００２】[0002]

【従来の技術】従来のＬＤＤトランジスタの構造を図８
及び図９に示す。2. Description of the Related Art The structure of a conventional LDD transistor is shown in FIG.
And FIG.

【０００３】図８は、従来のＬＤＤトランジスタの第１
の例を示す断面図である。このトランジスタを作製する
には、まず、Ｐ型シリコン基板１上にゲート酸化膜３を
形成し、その上に多結晶シリコンを堆積してゲート電極
４を形成する。次に、シリコン基板１に硼素と燐をそれ
ぞれイオン注入して、Ｐ型不純物層６とＮ型低濃度不純
物層７を形成する。次に、酸化膜を堆積した後、リアク
ティブ イオン エッチングを行ってゲート電極４の両
側に側壁酸化膜１１を形成し、その後、シリコン基板１
に砒素をイオン注入してＮ型高濃度不純物層８を形成し
て作製する。FIG. 8 shows a first example of a conventional LDD transistor.
It is sectional drawing which shows the example of. To manufacture this transistor, first, a gate oxide film 3 is formed on a P-type silicon substrate 1, and polycrystalline silicon is deposited thereon to form a gate electrode 4. Next, boron and phosphorus are ion-implanted into the silicon substrate 1 to form a P-type impurity layer 6 and an N-type low concentration impurity layer 7. Next, after depositing an oxide film, reactive ion etching is performed to form sidewall oxide films 11 on both sides of the gate electrode 4.
Then, arsenic is ion-implanted to form an N-type high-concentration impurity layer 8.

【０００４】図９は、従来のＬＤＤトランジスタの第２
の例を示す断面図である。このトランジスタを作製する
には、まず、Ｐ型シリコン基板１にマスクを用いてチャ
ネル部分のみに硼素イオンを注入してＰ型不純物層１２
を形成した後、半導体基板１上にゲート酸化膜３を形成
し、その上に多結晶シリコンを堆積してゲート電極４を
形成する。次に、シリコン基板１に燐をイオン注入して
Ｎ型低濃度不純物層７を形成し、次に、酸化膜を堆積し
た後、リアクティブ イオン エッチングを実施してゲ
ート電極４の両側に側壁酸化膜１１を形成し、その後、
Ｐ型シリコン基板１に砒素をイオン注入してＮ型高濃度
不純物層８を形成して作製する。FIG. 9 shows a second conventional LDD transistor.
It is sectional drawing which shows the example of. In order to fabricate this transistor, first, boron ions are implanted only into the channel portion of the P-type silicon substrate 1 using a mask to form the P-type impurity layer 12.
Is formed, a gate oxide film 3 is formed on the semiconductor substrate 1, and polycrystalline silicon is deposited thereon to form a gate electrode 4. Next, phosphorus is ion-implanted into the silicon substrate 1 to form an N-type low-concentration impurity layer 7, then, after depositing an oxide film, reactive ion etching is performed to oxidize the sidewalls on both sides of the gate electrode 4. After forming the film 11,
Arsenic is ion-implanted into a P-type silicon substrate 1 to form an N-type high-concentration impurity layer 8 for fabrication.

【０００５】[0005]

【発明が解決しようとする課題】このような従来のＬＤ
Ｄトランジスタにおいては、トランジスタを微細化する
に従って短チャネル効果が生じ、パンチスルーを起こし
やすくなる。これを改善するために、図８に示すよう
に、ソース・ドレイン領域であるＮ型低濃度不純物層
７、Ｎ型高濃度不純物層８の周辺にＰ型不純物層６を設
けるか、図９に示すように、チャネル部分にＰ型不純物
層１２を設ける方法がある。SUMMARY OF THE INVENTION Such a conventional LD
In a D transistor, as the transistor is miniaturized, a short channel effect occurs, and punch-through easily occurs. In order to improve this, as shown in FIG. 8, a P-type impurity layer 6 is provided around the N-type low-concentration impurity layer 7 and the N-type high-concentration impurity layer 8 which are source / drain regions, or FIG. As shown, there is a method of providing a P-type impurity layer 12 in a channel portion.

【０００６】しかし、Ｐ型不純物層６を設ける場合に
は、Ｐ型不純物層６の存在によって、Ｎ型高濃度不純物
層８とＰ型基板１間の接合容量が増加するという問題が
ある。However, when the P-type impurity layer 6 is provided, there is a problem that the presence of the P-type impurity layer 6 increases the junction capacitance between the N-type high-concentration impurity layer 8 and the P-type substrate 1.

【０００７】一方、チャネル部分にＰ型不純物層１２を
設ける場合には、閾値電圧Ｖｔには限度があるので、不
純物の濃度を高めるのに限度がある。更に、適当な閾値
電圧Ｖｔを維持するとしても、ボデーエフェクト（Ｂｏ
ｄｙ Ｅｆｆｅｃｔ：バックバイアスによる閾値電圧Ｖ
ｔの変化）が大きくなるという問題がある。On the other hand, when the P-type impurity layer 12 is provided in the channel portion, the threshold voltage Vt has a limit, so that there is a limit in increasing the impurity concentration. Further, even if an appropriate threshold voltage Vt is maintained, the body effect (Bo
dy Effect: threshold voltage V due to back bias
(change in t) becomes large.

【０００８】本発明の目的は、ソース・ドレイン領域と
基板間の接合容量を減少するとともに、ボデーエフェク
トおよび短チャネル効果を減らして、動作速度を向上し
たＬＤＤトランジスタの製造方法を提供することにあ
る。An object of the present invention is to reduce the junction capacitance between the source and drain regions and the substrate, to reduce the body effect and the short-channel effect, to provide a manufacturing method of the LDD transistor capacitor with improved operating speed is there.

【０００９】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明のＬＤＤトランジスタの製造方法は、第１導
電型の半導体基板上にフィールド酸化膜を形成する工程
と、上記半導体基板上に第１多結晶シリコン膜、窒化
膜、第２多結晶シリコン膜からなる積層体を選択的に形
成する工程と、上記積層体の側壁に側壁酸化膜を形成す
る工程と、上記工程を経た上記半導体基板上に第３多結
晶シリコン膜を形成した後、該第３多結晶シリコン膜に
不純物をドープする工程と、上記積層体上から上記フィ
ールド酸化膜上に至る部分を残して、上記第３多結晶シ
リコン膜を除去する工程と、上記工程を経た上記半導体
基板上をホトレジスト膜で覆い、上記第３多結晶シリコ
ン膜の頂部が露出するまでエッチバックする工程と、上
記窒化膜が露出するまで上記第３多結晶シリコン膜と上
記第２多結晶シリコン膜とをエッチングする工程と、上
記側壁酸化膜をエッチングにより除去する工程と、上記
ホトレジスト膜を除去した後、上記側壁酸化膜があった
箇所の上記半導体基板に不純物をドープして、第１導電
型不純物層と、上記第１導電型と逆の導電型の第２導電
型低濃度不純物層とをそれぞれ形成する工程と、上記工
程を経た上記半導体基板上に絶縁膜を形成した後、熱処
理を行って、ドーピングされた上記第３多結晶シリコン
膜から不純物を拡散させて上記半導体基板に第２導電型
高濃度不純物層を形成する工程と、上記第３多結晶シリ
コン膜上にコンタクト孔を設け、そこに導電膜を堆積し
て電気的接続をとる工程とを含むことを特徴とする。[Means for Solving the Problems] In order to achieve the above purpose
According to the method of manufacturing an LDD transistor of the present invention , a field oxide film is formed on a semiconductor substrate of a first conductivity type, and a first polysilicon film, a nitride film, and a second polysilicon film are formed on the semiconductor substrate. Selectively forming a film stack, forming a side wall oxide film on the side wall of the stack, forming a third polycrystalline silicon film on the semiconductor substrate after the above steps, Doping the third polycrystalline silicon film with an impurity, removing the third polycrystalline silicon film while leaving a portion extending from above the stacked body to above the field oxide film; Covering the substrate with a photoresist film and etching back until the top of the third polycrystalline silicon film is exposed; and etching the third polycrystalline silicon film and the second polycrystalline silicon until the nitride film is exposed. Etching the film, removing the sidewall oxide film by etching, removing the photoresist film, and then doping impurities into the semiconductor substrate where the sidewall oxide film was located, thereby forming a first conductive film. Forming a second impurity layer and a second conductivity type low-concentration impurity layer having a conductivity type opposite to the first conductivity type, and forming an insulating film on the semiconductor substrate having undergone the above-described process. Forming a second conductivity type high concentration impurity layer in the semiconductor substrate by diffusing impurities from the doped third polycrystalline silicon film; and providing a contact hole on the third polycrystalline silicon film. And depositing a conductive film thereon to establish an electrical connection.

【００１０】この場合、上記第３多結晶シリコンにドー
プする不純物として燐または砒素を用いることを特徴と
する。In this case, phosphorus or arsenic is used as an impurity to be doped into the third polycrystalline silicon.

【００１１】またこの場合、上記第１導電型不純物層を
形成するための不純物として硼素またはＢＦ2を用いる
ことを特徴とする。In this case, boron or BF 2 is used as an impurity for forming the first conductivity type impurity layer.

【００１２】[0012]

【作用】第１導電型高濃度不純物層が、ゲートに隣接す
る部分にのみ存在するので、ソース・ドレイン領域と基
板間の接合容量が減少するとともに、ボデーエフェクト
が減少する。Since the first conductivity type high-concentration impurity layer exists only in the portion adjacent to the gate, the junction capacitance between the source / drain region and the substrate is reduced, and the body effect is reduced.

【００１３】第２導電型高濃度不純物層の上面に接して
多結晶シリコン膜が設けられており、該多結晶シリコン
膜の上面に接して導電膜が設けられているので、半導体
基板の第２導電型高濃度不純物領域と多結晶シリコン膜
との間、及び、該多結晶シリコン膜と導電膜との間の電
気的接続が形成される。A polycrystalline silicon film is provided in contact with the upper surface of the second conductivity type high concentration impurity layer, and a conductive film is provided in contact with the upper surface of the polycrystalline silicon film. An electrical connection is formed between the conductive high-concentration impurity region and the polycrystalline silicon film, and between the polycrystalline silicon film and the conductive film.

【００１４】また、第２導電型高濃度不純物層の上面に
接して多結晶シリコン膜が設けられているので、多結晶
シリコン膜と接続するための導電膜形成に際し、多結晶
シリコン膜との接続が良好になされるように導電膜をア
ライメントすることが可能となる。Further, since the polycrystalline silicon film is provided in contact with the upper surface of the second-conductivity-type high-concentration impurity layer, when forming the conductive film for connecting to the polycrystalline silicon film, the polycrystalline silicon film is connected to the polycrystalline silicon film. It is possible to align the conductive film so that the satisfactorily performed.

【００１５】第２導電型高濃度不純物層は、半導体基板
の表面に直接接して形成されている多結晶シリコン膜か
ら不純物を拡散させて形成するので、その形成が容易で
あり、かつ、第２導電型低濃度不純物層の厚さよりも薄
く形成することが可能である。The second-conductivity-type high-concentration impurity layer is formed by diffusing impurities from a polycrystalline silicon film formed directly in contact with the surface of the semiconductor substrate. It can be formed thinner than the thickness of the conductive type low concentration impurity layer.

【００１６】また、第２導電型高濃度不純物層の厚さ
を、第２導電型低濃度不純物層の厚さよりも薄くするこ
とにより短チャンネル効果が減少する。Further, the short channel effect is reduced by making the thickness of the second conductivity type high concentration impurity layer smaller than the thickness of the second conductivity type low concentration impurity layer.

【００１７】[0017]

【実施例】本実施例の一実施例であるＬＤＤトランジス
タの製造工程断面図を図１〜図７に示し、その製造方法
及び構造を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 7 are cross-sectional views showing a manufacturing process of an LDD transistor according to an embodiment of the present invention, and a manufacturing method and a structure thereof will be described.

【００１８】図１に示すように、Ｐ型シリコン基板１上
に窒化膜１３を堆積した後、マスクを用いてフィールド
酸化膜２を形成する部分の窒化膜１３をエッチングによ
り除去し、その場所にフィールド酸化膜２を形成する。As shown in FIG. 1, after a nitride film 13 is deposited on a P-type silicon substrate 1, a portion of the nitride film 13 where a field oxide film 2 is to be formed is removed by etching using a mask. A field oxide film 2 is formed.

【００１９】次に、図２に示すように、窒化膜１３を除
去した後、ゲート酸化膜３を形成し、その上に、第１多
結晶シリコン膜４ａ、窒化膜１４、及び、第２多結晶シ
リコン膜４ｂを順次堆積し、マスクを用いてパターニン
グして積層体を形成する。Next, as shown in FIG. 2, after the nitride film 13 is removed, a gate oxide film 3 is formed, on which a first polysilicon film 4a, a nitride film 14, and a second polysilicon film 14 are formed. A crystalline silicon film 4b is sequentially deposited and patterned using a mask to form a laminate.

【００２０】次に、図３に示すように、公知の方法によ
り、上記積層体の両側に側壁酸化膜１１を形成した後、
ドーピングしてない第３多結晶シリコン膜５を堆積し、
その後、例えば砒素または燐のような不純物を第３多結
晶シリコン膜５にイオン注入する。Next, as shown in FIG. 3, after a sidewall oxide film 11 is formed on both sides of the laminate by a known method,
Depositing an undoped third polycrystalline silicon film 5,
After that, an impurity such as arsenic or phosphorus is ion-implanted into the third polysilicon film 5.

【００２１】次に、図４に示すように、マスクを用い
て、上記積層体上からフィールド酸化膜２に至る部分を
残して、第３多結晶シリコン膜５を除去し、次に、ホト
レジスト膜１５で覆った後、第３多結晶シリコン膜５が
現われるまでエッチバックして平坦化する。Next, as shown in FIG. 4, the third polycrystalline silicon film 5 is removed by using a mask, leaving a portion extending from the above-mentioned laminate to the field oxide film 2, and then a photoresist film is formed. After covering with 15, the third polycrystalline silicon film 5 is flattened by etching back until it appears.

【００２２】次に、図５に示すように、窒化膜１４が現
われるまで第２多結晶シリコン膜４ｂと、第３多結晶シ
リコン膜５の一部とを、エッチングして除去する。Next, as shown in FIG. 5, the second polysilicon film 4b and a part of the third polysilicon film 5 are removed by etching until the nitride film 14 appears.

【００２３】次に、図６に示すように、側壁酸化膜１１
をエッチングして除去し、ホトレジスト膜１５を除去し
た後、側壁酸化膜１１があった箇所のシリコン基板１
に、例えば硼素またはＢＦ2のような不純物をイオン注
入してＰ型不純物層６を形成したうえで、砒素または燐
のような不純物をイオン注入してＮ型低濃度不純物層７
を形成する。Next, as shown in FIG.
Is removed by etching, and the photoresist film 15 is removed.
Then, an impurity such as boron or BF 2 is ion-implanted to form a P-type impurity layer 6, and then an impurity such as arsenic or phosphorus is ion-implanted to form an N-type low-concentration impurity layer 7.
To form

【００２４】次に、図７に示すように、ＳＯＧ、ＢＰＳ
Ｇ等からなる絶縁膜９を形成し、熱処理を行って、第３
多結晶シリコン膜５から不純物を拡散させ、Ｎ型低濃度
不純物層７よりも厚さが薄いＮ型高濃度不純物層８を形
成する。次に、第３多結晶シリコン膜５の上の絶縁膜９
の部分にコンタクト孔を設け、そこに導電膜１０を堆積
して電気的接続をとり、ＬＤＤトランジスタを形成す
る。Next, as shown in FIG.
An insulating film 9 made of G or the like is formed, and heat treatment is performed .
Impurities are diffused from the polycrystalline silicon film 5 to form an N-type high-concentration impurity layer 8 thinner than the N-type low-concentration impurity layer 7. Next, the insulating film 9 on the third polycrystalline silicon film 5
Is provided with a contact hole, and a conductive film 10 is deposited there to make an electrical connection to form an LDD transistor.

【００２５】上記のように作製したＬＤＤトランジスタ
においては、高濃度のＰ型不純物層６が、ゲート電極で
ある第１多結晶シリコン膜４ａに隣接する部分にのみ存
在するので、ソース・ドレイン領域であるＮ型高濃度不
純物層８と基板１間の接合容量を減少するとともに、ボ
デーエフェクトが減少する。また、Ｎ型高濃度不純物層
８の厚さが、Ｎ型低濃度不純物層７の厚さよりも薄いの
で、短チャネル効果が減少する。In the LDD transistor manufactured as described above, the high-concentration P-type impurity layer 6 exists only in the portion adjacent to the first polycrystalline silicon film 4a serving as the gate electrode. The junction capacitance between a certain N-type high-concentration impurity layer 8 and the substrate 1 is reduced, and the body effect is reduced. Further, since the thickness of the N-type high-concentration impurity layer 8 is smaller than the thickness of the N-type low-concentration impurity layer 7, the short channel effect is reduced.

【００２６】[0026]

【発明の効果】以上説明したように、本発明のＬＤＤト
ランジスタの製造方法によれば、ソース・ドレイン領域
と基板間の接合容量の減少、ボデーエフェクトの減少、
短チャネル効果の減少が可能となり、トランジスタの動
作特性の向上と、チップの動作速度の向上が可能となる
という効果が有る。 As described above, the LDD transistor of the present invention
According to the method of manufacturing a transistor, the junction capacitance between the source / drain region and the substrate is reduced , the body effect is reduced ,
Short-channel effects can be reduced, and the operating characteristics of transistors and the operating speed of chips can be improved.
There is an effect that.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例であるＬＤＤトランジスタの
製造工程を説明するための半導体装置の製造工程断面図
である。1 is a manufacturing process sectional views of a semiconductor device for explaining a higher manufacturing processes of the LDD transistor which is one embodiment of the present invention.

【図２】本発明の一実施例であるＬＤＤトランジスタの
製造工程を説明するための半導体装置の製造工程断面図
である。2 is a manufacturing process sectional views of a semiconductor device for explaining a higher manufacturing processes of the LDD transistor which is one embodiment of the present invention.

【図３】本発明の一実施例であるＬＤＤトランジスタの
製造工程を説明するための半導体装置の製造工程断面図
である。3 is a manufacturing process sectional views of a semiconductor device for explaining a higher manufacturing processes of the LDD transistor which is one embodiment of the present invention.

【図４】本発明の一実施例であるＬＤＤトランジスタの
製造工程を説明するための半導体装置の製造工程断面図
である。4 is a manufacturing process sectional views of a semiconductor device for explaining a higher manufacturing processes of the LDD transistor which is one embodiment of the present invention.

【図５】本発明の一実施例であるＬＤＤトランジスタの
製造工程を説明するための半導体装置の製造工程断面図
である。5 is a manufacturing process sectional views of a semiconductor device for explaining a higher manufacturing processes of the LDD transistor which is one embodiment of the present invention.

【図６】本発明の一実施例であるＬＤＤトランジスタの
製造工程を説明するための半導体装置の製造工程断面図
である。6 is a manufacturing process sectional views of a semiconductor device for explaining a higher manufacturing processes of the LDD transistor which is one embodiment of the present invention.

【図７】本発明の一実施例であるＬＤＤトランジスタの
製造工程を説明するための半導体装置の製造工程断面図
である。7 is a manufacturing process sectional views of a semiconductor device for explaining a higher manufacturing processes of the LDD transistor which is one embodiment of the present invention.

【図８】従来のＬＤＤトランジスタの断面図の第１例で
ある。FIG. 8 is a first example of a sectional view of a conventional LDD transistor.

【図９】従来のＬＤＤトランジスタの断面図の第２例で
ある。FIG. 9 is a second example of a sectional view of a conventional LDD transistor.

【符号の説明】[Explanation of symbols]

１ Ｐ型シリコン基板 ２ フィールド酸化膜 ３ ゲート酸化膜 ４ ゲート電極 ４ａ 第１多結晶シリコン膜 ４ｂ 第２多結晶シリコン膜 ５ 第３多結晶シリコン膜 ６ Ｐ型不純物層 ７ Ｎ型低濃度不純物層 ８ Ｎ型高濃度不純物層 ９ 絶縁膜 １０ 導電膜 １１ 側壁酸化膜 １２ Ｐ型不純物層 １３，１４ 窒化膜 １５ ホトレジスト膜Reference Signs List 1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode 4 a First polycrystalline silicon film 4 b Second polycrystalline silicon film 5 Third polycrystalline silicon film 6 P-type impurity layer 7 N-type low-concentration impurity layer 8 N-type high concentration impurity layer 9 insulating film 10 conductive film 11 sidewall oxide film 12 P-type impurity layers 13, 14 nitride film 15 e Torejisuto film

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】第１導電型半導体基板上にフィールド酸化
膜を形成する工程と、上記半導体基板上に第１多結晶シ
リコン膜、窒化膜、第２多結晶シリコン膜からなる積層
体を選択的に形成する工程と、上記積層体の側面に側壁
酸化膜を形成する工程と、上記工程を経た上記半導体基
板上に第３多結晶シリコン膜を形成した後、該第３多結
晶シリコン膜に不純物をドープする工程と、上記積層体
から上記フィールド酸化膜上に至る部分を残して、上記
第３多結晶シリコン膜を除去する工程と、上記工程を経
た上記半導体基板上をホトレジスト膜で覆い、上記第３
多結晶シリコン膜の頂部が露出するまでエッチバックす
る工程と、上記窒化膜が露出するまで上記第３多結晶シ
リコン膜と上記第２多結晶シリコン膜とをエッチングす
る工程と、上記側壁酸化膜をエッチングにより除去する
工程と、上記ホトレジスト膜を除去した後、上記側壁酸
化膜があった箇所の上記半導体基板に不純物をドープし
て、第１導電型不純物層と、上記第１導電型と逆の導電
型の第２導電型低濃度不純物層とをそれぞれ形成する工
程と、上記工程を経た上記半導体基板上に絶縁膜を形成
した後、熱処理を行って、ドーピングされた上記第３多
結晶シリコン膜から不純物を拡散させて上記半導体基板
に第２導電型高濃度不純物層を形成する工程と、上記第
３多結晶シリコン膜上にコンタクト孔を設け、そこに導
電膜を堆積して電気的接続をとる工程とを含むことを特
徴とするＬＤＤトランジスタの製造方法。A step of forming a field oxide film on a semiconductor substrate of a first conductivity type, and selectively forming a laminate of a first polysilicon film, a nitride film and a second polysilicon film on the semiconductor substrate. Forming a sidewall oxide film on the side surface of the stacked body, forming a third polysilicon film on the semiconductor substrate after the above-described process, and then adding an impurity to the third polysilicon film. Doping, removing the third polycrystalline silicon film while leaving a portion from the laminate to the field oxide film, and covering the semiconductor substrate after the above process with a photoresist film, Third
Etching back until the top of the polycrystalline silicon film is exposed; etching the third polycrystalline silicon film and the second polycrystalline silicon film until the nitride film is exposed; Removing the photoresist film by etching, and after removing the photoresist film, doping impurities into the semiconductor substrate where the side wall oxide film was located, thereby forming a first conductivity type impurity layer and a first conductivity type opposite to the first conductivity type. Forming a second conductive type low-concentration impurity layer of a conductive type, forming an insulating film on the semiconductor substrate having undergone the above-described process, and then performing a heat treatment on the doped third polycrystalline silicon film. Forming a second-conductivity-type high-concentration impurity layer on the semiconductor substrate by diffusing impurities from the substrate; and forming a contact hole on the third polycrystalline silicon film, and depositing a conductive film on the contact hole. Method for producing a LDD transistor which comprises the step of taking a connection. 【請求項２】上記第３多結晶シリコンにドープする不純
物として燐または砒素を用いることを特徴とする請求項
１記載のＬＤＤトランジスタの製造方法。2. A claim which comprises using the phosphorus or arsenic as an impurity doped in the third polysilicon
2. The method for manufacturing an LDD transistor according to item 1 . 【請求項３】上記第１導電型不純物層を形成するための
不純物として硼素またはＢＦ2を用いることを特徴とす
る請求項１記載のＬＤＤトランジスタの製造方法。3. The process for producing an LDD transistor according to claim 1, wherein the use of boron or BF 2 as an impurity for forming the first conductive type impurity layer.
JP3158627A 1990-06-30 1991-06-28 Method for manufacturing LDD transistor Expired - Fee Related JP2602589B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019900009896A KR930011031B1 (en) 1990-06-30 1990-06-30 Ldd structure and manufacturing method thereof
KR90-9896 1990-06-30

Publications (2)

Publication Number Publication Date
JPH04233238A JPH04233238A (en) 1992-08-21
JP2602589B2 true JP2602589B2 (en) 1997-04-23

Family

ID=19300752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3158627A Expired - Fee Related JP2602589B2 (en) 1990-06-30 1991-06-28 Method for manufacturing LDD transistor

Country Status (3)

Country Link
JP (1) JP2602589B2 (en)
KR (1) KR930011031B1 (en)
DE (1) DE4121456C2 (en)

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Publication number Priority date Publication date Assignee Title
KR20010000789A (en) * 2000-10-19 2001-01-05 김주연 Manufacturing Method of Elvan Contain Synthesize Resin Molding

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442589A (en) * 1981-03-05 1984-04-17 International Business Machines Corporation Method for manufacturing field effect transistors
EP0071335B1 (en) * 1981-07-27 1986-10-15 Xerox Corporation Field effect transistor
EP0083447B1 (en) * 1981-12-30 1989-04-26 Thomson Components-Mostek Corporation Triple diffused short channel device structure
JPS60263468A (en) * 1984-06-12 1985-12-26 Toshiba Corp Manufacture of semiconductor device
US4697198A (en) * 1984-08-22 1987-09-29 Hitachi, Ltd. MOSFET which reduces the short-channel effect
EP0227971A1 (en) * 1985-12-17 1987-07-08 Siemens Aktiengesellschaft MOS transistor with a short gate for highly integrated circuits, and method for its production
DE3737144A1 (en) * 1986-11-10 1988-05-11 Hewlett Packard Co Metal-oxide semiconductor field-effect transistor (MOSFET) and method for producing it

Also Published As

Publication number Publication date
JPH04233238A (en) 1992-08-21
KR920001743A (en) 1992-01-30
KR930011031B1 (en) 1993-11-19
DE4121456C2 (en) 1996-08-29
DE4121456A1 (en) 1992-01-09

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