JPH0521789A - Field effect type transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a MOS transistor with an improved reliability by controlling a short-channel phenomenon even if dimensions of the transistor become small. CONSTITUTION:A groove 17 for channel is dug on a silicon substrate 11 and a gate electrode 13 is formed on the groove 17 through a ground gate oxide film 12. Then, impurity diffusion regions 15 and 16 which become source/drain are formed in self-alignment manner with this gate electrode 13 as a mask, thus enabling a MOS transistor with a longer channel than mask dimensions when patterning the gate to be formed and enabling a short-channel effect to be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor capable of suppressing a short channel phenomenon and a manufacturing method thereof.

[0002]

2. Description of the Related Art LDD (Lightly
Doped drain structure field effect transistor (hereinafter,
A MOS transistor) is constructed as shown in the sectional view of FIG. 3, and the gate oxide film and the gate electrode of the transistor are formed on a flat silicon substrate. In FIG. 3, reference numeral 1 is a silicon substrate, 2 is a gate oxide film, 3 is a gate electrode, 4 is an overlay oxide film, 5 is a sidewall, 6 is a low-concentration impurity diffusion region of a conductivity type opposite to that of the silicon substrate 1, 7 Is a high-concentration impurity diffusion region of the opposite conductivity type to the silicon substrate 1, and a method of manufacturing the transistor will be described with reference to FIG.

In FIG. 4, first, a silicon substrate 1 of, for example, P type as one conductivity type is prepared.
An oxide film covering the entire surface is deposited. Then, on the oxide film, a polysilicon film containing phosphorus or the like having an opposite conductivity type to the silicon substrate 1, that is, N type impurities is deposited.
Moreover, after depositing an oxide film on this polysilicon film, as shown in FIG. 4A, by patterning these, the gate oxide film 2, the gate electrode 3 of the transistor,
The overlay oxide film 4 is formed. Further, impurities such as phosphorus are ion-implanted into the silicon substrate 1 using these as a mask to form a low-concentration impurity diffusion region 6 serving as a source / drain (hereinafter abbreviated as S / D) region of the transistor ( Figure 4 (b)).

After that, as shown in FIG. 4 (c), an oxide film is deposited over the entire surface of the silicon substrate, and then selectively patterned by anisotropic etching to form sidewalls 5. Is ion-implanted to form a high-concentration impurity diffusion region 7 to be the S / D region of the transistor. As a result, the MOS transistor having the LDD structure as shown in FIG. 3 is completed.

[0005]

However, in such a conventional MOS transistor, when the gate length of the transistor is shortened due to the demand for high integration, a threshold voltage called a short channel phenomenon of the MOS transistor is obtained. V _th and S / D breakdown voltage are reduced, and
There is a problem that the transistor cannot operate normally.

The present invention has been made in order to solve the above-mentioned problems, and even if the size of the transistor is reduced, the short channel phenomenon is suppressed and the reliability is improved.
It is an object to provide an OS transistor and a manufacturing method thereof.

[0007]

In order to achieve the above object, a MOS transistor according to the present invention has a groove for a channel formed on a semiconductor substrate of one conductivity type by using a photoengraving technique, and the groove is formed on the groove. It is possible to form a transistor having a channel length longer than the mask size of the gate by forming a gate electrode via a gate insulating film and forming a source / drain region in a self-aligned manner using this gate electrode as a mask. Characterize.

Further, in the method of manufacturing a MOS transistor according to the present invention, a channel groove is formed on a semiconductor substrate of one conductivity type by a photolithography technique, and a gate electrode is formed on the groove via a base gate insulating film. After that, the method is characterized by including a step of forming source / drain regions in a self-aligned manner using the gate electrode as a mask.

[0009]

In the present invention, since the channel of the MOS transistor is formed along the groove on the semiconductor substrate, S
MO with channel length longer than the distance between the / D diffusion layers
It becomes possible to form an S transistor and suppress the short channel phenomenon.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a structural sectional view showing an embodiment of a MOS transistor according to the present invention, and FIG. 2 is a process sectional view showing a procedure of a manufacturing method thereof. In FIG. 1, reference numeral 11 is a silicon substrate, 12 is a gate oxide film, 13 is a gate electrode, 1
4 is an overlay oxide film, and 15 and 16 are silicon substrates 1 respectively.
A low-concentration impurity diffusion region having a conductivity type opposite to that of 1 and a high-concentration impurity diffusion region, and 17 are channel grooves on the silicon substrate 11.

That is, in the MOS transistor of this embodiment, a concave groove 17 to be a channel of the transistor is formed on a P-type silicon substrate 11 by using an ordinary photolithography technique, and the groove 17 is formed in the groove 17. Oxide film 12, gate electrode 13 and overlay oxide film 1 so that
4 are sequentially laminated and formed. And this overlay oxide film 1
N in a self-aligned manner using the gate electrode 13 containing 4 as a mask.
Type impurities are ion-implanted to form an S / D low-concentration impurity diffusion region 15 and a high-concentration impurity diffusion region 16 which are sequentially laminated to form a MO having a double diffusion structure as shown in FIG.
The S transistor is formed.

Next, a method of manufacturing the MOS transistor of this embodiment will be described with reference to FIG. First, a P-type recon substrate 11 is prepared, and a MOS is formed by using an ordinary photoengraving technique.
A concave groove 17 is dug in a portion which will be a channel of the transistor (FIG. 2 (a)). Then, a first oxide film, N-type polysilicon, and a second oxide film are sequentially deposited over the entire surface of the silicon substrate 11 including the groove 17, and then they are patterned to form a gate on the concave groove 17. An oxide film 12, a gate electrode 13, and an overlay oxide film 14 are formed (FIG. 2 (b)).

Further, N-type impurities such as phosphorus are ion-implanted into the silicon substrate 11 using these as a mask to form a low-concentration impurity diffusion region 15, and then impurities such as arsenic are injected to highly-concentrate impurities. By forming the diffusion region 16 (FIG. 2 (c)), a MOS transistor having a double diffusion structure S / D as shown in FIG. 1 is completed.

As described above, according to the MOS transistor of the above-described embodiment, the concave groove 17 for the channel is provided on the silicon substrate 11, and the gate oxide film 12, the gate electrode 13, and the overlay oxide film 14 are formed in the groove 17. Allows the MOS of the channel longer than the dimension when the gate is patterned.
A transistor can be obtained. Therefore, the short channel effect can be suppressed. In addition, the S / D diffusion layer is composed of a low-concentration impurity diffusion region 15 and a high-concentration impurity diffusion region 16.
Since it has a heavy diffusion structure, the electric field strength near the drain can be further relaxed.

[0015]

As described above, according to the present invention, a trench for a channel is formed on a semiconductor substrate such as silicon, and a gate electrode is formed above the trench through a gate insulating film to form a MOS transistor. Since the channel region of is changed from a planar one to a three-dimensional one, it becomes possible to form a MOS transistor having a channel longer than the size of the mask when patterning the gate electrode. The short channel phenomenon can be suppressed. Therefore, _Vth deterioration can be prevented, and the S / D breakdown voltage can be improved, which is an excellent effect in improving the reliability of the MOS device.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a MOS transistor according to the present invention.

FIG. 2 is a process sectional view showing a procedure of the manufacturing method.

FIG. 3 is a sectional view showing the structure of a conventional MOS transistor.

FIG. 4 is a process cross-sectional view showing the procedure of the manufacturing method.

[Explanation of symbols]

11 Silicon substrate 12 Gate oxide film 13 Gate electrode 14 Overlay oxide film 15 Low concentration impurity diffusion region 16 High concentration impurity diffusion region 17 Channel groove on silicon substrate

Claims (2)

[Claims] 1. A groove for a channel formed on a semiconductor substrate of one conductivity type by using a photoengraving technique, and a gate electrode formed in the groove via a gate insulating film so as to fill the groove. A field effect transistor, comprising: a source / drain region formed in a self-aligned manner on a semiconductor substrate using the gate electrode as a mask. 2. A step of forming a groove to be a channel of a transistor by a photolithography technique on a semiconductor substrate of one conductivity type, and an insulating film on the semiconductor substrate in which the groove is formed,
A step of sequentially depositing and patterning a polysilicon film for a gate, and then forming a gate electrode only above a groove on the semiconductor substrate via a gate insulating film; and using this gate electrode as a mask, self-alignment on the semiconductor substrate And a step of selectively forming a source / drain region.