CN112614881B - Novel high-speed high-isolation pHEMT microwave switch chip - Google Patents

Novel high-speed high-isolation pHEMT microwave switch chip Download PDF

Info

Publication number
CN112614881B
CN112614881B CN202011477475.1A CN202011477475A CN112614881B CN 112614881 B CN112614881 B CN 112614881B CN 202011477475 A CN202011477475 A CN 202011477475A CN 112614881 B CN112614881 B CN 112614881B
Authority
CN
China
Prior art keywords
electrode
gate
grid electrode
auxiliary
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011477475.1A
Other languages
Chinese (zh)
Other versions
CN112614881A (en
Inventor
黄永锋
殷玉喆
刘伟
何力
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Zhixin Electronic Technology Co ltd
Original Assignee
Chengdu Zhixin Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Zhixin Electronic Technology Co ltd filed Critical Chengdu Zhixin Electronic Technology Co ltd
Priority to CN202011477475.1A priority Critical patent/CN112614881B/en
Publication of CN112614881A publication Critical patent/CN112614881A/en
Application granted granted Critical
Publication of CN112614881B publication Critical patent/CN112614881B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses a novel high-speed high-isolation pHEMT microwave switch chip, which comprises a substrate layer, wherein a semiconductor layer is arranged on the substrate layer, the semiconductor layer is formed by a plurality of stacked semiconductor sublayers, a source electrode, a drain electrode and a grid electrode are arranged at the top of the semiconductor layer, the grid electrode is positioned between the source electrode and the drain electrode, gaps are respectively reserved between the source electrode and the grid electrode and between the drain electrode and the grid electrode, and two grid electrode side wall regions are formed; and arranging an auxiliary grid electrode on the side wall region of at least one grid electrode, wherein the auxiliary grid electrode is realized by an air bridge or a buried auxiliary grid electrode. The switch chip disclosed by the invention can be switched on and off without counteracting the obstruction of surface charges and interface trap electrostatic potential to channel current through the charging and discharging processes of the LC network of the grid electrode and the drain electrode, and has the advantages of high speed, high isolation degree, long service life, good broadband characteristic, low power consumption, high efficiency and the like.

Description

Novel high-speed high-isolation pHEMT microwave switch chip
Technical Field
The invention relates to the field of semiconductors, in particular to a novel high-speed high-isolation pHEMT microwave switch chip.
Background
Microwave switches are widely used in modern communication systems such as transceiver modules. The existing microwave switch has two technologies: one is a mechanical switch, and the on-off of a mechanical arm is controlled by an electric control to control the switch of a microwave channel; the other is a chip switch, and the on-off of a transistor in the chip is controlled by electric control to control the switch of a microwave channel.
The advantages of mechanical switches over chip switches: the isolation is high and can reach more than 60dB, and the chip switch can only reach about 20 dB. Therefore, the mechanical switch is widely applied to the fields of instruments and meters and the like which need high isolation, high sensitivity, precision measurement and the like.
The advantages of chip switches over mechanical switches: the volume is small, the integration is easy, and the switching speed is high. The chip switches have a transistor with the size of about 100 microns, so that a plurality of switches can be cascaded on a chip conveniently and can be integrated with other control circuits and microwave circuits. This is not done with mechanical switches. And because the chip switch is used for electrically controlling the on-off of the chip transistor to realize the microwave switch function, the speed is far higher than that of a mechanical switch. The mechanical switch switching needs about 100 milliseconds, and the chip switch can realize the switching speed within 10 ms. Therefore, the chip switch is widely applied to modern communication systems with high requirements on volume and integration degree, such as a multichannel transceiving chip/module, 5G, wifi and the like.
The on-chip switches may be implemented on a variety of types of chips, with different substrates, typically of the type GaAs, gaN, inP, bulk silicon CMOS-RF, SOI-RF, etc. The chip switch with the novel structure also comprises a micro electro mechanical system MEMS chip switch.
Besides the MEMS chip switch, several other microwave switches have the same structure, and typically compound semiconductor switches such as GaAs, gaN, etc. are chip switches of pHEMT transistor type. The basic structure of this switch is a pHEMT transistor, which mainly includes a substrate and structures of gate, drain, source, etc., a typical GaAs pHEMT structure is shown in fig. 1, and a silicon-based compound semiconductor transistor is similar to this.
The undoped InGaAs layer forms a heterojunction with the AlGaAs layer at the interface, creating a two-dimensional electron gas. The grid controls the height of a potential barrier, and when the grid reaches a certain bias voltage, the two-dimensional electron gas tunnel passes through the potential barrier to form current between the source electrode and the drain electrode. To prevent current leakage into the GaAs substrate, an undoped GaAs/AlGaAs superlattice buffer layer is added.
The principle of the pHEMT structure transistor switch chip based on the prior art is: when no control voltage is applied to the gate, the barrier of the gate prevents the two-dimensional electron gas current of the source from flowing to the drain, and the switch is in an off state. When the control voltage is applied to the gate, the potential barrier of the gate is lowered, the two-dimensional electron gas current of the source is not blocked to flow to the drain any more, and the switch is in an open state. There are two factors that determine pHEMT switching speed and isolation:
(1) Gate control region
The two-dimensional electron gas in the part of the area is directly controlled by the grid, and current can rapidly flow from the source electrode to the drain electrode in the channel. The physical characteristics of the pHEMT transistor determine that the time required for current migration in this portion is short and is not a major factor affecting switching speed and isolation.
(2) Side wall region of gate electrode
The two-dimensional electron gas in the partial area is controlled by the grid electrode, but is weaker, and is also controlled by surface charges accumulated on the side wall area of the grid electrode and electrostatic potential of an interface trap. In the equilibrium state, the two-dimensional electron movement is hindered by the external electrostatic potentials. When the switch is turned on, the external electrostatic potential is counteracted through the LC charging effect of the source electrode and the drain electrode, so that the two-dimensional electron gas moves. This process is relatively slow due to the delay effect of the LC charging, and is a major factor affecting pHEMT switching speed and isolation.
Because the isolation of the pHEMT switch is far weaker than that of a mechanical arm of the mechanical switch, the isolation of the chip switch is far weaker than that of the mechanical switch, and the application of the chip switch is seriously influenced. Meanwhile, the pHEMT switching speed is limited, so that the performances of advanced wireless communication systems such as a related high-speed AD/DA sampling circuit and 5G/Wifi6 are seriously influenced.
The pHEMT transistor is a planar microwave structure manufactured on a chip, so the pHEMT transistor is a planar structure, mainly for facilitating the manufacturing process of a semiconductor chip, and the structural characteristics of the prior art are as follows: the gate is formed as a plurality of fingers inserted between the source and drain. A typical GaAs pHEMT transistor layout design is shown in fig. 2.
Disclosure of Invention
The invention aims to: aiming at the existing problems, a novel high-speed high-isolation pHEMT microwave switch chip is provided to improve the switching speed and isolation of the switch chip.
The technical scheme adopted by the invention is as follows:
a novel high-speed high-isolation pHEMT microwave switch chip comprises a substrate layer, wherein a semiconductor layer is arranged on the substrate layer and consists of a plurality of stacked semiconductor sublayers, a source electrode, a drain electrode and a grid electrode are arranged at the top of the semiconductor layer, the grid electrode is positioned between the source electrode and the drain electrode, gaps are respectively reserved between the source electrode and the grid electrode and between the drain electrode and the grid electrode, and two grid electrode side wall regions are formed; an auxiliary gate is provided on at least one gate sidewall region.
The auxiliary grid can inhibit surface charges and interface traps of a side wall area of the grid electrode, so that the impedance of the surface charges and the electrostatic potential of the interface traps to channel current is counteracted without passing through the LC network charging and discharging process of the grid electrode and the drain electrode when the pHEMT transistor is switched.
Preferably, the air bridge provided at the sidewall region of the gate forms an auxiliary gate.
Preferably, the auxiliary grid is led out from the same side, the opposite side or the upper part of the grid stage leading-out circuit.
Preferably, the auxiliary gate is a buried auxiliary gate.
Preferably, the buried auxiliary gate functions as an auxiliary gate through the buried metal layer.
Preferably, the metal layer is disposed between the semiconductor layer and the substrate layer, or between adjacent semiconductor sublayers.
Preferably, the auxiliary grid is led out from the same side or the opposite side of the grid electrode leading-out circuit.
Preferably, the buried auxiliary gate is connected to a back gate electrode disposed on the back surface of the substrate through a metalized via.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. the novel high-speed high-isolation pHEMT microwave switch chip disclosed by the invention has the advantages that the obstruction of surface charges and interface trap electrostatic potential to channel current is counteracted in the charging and discharging processes of an LC network of a grid electrode and a drain electrode during switching, so that the switching speed is high and the isolation is high.
2. The novel high-speed high-isolation pHEMT microwave switch chip does not need to be charged frequently in the switching process, cannot be aged or damaged due to Schottky contact of a source electrode and a drain electrode, and is long in service life.
3. The novel high-speed high-isolation pHEMT microwave switch chip has the characteristics of good broadband characteristic, low power consumption and high efficiency.
Drawings
The invention will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 is a GaAs pHEMT substrate structure.
Fig. 2 is a conventional pHEMT switch layout.
Fig. 3 is a vertical structure diagram of an auxiliary gate implemented based on an air bridge.
Fig. 4 is a horizontal structural view of a gate-drain-source structure of a conventional pHEMT.
Fig. 5 is a view of the extraction of an auxiliary gate from the gate extraction electrode-opposite side in the horizontal direction of the substrate.
Fig. 6 is an enlarged view of the auxiliary gate electrode drawn from the opposite side of the gate electrode in the horizontal direction of the substrate.
Fig. 7 is a view of drawing an auxiliary gate from the same side as a gate drawing electrode in the horizontal direction of a substrate.
Fig. 8 is an enlarged view of the auxiliary gate electrode led out from the same side as the gate lead-out electrode in the horizontal direction of the substrate.
Fig. 9 is a view of drawing an auxiliary gate above a gate-drawing electrode in the horizontal direction of the substrate.
Fig. 10 is an enlarged view of the effect of drawing the auxiliary gate above the gate-drawing electrode in the horizontal direction of the substrate.
Fig. 11 is a vertical structure diagram of the buried auxiliary gate.
Fig. 12 is a diagram of back-cut extraction of buried assist gates.
Detailed Description
All of the features disclosed in this specification, or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
Any feature disclosed in this specification (including any accompanying claims, abstract) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
The embodiment discloses a novel high-speed high-isolation pHEMT microwave switch chip, which comprises a substrate layer, a semiconductor layer grown on the substrate layer, a source electrode, a drain electrode and a grid electrode etched on the top of the semiconductor layer, wherein the grid electrode is positioned between the source electrode and the drain electrode, gaps are respectively reserved between the source electrode, the drain electrode and the grid electrode, and two grid electrode side wall regions (a grid electrode side wall region between the source electrode and the grid electrode, and a grid electrode side wall region between the drain electrode and the grid electrode) are formed. The semiconductor layer is composed of a plurality of stacked semiconductor sublayers, the semiconductor layer does not belong to the key point of the invention, and the semiconductor layer in the existing pHEMT transistor can be adopted, for example, the semiconductor layer is composed of a buffer layer, a channel layer, an isolation layer and a barrier layer from bottom to top. The sidewall region has a large amount of surface charges and interface traps and is not controlled by the gate. These surface charges and the electrostatic potential of the interface traps produce a pulling effect on the channel electrons. When the grid controls the channel current to be switched, the surface charges and the electrostatic potential of the interface trap can be counteracted only through the charging and discharging processes of the LC network of the grid and the drain. The delay in charging and discharging the LC network is therefore a major factor in the reduction of the switching speed of the pHEMT transistor.
In the embodiment, the auxiliary gate is arranged on at least one gate side wall region to suppress surface charges and interface traps of the gate side wall region, so that the impedance of the surface charges and the electrostatic potential of the interface traps to channel current is counteracted without passing through the LC network charging and discharging process of the gate and the drain when the pHEMT transistor is switched. The technology can be realized on a III-V compound semiconductor, such as GaAs, gaN, inP, siC, etc., and also can be realized on a silicon-based compound semiconductor, such as bulk silicon CMOS, SOI substrate, etc. The pHEMT transistor switching technology with the auxiliary gate is specifically realized as follows:
1. air bridge is used as auxiliary grid
The transistor switch is characterized by comprising the following structural characteristics: and arranging an air bridge as an auxiliary grid in the side wall area of the grid between the source electrode and the grid and/or the side wall area of the grid between the drain electrode and the grid.
2. Auxiliary grid electrode buried in grid electrode side wall area
The transistor switch is characterized by comprising the following structural characteristics: and embedding a metal layer in a gate side wall region between the source electrode and the gate and/or a gate side wall region between the drain electrode and the gate, and then leading out the metal layer to be used as an auxiliary gate.
The transistor switch with the two structures inhibits the surface charges and interface traps of the side wall area of the gate electrode by applying the auxiliary gate voltage on the auxiliary gate electrode, so that the blockage of the surface charges and the electrostatic potential of the interface traps to channel current is counteracted without the LC network charge-discharge process of the gate electrode and the drain electrode when the pHEMT transistor switch is switched, and the switching speed is improved. The switching speed of the pHEMT transistor with the auxiliary grid electrode can be improved to more than 100GHz, and is about 10-100 times higher than that of the pHEMT transistor in the prior art represented by the background technology.
In addition, the surface charges of the gate sidewall region and the electrostatic potential of the interface traps, the leakage current due to the electrostatic potential, also reduce the isolation. The isolation of the pHEMT transistor switch with the auxiliary grid can be improved to be more than 50GHz, the difference between the isolation and the mechanical switch is small, and the pHEMT transistor switch with the auxiliary grid can be applied to novel communication systems such as precision instruments, high-speed ADDA,5G, wifi6, CV2X and NBIoT.
In addition, the prior art pHEMT transistor switch has the defects of damage caused by the gradual aging of the schottky contacts of the source and the drain due to the surface charges of the side wall region of the gate and the electrostatic potential of the interface trap along with the frequent charging and discharging of the switch, and the conventional pHEMT transistor switch has high use frequency and short service life. The pHEMT transistor switch with the auxiliary grid electrode provided by the invention does not need to counteract the obstruction of surface charges and interface trap electrostatic potential to channel current in the charging and discharging process of an LC network of the grid electrode and the drain electrode, and the service life can be prolonged to more than 1000 ten thousand times of switching.
Finally, the pHEMT transistor switch of the prior art requires charging and discharging every time the switch is switched, so that the switching efficiency is reduced and the power consumption is increased. Meanwhile, the frequency response is reduced due to the resonance of the LC network, so that the bandwidth of the switch is reduced. The switch bandwidth of the pHEMT transistor with the auxiliary grid can cover millimeter waves and terahertz frequency bands above 100GHz, and the efficiency can be improved from 30% to 40%.
In the foregoing, two types of transistor switches with auxiliary gates designed by the present invention are described in detail in this embodiment.
For the first type of transistor structure, in some embodiments, an air bridge arrangement is shown in fig. 3. A semiconductor layer is arranged on a GaAs substrate and comprises an undoped GaAs/AlGaAs superlattice buffer layer, an undoped InGaAs channel layer, an undoped AlGaAs isolation layer and a grid control layer (a barrier layer, such as an N-type AlGaAs barrier layer) which sequentially grow from bottom to top, N-type heavily doped GaAs contact layers are respectively arranged on two sides of the grid control layer through an etching technology to serve as a source electrode and a drain electrode, a grid electrode is arranged between the source electrode and the drain electrode, gaps are respectively arranged between the grid electrode and the source electrode and between the grid electrode and the drain electrode, a grid electrode side wall region is formed in each gap, and an air bridge is arranged in each grid electrode side wall region to serve as an auxiliary grid electrode.
In the aspect of the specific embodiment, the auxiliary gate based on the air bridge can be led out from the same side of the gate lead-out circuit, the opposite side of the gate, or the upper part of the gate, etc. on the horizontal structure of the transistor switch.
1.1 leading out air bridge at the opposite side of grid in horizontal direction as auxiliary grid
As shown in fig. 4, the horizontal structure of the drain and the source of the gate of the conventional pHEMT is based on this embodiment, and an auxiliary gate is led out from the opposite side of the gate lead-out circuit, as shown in fig. 5 and 6, in the switch active region, the gate is sandwiched between two auxiliary gates, and the auxiliary gate is led out from the opposite side of the gate lead-out circuit in the substrate horizontal direction.
1.2 leading out air bridge as auxiliary grid at the same side of grid in horizontal direction
In this embodiment, the auxiliary gates are led out on the same side of the gate lead-out circuit, and as shown in fig. 7 and 8, the gate is sandwiched between the two auxiliary gates in the switch active region.
1.3 this embodiment has an auxiliary gate led over the gate,
in this embodiment, the auxiliary gate is led out above the gate lead-out circuit, and as shown in fig. 9 and 10, the gate is sandwiched between two auxiliary gates in the switch active region.
For the second type of transistor switch, the auxiliary gate is formed by a buried metal layer. In some embodiments, the scheme of disposing the buried auxiliary gate is as shown in fig. 11. A semiconductor layer is arranged on a GaAs substrate and comprises an undoped GaAs/AlGaAs superlattice buffer layer, an undoped InGaAs channel layer, an undoped AlGaAs isolation layer and a grid control layer which sequentially grow from bottom to top, N-type heavily doped GaAs contact layers are respectively arranged on two sides of the grid control layer as a source electrode and a drain electrode through an etching technology, a grid electrode is arranged between the source electrode and the drain electrode, gaps are respectively arranged between the grid electrode and the source electrode and between the grid electrode and the drain electrode, a grid electrode side wall region is formed in each gap, and a metal layer is embedded in the grid electrode side wall region to serve as an auxiliary grid electrode and then is led out.
Fig. 11 is a diagram of a vertical structure of a transistor switch, in which a gate sidewall region is embedded with a metal layer parallel to a gate, and an auxiliary gate is disposed on both sides of the gate, similar to the case of using an air bridge, except that a metal layer is provided as the auxiliary gate, in the air bridge scheme, the auxiliary gate is implemented by adding an air bridge metal layer above the gate, and in the embedded auxiliary gate scheme, the auxiliary gate is implemented by embedding a metal layer between any two adjacent layers of semiconductors in an epitaxial layer (i.e., between any two adjacent semiconductor sublayers, or between a semiconductor layer and a substrate). Similar to the air bridge scheme, the buried auxiliary gate can be led out from the same side or the opposite side of the gate lead-out circuit, and the lead-out point is connected with a surface pad (a pad arranged on the exposed surface) through a metalized via.
As shown in fig. 12, the buried auxiliary gate may be connected to a pad (or a back gate electrode) disposed on the back surface of the substrate through a metalized via, so as to form an auxiliary gate in a back gate manner.
Example two
The embodiment discloses a pHEMT microwave switch chip for realizing an auxiliary grid based on an air bridge, which comprises a GaAs substrate, wherein an epitaxial layer grows on the GaAs substrate and comprises an undoped GaAs/AlGaAs superlattice buffer layer, an undoped InGaAs channel layer, an undoped AlGaAs isolation layer and a grid control layer (barrier layer, such as an N-type AlGaAs barrier layer), which grow from bottom to top in sequence, N-type heavily doped GaAs contact layers are respectively arranged on two sides of the grid control layer as a source electrode and a drain electrode through an etching technology, a grid electrode is arranged between the source electrode and the drain electrode, gaps respectively exist between the grid electrode and the source electrode and between the grid electrode and the drain electrode, and two grid electrode side wall regions are formed at the two gaps. As shown in fig. 3, the air bridge based auxiliary gate is implemented in the present embodiment, and the air bridge is provided as the auxiliary gate in both gate sidewall regions, but this is a preferable mode, and the embedded auxiliary gate also has a certain effect in that the auxiliary gate is provided in only one gate sidewall region.
In some embodiments, the gate is inserted in an interdigitated fashion between the source and drain, as shown in figure 2. The air bridge can be led out from the same side of the grid lead-out circuit, the opposite side of the grid or the upper part of the grid. Fig. 5 and 6 show a mode in which the air bridge is drawn out from the opposite side of the gate lead-out circuit, fig. 7 and 8 show a mode in which the air bridge is drawn out from the same side of the gate lead-out circuit, and fig. 9 and 10 show a mode in which the air bridge is drawn out from above the gate lead-out circuit.
EXAMPLE III
The embodiment discloses a pHEMT microwave switch chip provided with a buried auxiliary grid, which comprises a GaAs substrate, wherein an epitaxial layer grows on the GaAs substrate and comprises an undoped GaAs/AlGaAs superlattice buffer layer, an undoped InGaAs channel layer, an undoped AlGaAs isolation layer and a grid control layer (barrier layer, such as an N-type AlGaAs barrier layer), which grow from bottom to top in sequence, N-type heavily doped GaAs contact layers are respectively arranged on two sides of the grid control layer as a source electrode and a drain electrode through an etching technology, a grid electrode is arranged between the source electrode and the drain electrode, gaps are respectively arranged between the grid electrode and the source electrode and between the grid electrode and the drain electrode, and two grid electrode side wall regions are formed at the two gaps. As shown in fig. 11, a buried auxiliary gate is disposed on both gate sidewall regions.
In one embodiment, the buried auxiliary gate is implemented by a buried metal layer. The buried metal layer is positioned between any two adjacent layers of semiconductors between the barrier layer and the substrate or between the substrate and the epitaxial layer.
The buried metal layer requires a pull-out applied voltage and in one embodiment can be pulled out from the same side or the opposite side of the gate pull-out circuit, as the metal layer is buried in the chip it is pulled out through the metalized via to the surface pad.
In another embodiment, the metal layer is led out through a back gate mode, namely the metal layer is connected with a bonding pad on the back surface of the substrate through a metalized through hole, and an auxiliary gate in the back gate mode is formed.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed.

Claims (5)

1. A novel high-speed high-isolation pHEMT microwave switch chip comprises a substrate layer, wherein a semiconductor layer is arranged on the substrate layer and consists of a plurality of stacked semiconductor sublayers, a source electrode, a drain electrode and a grid electrode are arranged at the top of the semiconductor layer, the grid electrode is positioned between the source electrode and the drain electrode, and gaps are respectively reserved between the source electrode and the grid electrode and between the drain electrode and the grid electrode to form two grid electrode side wall regions; wherein an auxiliary gate is provided on at least one of said gate sidewall regions;
the auxiliary gate is formed by an air bridge provided at a sidewall region of the gate; or, the auxiliary gate is a buried auxiliary gate, and the buried auxiliary gate is used as the auxiliary gate through a buried metal layer.
2. The novel high-speed high-isolation pHEMT microwave switch chip according to claim 1, wherein for an air bridge based auxiliary gate, the auxiliary gate is led out from the same side, the opposite side or the upper part of the gate stage lead-out circuit.
3. The novel high-speed high-isolation pHEMT microwave switch chip of claim 1, wherein said metal layer is disposed between said semiconductor layer and said substrate layer, or between adjacent semiconductor sublayers.
4. The novel high-speed high-isolation pHEMT microwave switch chip as claimed in claim 1 or 3, wherein for embedded auxiliary gates, said auxiliary gates are led out from the same side or opposite side of the gate lead-out circuit.
5. A novel high-speed high-isolation pHEMT microwave switch chip according to claim 1 or 3, wherein said buried auxiliary gate is connected to a back gate electrode disposed on the back side of said substrate by a metallized via.
CN202011477475.1A 2020-12-15 2020-12-15 Novel high-speed high-isolation pHEMT microwave switch chip Active CN112614881B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011477475.1A CN112614881B (en) 2020-12-15 2020-12-15 Novel high-speed high-isolation pHEMT microwave switch chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011477475.1A CN112614881B (en) 2020-12-15 2020-12-15 Novel high-speed high-isolation pHEMT microwave switch chip

Publications (2)

Publication Number Publication Date
CN112614881A CN112614881A (en) 2021-04-06
CN112614881B true CN112614881B (en) 2023-04-07

Family

ID=75234244

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011477475.1A Active CN112614881B (en) 2020-12-15 2020-12-15 Novel high-speed high-isolation pHEMT microwave switch chip

Country Status (1)

Country Link
CN (1) CN112614881B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113253489A (en) * 2021-05-28 2021-08-13 重庆邮电大学 Terahertz multichannel modulator and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110768643A (en) * 2019-10-11 2020-02-07 成都挚信电子技术有限责任公司 Electronic control impedance allocation chip based on radio frequency micro-electromechanical structure and microwave system
CN111081771A (en) * 2019-12-24 2020-04-28 成都挚信电子技术有限责任公司 Insulating layer buried transistor structure and device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3325356B2 (en) * 1993-09-17 2002-09-17 三菱電機株式会社 Thin film transistor and method of manufacturing the same
KR100702029B1 (en) * 2005-09-22 2007-03-30 삼성전자주식회사 Non-volatile memory devices including a high voltage MOS transistors with a floated drain-side auxiliary gate and methods of fabricating the same
JP5105160B2 (en) * 2006-11-13 2012-12-19 クリー インコーポレイテッド Transistor
JP5694020B2 (en) * 2011-03-18 2015-04-01 トランスフォーム・ジャパン株式会社 Transistor circuit
JP6238789B2 (en) * 2014-02-26 2017-11-29 株式会社豊田中央研究所 Semiconductor device
US20150263116A1 (en) * 2014-03-14 2015-09-17 Chunong Qiu High electron mobility transistors with improved gates and reduced surface traps
CN104681631B (en) * 2015-03-24 2019-04-30 京东方科技集团股份有限公司 Thin film transistor and its manufacturing method, array substrate and display device
CN106373884B (en) * 2016-09-08 2019-12-24 西安电子科技大学 Method for manufacturing composite gate dielectric GaN-based insulated gate high electron mobility transistor
US10388746B2 (en) * 2017-07-06 2019-08-20 Teledyne Scientific & Imaging, Llc FET with buried gate structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110768643A (en) * 2019-10-11 2020-02-07 成都挚信电子技术有限责任公司 Electronic control impedance allocation chip based on radio frequency micro-electromechanical structure and microwave system
CN111081771A (en) * 2019-12-24 2020-04-28 成都挚信电子技术有限责任公司 Insulating layer buried transistor structure and device

Also Published As

Publication number Publication date
CN112614881A (en) 2021-04-06

Similar Documents

Publication Publication Date Title
CN110400848B (en) Schottky diode and manufacturing method thereof
US11888027B2 (en) Monolithic integration of high and low-side GaN FETs with screening back gating effect
JP4322414B2 (en) Semiconductor device
KR101737149B1 (en) Electronic component, method of forming an electronic component, assembly, half bridge, and bridge circuit for low emi circuits
US20170018617A1 (en) Field-plate structures for semiconductor devices
JP5735139B2 (en) Semiconductor device having low conductivity electric field control element
US11056584B2 (en) Semiconductor device
US10516043B1 (en) Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors
CN110649096B (en) High-voltage n-channel HEMT device
CN112614881B (en) Novel high-speed high-isolation pHEMT microwave switch chip
JP2022167848A (en) Gallium nitride device, switching power transistor, drive circuit, and gallium nitride device production method
CN110168936A (en) Transistor unit
CN102315262B (en) Semiconductor device and making method thereof
CN113035841A (en) Integrated chip with junction isolation structure and manufacturing method thereof
CN113140566A (en) Integrated chip with isolation structure and manufacturing method thereof
CN116190374A (en) ESD protection device with isolation structure layout to minimize harmonic distortion
CN111081771B (en) Buried-insulating-layer transistor structure and device
CN113421922B (en) Three-dimensional IGBT with grid self-clamping function and manufacturing method thereof
US7397109B2 (en) Method for integration of three bipolar transistors in a semiconductor body, multilayer component, and semiconductor arrangement
CN113611768B (en) Photosensitive field effect transistor
CN101924079A (en) Semiconductor chip package structure
CN113421923A (en) IGBT with grid self-clamping function and manufacturing method thereof
CN107359193B (en) LDMOS device
CN111834453A (en) Semiconductor device and preparation method thereof
JP2007115895A (en) Compound semiconductor switch circuit device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant