CN104681631B - Thin film transistor and its manufacturing method, array substrate and display device - Google Patents
Thin film transistor and its manufacturing method, array substrate and display device Download PDFInfo
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- CN104681631B CN104681631B CN201510132002.0A CN201510132002A CN104681631B CN 104681631 B CN104681631 B CN 104681631B CN 201510132002 A CN201510132002 A CN 201510132002A CN 104681631 B CN104681631 B CN 104681631B
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- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000009413 insulation Methods 0.000 claims abstract description 132
- 125000006850 spacer group Chemical group 0.000 claims description 32
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000010410 layer Substances 0.000 description 236
- 238000000034 method Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000000059 patterning Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
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Abstract
The present invention relates to field of display technology, disclose a kind of thin film transistor (TFT), it include: the grid being formed on underlay substrate, source electrode, drain electrode, active layer and gate insulation layer, further include: the auxiliary grid with the drain electrode connection is spaced the gate insulation layer between the auxiliary grid and the active layer.Also disclose a kind of thin film transistor (TFT) production method, array substrate and display device.Thin film transistor (TFT) of the invention can be effectively reduced off-state current.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of thin film transistor and its manufacturing method, array substrate and
Display device.
Background technique
For thin film transistor (TFT) (TFT) device of display pannel, since there are biggish for the reason of material property itself
Off-state current, if polysilicon is as active layer, then being present in the crystal boundary of polysilicon membrane has a large amount of defects, becomes crystal boundary and closes
State electric current excessive main " channel ", this seriously affects the using effect of TFT.Be traditionally used for reduce off-state current method be
Lower on-state current is also resulted in using LDD (Lightly Doped Drain) structure, but while reduction off-state current,
So that reducing the ineffective of off-state current in larger operating voltage.
Summary of the invention
(1) technical problems to be solved
The technical problem to be solved by the present invention is how to be effectively reduced the off-state current of thin film transistor (TFT).
(2) technical solution
In order to solve the above technical problems, the present invention provides a kind of thin film transistor (TFT)s, comprising: be formed on underlay substrate
Grid, source electrode, drain electrode, active layer and gate insulation layer, further includes: the auxiliary grid with the drain electrode connection, the auxiliary grid
The gate insulation layer is spaced between the active layer.
Wherein, the active layer is located on the underlay substrate, and the gate insulation layer is located at the active layer, institute
It states grid to be located on the gate insulation layer, the source electrode and drain electrode is located above active layer, and has between insulation with gate spacer
Interlayer；The auxiliary grid is located on the same floor with the grid, and the source electrode is by passing through the dielectric spacer layer and gate insulation
First via hole of layer connects the active layer, and the drain electrode passes through the second via hole across the dielectric spacer layer and gate insulation layer
The active layer is connected, the drain electrode is connect by second via hole with the auxiliary grid.
Wherein, the active layer is located on the underlay substrate, and the gate insulation layer is located at the active layer, institute
It states grid to be located on the gate insulation layer, the source electrode and drain electrode is located above active layer, and has between insulation with gate spacer
Interlayer；The source electrode connects the active layer, the leakage with the first via hole of gate insulation layer by passing through the dielectric spacer layer
Pole connects the active layer with the second via hole of gate insulation layer by passing through the dielectric spacer layer, and second via hole is in step
Shape is greater than the opening across the gate insulation layer across the opening of the dielectric spacer layer, and the auxiliary grid is formed in described
On the step of gate insulation layer, and it is integrally formed with the drain electrode.
Wherein, the grid is located on the underlay substrate, and the gate insulation layer is located on the grid, described to have
Active layer is located on the gate insulation layer, and the source electrode and drain electrode is located at the active layer, the auxiliary grid with it is described
Grid is located on the same floor, and connects the drain electrode with the via hole of active layer by passing through the gate insulation layer.
The present invention also provides a kind of thin film transistor (TFT)s, comprising: the grid that is formed on underlay substrate source electrode, drains, has
Active layer and the first gate insulation layer, further includes: the second gate insulation layer and the auxiliary grid with the drain electrode connection, the active layer position
Between first gate insulation layer and second gate insulation layer, between the auxiliary grid and the active layer described in interval
Second gate insulation layer.
Wherein, the grid is located on the underlay substrate, and first gate insulation layer is located on the grid, institute
Active layer is stated to be located on first gate insulation layer, the source electrode, drain electrode and the second gate insulation layer be located at the active layer it
On, the auxiliary grid is located on second gate insulation layer, and the via hole by passing through second gate insulation layer connects
The drain electrode.
Wherein, the grid is located on the underlay substrate, and first gate insulation layer is located on the grid, institute
It states active layer to be located on first gate insulation layer, second gate insulation layer is located at the active layer, the source electrode
It is located above the active layer with drain electrode, the source electrode has described in the first via hole connection of second gate insulation layer by passing through
Active layer, the drain electrode connect the active layer, the auxiliary grid position by passing through the second via hole of second gate insulation layer
On the second grid, and it is integrally formed with the drain electrode.
Wherein, the active layer is the active layer with light-dope structure.
The present invention also provides a kind of thin film transistor (TFT) production methods, comprising:
Formation includes the figure of active layer, gate insulation layer, grid and auxiliary grid on underlay substrate；
Dielectric spacer layer is formed, and forms the first via hole and the second mistake for running through the dielectric spacer layer and gate insulation layer
Hole exposes active layer by first via hole and the second via hole, and exposes the supplementary gate by second via hole
Pole；
The figure of source electrode and drain electrode is formed, and the source electrode is made to connect the active layer by first via hole, makes institute
It states drain electrode and active layer and auxiliary grid is connected by the second via hole.
The present invention also provides a kind of thin film transistor (TFT) production methods, comprising:
The figure including active layer, gate insulation layer and grid is formed on underlay substrate；
Dielectric spacer layer is formed, and forms the first via hole and the second mistake for running through the dielectric spacer layer and gate insulation layer
Hole exposes active layer by first via hole and the second via hole, and second via hole passes through the dielectric spacer layer
Opening is greater than the opening across the gate insulation layer, makes to form gate insulation layer step；
The figure of source electrode, drain electrode and auxiliary grid is formed, and makes the source electrode by having described in first via hole connection
Active layer, the auxiliary electrode and drain electrode are integrally formed, and the auxiliary grid is formed on the gate insulation layer step, the drain electrode
Active layer is connected by the second via hole.
The present invention also provides a kind of thin film transistor (TFT) production methods, comprising:
Formation includes the figure of grid, auxiliary grid, gate insulation layer and active layer on underlay substrate；
The via hole across the gate insulation layer and active layer is formed, makes to expose the auxiliary grid；
The figure of source electrode and drain electrode is formed in active layer, the drain electrode connects the supplementary gate by the via hole
Pole.
The present invention also provides a kind of thin film transistor (TFT) production methods, comprising:
The figure including grid, the first gate insulation layer and active layer is formed on underlay substrate；
Formation includes the figure of source electrode, drain electrode, the second gate insulation layer and auxiliary grid above active layer, is made described active
Second gate insulation layer is spaced between layer and auxiliary grid, the auxiliary grid connects the drain electrode.
Wherein, the formation above active layer includes the figure of source electrode, drain electrode, the second gate insulation layer and auxiliary grid,
Make to be spaced second gate insulation layer between the active layer and auxiliary grid, the step of auxiliary grid connects the drain electrode
It specifically includes:
The figure of source electrode and drain electrode is formed in active layer；
The second gate insulation layer and the thereon figure of via hole are formed, drain electrode is exposed in the via hole；
The figure of auxiliary grid is formed, the auxiliary grid connects the drain electrode by via hole.
Wherein, the formation above active layer includes the figure of source electrode, drain electrode, the second gate insulation layer and auxiliary grid,
Make to be spaced second gate insulation layer between the active layer and auxiliary grid, the step of auxiliary grid connects the drain electrode
It specifically includes:
Form the second gate insulation layer and the first via hole and the second via hole thereon in active layer, first via hole and
Active layer is exposed in second via hole；
The figure for forming the source electrode, drain electrode and auxiliary grid connects the source electrode by the first via hole described active
Layer, drain electrode connect the active layer by the second via hole, and auxiliary grid is formed on second gate insulation layer, and with drain electrode
It is integrally formed.
The present invention also provides a kind of array substrates, including thin film transistor (TFT) described in any of the above embodiments.
The present invention also provides a kind of display devices, including above-mentioned array substrate.
(3) beneficial effect
In thin-film transistor structure of the invention, auxiliary grid connection drain electrode is equivalent to and forms a grid connection
The auxiliary TFT of drain electrode, auxiliary TFT have the function of the one-way conduction of diode, if entire TFT is in the conductive state, two poles
Pipe structure is also exactly on state, if entire TFT shutdown, diode structure also just turn off, to reduce entire
The off-state current of TFT.
Detailed description of the invention
Fig. 1 is the TFT structure schematic diagram of an embodiment of the present invention；
Fig. 2 is the TFT structure schematic diagram of another embodiment of the invention；
Fig. 3 is the TFT structure schematic diagram of another embodiment of the invention；
Fig. 4 is the TFT structure schematic diagram of another embodiment of the invention；
Fig. 5 is the TFT structure schematic diagram of another embodiment of the invention；
Fig. 6 is the TFT structure schematic diagram of another embodiment of the invention；
Fig. 7 is the equivalent circuit schematic of the TFT structure of the embodiment of the present invention；
Fig. 8 is to be formed to have made the schematic diagram after grid and auxiliary grid in Fig. 1 in the method for TFT；
Fig. 9 is that dielectric spacer layer and the thereon schematic diagram of via hole are formed on the basis of Fig. 8；
Figure 10 is to be formed to have made the schematic diagram after grid in Fig. 2 in the method for TFT；
Figure 11 is that dielectric spacer layer and the thereon schematic diagram of via hole are formed on the basis of Figure 10；
Figure 12 is to be formed to have made the schematic diagram after active layer in Fig. 3 in the method for TFT；
Figure 13 is the schematic diagram that via hole is formed on the basis of Figure 12；
Figure 14 is to be formed to have made the schematic diagram after source-drain electrode in Fig. 4 in the method for TFT；
Figure 15 is that the second gate insulation layer and the thereon schematic diagram of via hole are formed on the basis of Figure 14；
Figure 16 is to be formed to have made the schematic diagram after active layer in Fig. 5 in the method for TFT；
Figure 17 is that the second gate insulation layer and the thereon schematic diagram of the first via hole and the second via hole are formed on the basis of Figure 16.
Specific embodiment
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.Implement below
Example is not intended to limit the scope of the invention for illustrating the present invention.
Thin film transistor (TFT) (TFT) of the invention include: the grid being formed on underlay substrate, source electrode, drain electrode, active layer and
Gate insulation layer, for the gate insulation layer between the grid and the active layer, the source electrode and drain electrode connection is described active
Layer.In order to reduce the off-state current of TFT, which further includes the auxiliary grid with the drain electrode connection, the auxiliary grid and institute
It states and is spaced gate insulation layer between active layer.The auxiliary TFT an of auxiliary grid and drain electrode connection is formed i.e. inside entire TFT,
Due to auxiliary grid and drain electrode connection, auxiliary TFT realizes the one-way conduction function of diode, if entire TFT is on
When state, diode structure is also exactly on state, if entire TFT shutdown, diode structure also just turn off, thus
Reduce the off-state current of entire TFT.
The TFT specific structure of the first embodiment of the present invention as shown in Figure 1, underlay substrate (including substrate 101 and thereon
Buffer layer 102) on successively include: active layer 103, gate insulation layer 104, grid 105, dielectric spacer layer 106, source electrode 107, leakage
Pole 108 and auxiliary grid 109.Auxiliary grid 109 is located on the same floor with grid 105, can be with grid 105 while shape in production
At.Source electrode 107 connects active layer 103, drain electrode by passing through the first via hole 110 of dielectric spacer layer 106 and gate insulation layer 104
108 connect active layer 103 by passing through the second via hole 111 of dielectric spacer layer 106 and gate insulation layer 104.Drain electrode passes through second
Via hole 111 is connect with auxiliary grid 109.
The TFT of the second embodiment of the present invention is as shown in Fig. 2, underlay substrate (buffer layer including substrate 201 and thereon
It 202) successively include: active layer 203, gate insulation layer 204, grid 205, dielectric spacer layer 206, source electrode 207 and drain electrode on
208.Source electrode 207 connects active layer 203, drain electrode by passing through the first via hole 210 of dielectric spacer layer 206 and gate insulation layer 204
208 connect active layer 203 by passing through the second via hole 211 of dielectric spacer layer 206 and gate insulation layer 204.In the present embodiment, the
Two via holes 211 are greater than the opening across gate insulation layer 204, auxiliary grid in step-like, across the opening of dielectric spacer layer 206
209 are formed on the step of gate insulation layer 204 (in Fig. 2 shown in dotted ellipse frame), and integrally formed with drain electrode 208, supplementary gate
Pole 209 is formed simultaneously in production with drain electrode 208.
Above-mentioned two embodiment is the TFT of top gate structure, this one supplementary gate of formation in entire TFT of the invention
The principle of the auxiliary TFT of pole connection drain electrode is equally applicable to the TFT of bottom grating structure.
As shown in figure 3, the third embodiment of the present invention shows a kind of bottom-gate type configuration TFT, comprising: in underlay substrate
Grid 302, auxiliary grid 308, gate insulation layer 303, active layer 304, source electrode 305 and the drain electrode 306 formed on 301.Supplementary gate
Pole 308 and grid 302 are formed in same layer, and drain electrode 306 is by passing through the via hole of active layer 304 and gate insulation layer 303 (see production
Via hole 309 in Figure 13 of process) connection auxiliary grid 308.
In above-described embodiment, auxiliary grid forms auxiliary TFT using original gate insulation layer, can also independently form one
Layer gate insulation layer forms auxiliary TFT, and structure includes the grid being formed on underlay substrate, source electrode, drain electrode, active layer and the
One gate insulation layer, in order to reduce TFT off-state current, further includes: the second gate insulation layer and the auxiliary grid with the drain electrode connection,
The active layer is between first gate insulation layer and second gate insulation layer, the auxiliary grid and the active layer
Between be spaced second gate insulation layer, following 4th and the 5th embodiment of specific structure.
As shown in figure 4, the fourth embodiment of the present invention shows a kind of bottom-gate type configuration TFT, comprising: in underlay substrate
Grid 402, the first gate insulation layer 403, active layer 404, source electrode 405, drain electrode 406 and the second gate insulation sequentially formed on 401
Layer 407.Source electrode 405 and drain electrode 406 are located on active layer 404, and are located on the same floor.Second gate insulation layer 407 covers source electrode
405 and drain electrode 406, and be located at active layer 404 on.Auxiliary grid 408 is located on the second gate insulation layer 407, by passing through
The via hole connection drain electrode 406 of second gate insulation layer 407.
As shown in figure 5, the fifth embodiment of the present invention shows a kind of bottom-gate type configuration TFT, comprising: in underlay substrate
Grid 502, the first gate insulation layer 503, active layer 504, the second gate insulation layer 507, source electrode 505 and the leakage sequentially formed on 501
Pole 506.Second gate insulation layer 507 is located on active layer 504, is formed with the first via hole 510 and the second via hole 509 thereon.Source
Pole 505 and drain electrode 506 connect active layer 504 by the first via hole 510 and the second via hole 509 respectively.Auxiliary grid 508 is located at the
On two gate insulation layers 407, and it is integrally formed with drain electrode 506, in production, auxiliary grid 508 is formed simultaneously with drain electrode 506.
In order to further decrease the off-state current of thin film transistor (TFT), the active layer of above-described embodiment is with being lightly doped
(LDD) active layer of structure, wherein LDD structure gently mix to the active layer of TFT in Fig. 2 as shown in dashed rectangle in Fig. 6
It is miscellaneous.
Auxiliary TFT (the grid of auxiliary TFT with diode function are all formd in the TFT structure of above-described embodiment
Pole connects the drain electrode of itself) structure, equivalent circuit as shown in fig. 7, auxiliary TFT is equivalent to together to the gate of electric current,
When entire TFT is closed, auxiliary TFT is also switched off, to reduce the off-state current of entire TFT.
The present invention also provides the production methods of the TFT of production first embodiment, as shown in Figure 8 and Figure 9, comprising:
As shown in figure 8, sequentially forming in underlay substrate (including substrate 101 and buffer layer 102) including active layer 103, grid
The figure of insulating layer 104, grid 105 and auxiliary grid 109, especially by patterning processes, (patterning processes generally include photoresist
The techniques such as coating, exposure, development, etching, photoresist lift off) form active layer 103, gate insulation layer 104, grid 105 and auxiliary
Grid 109.Grid 105 and auxiliary grid 109 are formed in a same patterning processes using same material.If active layer 103 is
When polycrystalline silicon material, processing also usually is doped to active layer.
As shown in figure 9, being formed includes dielectric spacer layer 106, and is formed and run through dielectric spacer layer 106 and gate insulation layer 104
The first via hole 110 and the second via hole 111.Active layer 103 is exposed in first via hole 110 and the second via hole 111.It is carving
It is exposed to the auxiliary grid 109 in second via hole 111, in order to connect with drain electrode 108.
Shown in Fig. 1, the figure including source electrode 107 and drain electrode 108 is formed, is connected with source electrode 107 by the first via hole 110
Active layer 103, drain electrode 108 connect active layer 103 and auxiliary grid 109 by the second via hole 111.
The present invention also provides the production methods of the TFT of second embodiment, as shown in FIG. 10 and 11, comprising:
As shown in Figure 10, it sequentially forms in underlay substrate (including substrate 201 and buffer layer 202) including active layer 203, grid
The figure of insulating layer 204 and grid 205.
As shown in figure 11, being formed includes dielectric spacer layer 206, and is formed and run through dielectric spacer layer 206 and gate insulation layer 204
The first via hole 210 and the second via hole 211.Active layer 203 is exposed in first via hole 210 and the second via hole 211.This reality
It applies in example, the opening that the second via hole 211 passes through dielectric spacer layer 206 is greater than the opening across the first gate insulation layer 204, makes to be formed
Gate insulation layer step shown in dotted line frame in Figure 11.
As shown in Fig. 2, the figure including source electrode 207, drain electrode 208 and auxiliary grid 209 is formed, the formation of auxiliary grid 209
It is simultaneously and integrally formed with drain electrode 208 on gate insulation layer step.
Above-mentioned two embodiment is the TFT production method of top gate structure, and the present invention also provides the bottoms of 3rd embodiment
The production method of grating structure TFT, as shown in Figures 12 and 13, comprising:
As shown in figure 12, formed on underlay substrate includes grid 302, auxiliary grid 308, gate insulation layer 303 and active
The figure of layer 304.
As shown in figure 13, the via hole 309 across gate insulation layer 303 and active layer 304 is formed, makes to expose auxiliary grid
308。
As shown in figure 3, forming the figure of source electrode 305 and drain electrode 306 on active layer 304, drain electrode 306 passes through via hole
The 309 connection auxiliary grids 308.
Auxiliary grid directly forms auxiliary TFT using original gate insulation layer in the production method of above-described embodiment.System
One layer of gate insulation layer can also be independently formed when making to form auxiliary TFT, making step is as follows:
The figure including grid, the first gate insulation layer and active layer is formed on underlay substrate；
Formation includes the figure of source electrode, drain electrode, the second gate insulation layer and auxiliary grid above active layer, is made described active
Second gate insulation layer is spaced between layer and auxiliary grid, the auxiliary grid connects the drain electrode.
Specific production step is as shown in the TFT method of following production example IV and embodiment five.
The present invention also provides the production methods of the bottom-gate type configuration TFT of fourth embodiment, as shown in FIG. 14 and 15, packet
It includes:
As shown in figure 14, it is sequentially formed on underlay substrate 401 including grid 402, the first gate insulation layer 403 and active layer
404 figure.On this basis, the figure including source electrode 405 and drain electrode 406 is re-formed.
As shown in figure 15, the figure of the second gate insulation layer 407 is formed on source electrode 405 and drain electrode 406, and in second gate
The via hole 409 for connecting drain electrode 406 is formed on insulating layer 407.
The figure of auxiliary grid 408 is formed on the second gate insulation layer 407, auxiliary grid 408 passes through the connection leakage of via hole 409
Pole 406 ultimately forms TFT shown in Fig. 4.
The present invention also provides the production methods of the bottom-gate type configuration TFT of the 5th embodiment, as shown in FIG. 16 and 17, packet
It includes:
As shown in figure 16, grid 502, the first gate insulation layer 503 and active layer are sequentially formed on underlay substrate 501
504 figure.
As shown in figure 17, the second gate insulation layer 507 and the first via hole 510 thereon and are formed on active layer 504
Active layer 504 is exposed in two via holes 509, the first via hole 510 and the second via hole 509.
The figure for forming source electrode 505, drain electrode 506 and auxiliary grid 508 is connected with source electrode 505 by the first via hole 510
Active layer 504, drain electrode 506 connect active layer 504 by the second via hole 509.Auxiliary grid 508 is formed in the second gate insulation layer 507
On, and it is simultaneously and integrally formed with drain electrode 506, ultimately form TFT shown in fig. 5.
In above-mentioned production method, existing patterning processes can be used when making each layer of figure, and (patterning processes are logical
Often include the techniques such as photoresist coating, exposure, development, etching, photoresist lift off) it is formed, details are not described herein again.
During making the TFT of the 5th embodiment, makes the second gate insulation layer 507 and source-drain layer can be same primary
It is completed in mask technique.It adjusts mask plate to be exposed photoresist using double, removes the first via hole 510 and the second via hole 509
The corresponding photoresist in region etches the first via hole 510 and the second via hole 509；Remaining photoresist is ashed, only retains and removes
Photoresist except 508 corresponding region of source-drain electrode and auxiliary grid；Drain metallic film is formed, remaining photoresist is carried out
Liftoff removing, removal are covered on the drain metallic film on photoresist, to form source electrode 505, drain electrode 506 and auxiliary grid
508.A mask technique can be saved with respect to example IV in this way.
In order to further decrease the off-state current of thin film transistor (TFT), in above-described embodiment, further include when forming active layer
(LDD) structure is lightly doped in active layer formation.
The present invention also provides a kind of array substrates, including above-mentioned thin film transistor (TFT).
The present invention also provides a kind of display devices, including above-mentioned array substrate.The display device can be with are as follows: liquid crystal surface
Plate, Electronic Paper, oled panel, mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator etc. are appointed
What products or components having a display function.
The above embodiments are only used to illustrate the present invention, and not limitation of the present invention, in relation to the common of technical field
Technical staff can also make a variety of changes and modification without departing from the spirit and scope of the present invention, therefore all
Equivalent technical solution also belongs to scope of the invention, and scope of patent protection of the invention should be defined by the claims.
Claims (9)
1. a kind of thin film transistor (TFT), comprising: grid, source electrode, drain electrode, active layer and the gate insulation layer being formed on underlay substrate,
It is characterized by further comprising: the auxiliary grid with the drain electrode connection,
The active layer is located on the underlay substrate, and the gate insulation layer is located at the active layer, the grid position
On the gate insulation layer, the source electrode and drain electrode is located above active layer, and has dielectric spacer layer with gate spacer；It is described
Auxiliary grid is located on the same floor with the grid, and the source electrode passes through the first mistake across the dielectric spacer layer and gate insulation layer
Hole connects the active layer, the drain electrode connected by passing through the dielectric spacer layer with the second via hole of gate insulation layer described in have
Active layer, the drain electrode are connect by second via hole with the auxiliary grid.
2. a kind of thin film transistor (TFT), comprising: grid, source electrode, drain electrode, active layer and the gate insulation layer being formed on underlay substrate,
It is characterized by further comprising: the auxiliary grid with the drain electrode connection,
The grid is located on the underlay substrate, and the gate insulation layer is located on the grid, and the active layer is located at
On the gate insulation layer, the source electrode and drain electrode is located at the active layer, and the auxiliary grid is located at the grid
Same layer connects the drain electrode with the via hole of active layer by passing through the gate insulation layer.
3. a kind of thin film transistor (TFT), comprising: grid, source electrode, drain electrode, active layer and the first gate insulation being formed on underlay substrate
Layer, which is characterized in that further include: the second gate insulation layer and the auxiliary grid with the drain electrode connection, the active layer are located at institute
It states between the first gate insulation layer and second gate insulation layer, described second is spaced between the auxiliary grid and the active layer
Gate insulation layer；
The grid is located on the underlay substrate, and first gate insulation layer is located on the grid, the active layer
On first gate insulation layer, the source electrode and drain electrode is located at the active layer, the covering of second grid insulating layer
The source electrode and drain electrode, second grid insulating layer have across the second grid insulating layer and expose the via hole of the drain electrode,
The auxiliary grid is located on second gate insulation layer, and the auxiliary grid passes through described across the second gate insulation layer and sudden and violent
The via hole for exposing the drain electrode connects the drain electrode.
4. thin film transistor (TFT) according to any one of claims 1 to 3, which is characterized in that the active layer is with gently mixing
The active layer of miscellaneous structure.
5. a kind of thin film transistor (TFT) production method characterized by comprising
Formation includes the figure of active layer, gate insulation layer, grid and auxiliary grid, the auxiliary grid and institute on underlay substrate
Grid is stated to be located on the same floor；
Dielectric spacer layer is formed, and forms the first via hole and the second via hole for running through the dielectric spacer layer and gate insulation layer, is led to
It crosses first via hole and the second via hole exposes active layer, and the auxiliary grid is exposed by second via hole；
The figure of source electrode and drain electrode is formed, and the source electrode is made to connect the active layer by first via hole, makes the leakage
Pole connects active layer and auxiliary grid by the second via hole.
6. a kind of thin film transistor (TFT) production method characterized by comprising
Formation includes the figure of grid, auxiliary grid, gate insulation layer and active layer on underlay substrate；
The via hole across the gate insulation layer and active layer is formed, makes to expose the auxiliary grid；
The figure of source electrode and drain electrode is formed in active layer, the drain electrode connects the auxiliary grid by the via hole.
7. a kind of thin film transistor (TFT) production method characterized by comprising
The figure including grid, the first gate insulation layer and active layer is formed on underlay substrate；
Above active layer formed include source electrode, drain electrode, the second gate insulation layer and auxiliary grid figure, make the active layer with
Second gate insulation layer is spaced between auxiliary grid, the auxiliary grid connects the drain electrode by via hole；
The formation above active layer includes the figure of source electrode, drain electrode, the second gate insulation layer and auxiliary grid, is made described active
Be spaced second gate insulation layer between layer and auxiliary grid, the step of auxiliary grid connects the drain electrode by via hole tool
Body includes:
The figure of source electrode and drain electrode is formed in active layer；
The second gate insulation layer and the thereon figure of via hole are formed, drain electrode is exposed in the via hole；
The figure of auxiliary grid is formed, the auxiliary grid connects the drain electrode by via hole.
8. a kind of array substrate, which is characterized in that including thin film transistor (TFT) as described in any one of claims 1 to 4.
9. a kind of display device, which is characterized in that including array substrate as claimed in claim 8.
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| CN109003892B (en) * | 2018-07-24 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor manufacturing method and thin film transistor |
| CN109326651A (en) * | 2018-08-29 | 2019-02-12 | 南京邮电大学 | Double-gate structure black phosphorus field-effect tube |
| CN109727999B (en) * | 2019-01-02 | 2020-07-03 | 合肥京东方显示技术有限公司 | Preparation method of array substrate, array substrate and display device |
| CN110071145A (en) * | 2019-04-08 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Display panel and electronic equipment |
| CN111863970B (en) * | 2019-04-26 | 2022-02-01 | 京东方科技集团股份有限公司 | Thin film transistor and display device |
| CN111063696A (en) * | 2019-12-10 | 2020-04-24 | 武汉华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN112614881B (en) * | 2020-12-15 | 2023-04-07 | 成都挚信电子技术有限责任公司 | Novel high-speed high-isolation pHEMT microwave switch chip |
| CN114863970B (en) * | 2022-04-02 | 2023-02-17 | 北京超弦存储器研究院 | Dynamic memory, manufacturing method thereof, reading method thereof and storage device |
| EP4394772A1 (en) | 2022-04-02 | 2024-07-03 | Beijing Superstring Academy of Memory Technology | Memory and manufacturing method therefor, and electronic device |
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