CN107359193B - LDMOS device - Google Patents
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- 239000002184 metal Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
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- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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Abstract
The invention provides an LDMOS device, and belongs to the technical field of power devices. The cellular structure of the LDMOS device of the invention comprises: the device comprises a substrate, a first active region, a second active region and a surface voltage-withstanding region, wherein the first active region and the second active region are positioned at two ends of the substrate; the first active region and the surface voltage-withstanding region are close to the side to form a MOSFET with a first conductivity type, and the second active region and the surface voltage-withstanding region are close to the side to form a MOSFET with a second conductivity type; the floating empty regions are respectively arranged in the device drain region and the surface voltage-resistant region, and the two floating empty regions are electrically connected with the drain region grid to form a three-terminal device, so that two types of carriers can automatically participate in conduction as majority carriers respectively without additionally increasing control signals, and a conductance modulation effect is not formed. The invention realizes the quick turn-off of the unipolar device while obviously enhancing the current capability of the device, and the invention can integrate two LDMOS devices with different conduction types but similar current capabilities under the same process.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a high-voltage transverse semiconductor device.
Background
miniaturization and integration of power electronic systems are important research directions of power semiconductor devices. In an intelligent Power Integrated Circuit (SPIC) or a High Voltage Integrated Circuit (HVIC), low voltage circuits such as protection, control, detection, and driving and High voltage Power devices are Integrated on the same chip, which not only reduces the system volume, but also improves the system reliability. Meanwhile, in a working occasion with higher frequency, the requirement of the buffering and protecting circuit can be obviously reduced due to the reduction of the inductance of the lead wire of the system.
on,sp on,sp on,spThe invention relates to a Lateral Double-diffused Metal Oxide Field Effect Transistor (LDMOS), which is a key technology of an SPIC or an HVIC.A high-Voltage and low-Voltage integrated circuit can be simultaneously manufactured on a thin epitaxial layer by utilizing a traditional low-Voltage integration technology without using a thick epitaxy to manufacture a high-Voltage-resistant power semiconductor device along with the invention of a reduced SURface electric Field technology (RESURF).
In order to obtain a better compromise relationship between BV and R on,sp, j.s.ajit et al proposed a double-layer RESURF (double RESURF) technology in the fifth international seminar of power semiconductor devices and integrated circuits in 6 months 1993, as shown in fig. 1, a P-type LDMOS (abbreviated as pLDMOS) structure designed based on the double-layer RESURF technology, wherein the P-type impurity dose of a voltage-withstanding region is increased by about 2 times through doping compensation, and is decreased compared with an on-resistance R on,sp, a three-layer RESURF (triple RESURF) technology is proposed in the thirteenth international seminar of power semiconductor devices and integrated circuits in 2 months 2001 for further decreasing R on,sp of the LDMOS device, and as shown in fig. 2, a LDMOS P device structure designed based on the three-layer RESURF technology.
However, a pLDMOS device designed based On the conventional RESURF technology only conducts through holes, so that R on,sp is about 3 times of an N-type LDMOS (nLDMOS) device, which is very disadvantageous for saving chip area and system power consumption.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the novel high-voltage LDMOS device can remarkably enhance the current capability of the LDMOS device, can realize quick turn-off and is compatible with the conventional RESURF technology.
In order to solve the technical problems, the invention provides the following technical scheme:
An LDMOS device, the cellular structure of which comprises: the semiconductor device comprises a substrate, a second conductive type semiconductor source substrate region positioned on one side of the top layer of the substrate, a first conductive type semiconductor drain region positioned on the other side of the top layer of the substrate, and a surface voltage-resistant region positioned on the surface of the substrate between the second conductive type semiconductor source substrate region and the first conductive type semiconductor drain region; the second conductive type semiconductor source substrate region is provided with a first second conductive type heavily doped body contact region and a first conductive type heavily doped source region which are independent of each other; the device surface is contacted with the first heavily doped body contact region of the second conduction type and the first heavily doped source region of the first conduction type through source metal, the upper surfaces of the first heavily doped source region of the first conduction type, part of the substrate region of the second conduction type semiconductor and part of the surface voltage-resisting region are provided with first gate dielectric layers, and the upper surface of each first gate dielectric layer is provided with a first gate; the second conductive type semiconductor source substrate region, the first second conductive type heavily doped body contact region, the first conductive type heavily doped source region, the source metal, the first gate dielectric layer and the first gate form a first active region, and a first conductive type MOSFET is formed on the side close to the first active region and the surface voltage-withstanding region; the method is characterized in that:
the surface voltage-withstanding region is formed by a first conduction type semiconductor layer and a second conduction type semiconductor layer, the second conduction type semiconductor layer partially surrounds the first conduction type semiconductor layer and is arranged on the upper surface of the substrate, the first conduction type semiconductor layer is arranged close to the second conduction type semiconductor source substrate region, two layers of semiconductor layers in the surface voltage-withstanding region are both contacted with the second conduction type semiconductor source substrate region, the second conduction type semiconductor layer in the surface voltage-withstanding region is contacted with the first conduction type semiconductor drain region, and the first conduction type semiconductor in the surface voltage-withstanding region is not contacted with the first conduction type semiconductor drain region; one end, close to a first conductive type semiconductor drain region, of a first conductive type semiconductor layer in the surface voltage-resisting region is provided with a first conductive type heavily doped semiconductor region, and the upper surface of the first conductive type heavily doped semiconductor region is provided with a first floating electrode;
The first conductive type semiconductor drain region is provided with a second conductive type heavily doped source region and a second conductive type heavily doped body contact region which are independent of each other; the surface of the device is in contact with a second heavily doped source region of a second conductivity type and a second heavily doped body contact region of the first conductivity type, drain metal is arranged in the drain region of the semiconductor of the first conductivity type, a second heavily doped semiconductor region of the first conductivity type is arranged in the drain region of the semiconductor of the first conductivity type, a second floating electrode is arranged on the upper surface of the first heavily doped semiconductor region of the first conductivity type, a first heavily doped semiconductor region which is used for communicating the second heavily doped semiconductor region of the first conductivity type with the second heavily doped body contact region of the first conductivity type does not exist between the second heavily doped semiconductor region of the first conductivity type and the second heavily doped body contact region of the first conductivity type, a second grid medium layer is arranged on the upper surface of the second heavily doped source region of the second conductivity type, a part of the drain region (10) of the semiconductor of the first conductivity type and a part; the first conductive type semiconductor drain region, the second conductive type heavily doped source region II, the first conductive type heavily doped body contact region II, the first conductive type heavily doped semiconductor region II, the drain metal, the second gate dielectric layer, the second gate and the second floating electrode form a second active region, and the second active region and the surface voltage-resisting region are close to form a second conductive type MOSFET.
Furthermore, the surface voltage-withstanding region of the invention further includes a second conductivity type top layer partially enclosed in the first conductivity type semiconductor layer, and an upper surface of the second conductivity type top layer coincides with an upper surface of the device.
Furthermore, the second heavily doped source region of the second conductivity type and the second heavily doped body contact region of the first conductivity type are arranged in parallel, and the longitudinal lengths of the second heavily doped source region of the second conductivity type and the second heavily doped body contact region of the first conductivity type are defined as L 13 and L 14 respectively, so that the L 13 -L 14 ≦ 50 μm.
further, the first conductivity type is P-type, and the second conductivity type is N-type.
Further, the first conductivity type is N-type, and the second conductivity type is P-type.
Further, the substrate is a P-type or N-type lightly doped semiconductor material, typically bulk silicon, gallium nitride or silicon carbide.
Further, the substrate is an SOI substrate, and the SOI substrate comprises a P-type or N-type semiconductor layer with a conductive type and a dielectric layer positioned on the semiconductor layer.
The invention has the following beneficial effects:
The invention provides an LDMOS device capable of integrating two conduction type current carriers and simultaneously taking the two conduction type current carriers as a majority current carrier to participate in conduction respectively. Two active regions are formed on a substrate, two MOSFETs with opposite conduction types are respectively formed on the two active regions and the side close to a surface voltage-withstanding region, the grid electrode of one MOSFET is connected with a floating electrode, a heavily doped region for communicating the lower doped region of the floating electrode with a heavily doped body contact region in the MOSFET does not exist between the lower doped region of the floating electrode and the heavily doped body contact region in the MOSFET, when a conduction type carrier channel is opened to conduct electricity, if a conduction type carrier in the surface voltage-withstanding region reaches a drain electrode, a parasitic resistor needs to flow to form a voltage drop, and no additional control signal needs to be added, so that the opening of the other conduction type carrier channel can be automatically realized. The realization of the technical means of the invention obviously enhances the current capability of the device. In addition, the invention reasonably designs the device structure. The conductance modulation effect can be avoided, and the rapid turn-off of the unipolar device is further ensured. The manufacturing process of the invention is compatible with the existing manufacturing process, so that the manufacturing process can be manufactured without large-scale modification of the existing process during large-scale manufacturing for manufacturers. The invention can integrate SJ-nLDMOS and SJ-pLDMOS with similar current capability on a chip to manufacture related power integrated circuits under the same process, thereby improving the overall performance of the power integrated circuits manufactured by the device.
drawings
FIG. 1 is a schematic diagram of a conventional dual-layer RESURF pLDMOS structure in the prior art;
FIG. 2 is a schematic diagram of a conventional three-layer RESURF pLDMOS structure in the prior art;
fig. 3 is a dual-layer RESURF pLDMOS fabricated on a bulk silicon substrate according to an embodiment of the present invention;
fig. 4 is a three-layer RESURF pLDMOS fabricated on a bulk silicon substrate according to an embodiment of the present invention;
FIG. 5 is a diagram of a dual layer RESURF pLDMOS fabricated on an SOI substrate according to an embodiment of the present invention;
FIG. 6 is a three-layer RESURF pLDMOS fabricated on an SOI substrate according to an embodiment of the present invention;
FIG. 7 is a comparison graph of current capability obtained by simulation of pLDMOS of the 620V-voltage-withstanding dual-layer RESURF technology, nLDMOS of "silicon-limited" dual-layer and three-layer RESURF technologies, and pLDMOS in accordance with an embodiment of the present invention;
in the figure, 1 is a P-type substrate, 2 is an N-type source substrate region, 3 is a first N + body contact region, 4 is a first P + source region, 5 is a first gate dielectric layer, 6 is a first gate, 7 is a source metal, 8 is a second gate, 9 is a second floating electrode, 10 is a P-type drain region, 11 is a drain metal, 12 is a second gate dielectric layer, 13 is a second N + source region, 14 is a second P + body contact region, 15 is a first P-type semiconductor layer, 16 is a first N-type semiconductor layer, 17 is a first P + doped region, 18 is a first floating electrode, 19 is a second P + doped region, 20 is an N-type top layer, 21 is a second P-type semiconductor layer, 22 is a second N-type semiconductor layer, 23 is a dielectric layer, and 24 is a P-type substrate layer.
Detailed Description
the present invention is described more fully with reference to the accompanying drawings, in which like reference numerals denote like or similar components or elements, and the gist of the present invention is to provide a novel high voltage LDMOS, in which the LDMOS device of the present invention may be an N-type LDMOS (nLDMOS) or a P-type LDMOS (pLDMOS), and in the embodiment of the present invention, the pLDMOS is specifically used for description, and accordingly, the principle of the nLDMOS is similar.
example 1:
FIG. 3 shows a cellular structure of a pLDMOS device manufactured on a bulk silicon substrate, the cellular structure comprises a P-type substrate 1, an N-type source substrate region 2 located on one side of the top layer of the P-type substrate 1, a P-type drain region 10 located on the other side of the top layer of the P-type substrate 1, and a surface voltage-withstanding region located on the surface of the substrate 1 between the N-type source substrate region 2 and the P-type drain region 10, wherein the N-type source substrate region 2 is provided with a first N + body contact region 3 and a first P + source region 4 which are independent of each other, the surface of the device, which is in contact with the first N + body contact region 3 and the first P + source region 4, the first P + source region 4, the upper surfaces of part of the N-type source substrate region 2 and part of the voltage-withstanding region are provided with a first gate dielectric layer 5, the upper surface of the first gate dielectric layer 5 is provided with a first gate dielectric layer 6, the N-type source substrate region 2, the first N + body contact region 3, the first P + source region 4, the source region 7, the first gate dielectric layer 5 and the first gate dielectric layer 6 are formed by the first P surface voltage:
the surface voltage-withstanding region is formed by a first P-type semiconductor layer 15 and a first N-type semiconductor layer 16, wherein the first N-type semiconductor layer 16 partially surrounds the first P-type semiconductor layer 15 and is arranged on the upper surface of the substrate 1, the first P-type semiconductor layer 15 is arranged close to the N-type source substrate region 2, the upper surface of the first P-type semiconductor layer 15 and part of the upper surface of the first N-type semiconductor layer 16 form the surface of a device, two layers of semiconductor layers 15 and 16 in the surface voltage-withstanding region are both contacted with the N-type source substrate region 2, the first N-type semiconductor layer 16 in the surface voltage-withstanding region is contacted with the P-type drain region 10, the first P-type semiconductor layer 15 is not contacted with the P-type drain region 10, one end, close to the P-type drain region 10, of the first P-type semiconductor layer 15 is provided with a first P + doped region 17, and the upper surface of the first;
The P-type drain region 10 is provided with a second N + source region 13 and a second P + body contact region 14 which are independent of each other, the surface of a device is in contact with the second N + source region 13 and the second P + body contact region 14 through drain metal 11, the P-type drain region 10 is further provided with a second P + doped region 19, the upper surface of the second P + doped region 19 is provided with a second floating electrode 9, a P-type heavily doped semiconductor region which is used for communicating the second P + doped region 19 with the second P + body contact region 14 does not exist between the second P + doped region 19 and the second P + body contact region 14, the upper surfaces of the second N + source region 13, a part of the P-type drain region 10 and a part of the surface voltage-withstanding region are provided with a second gate dielectric layer 12, the upper surface of the second gate dielectric layer 12 is provided with a second gate 638, the second gate 8 is respectively connected with the first floating electrode 18 and the second floating electrode 9, the P-type drain region 10, the second N + source region 13, the second P + body contact region 14, the second P +, the second P doped region, the second P + doped region 19, the second floating electrode 19 and the second floating electrode 9 form a MOSFET near side channel-type drain region, and the second.
In the invention, the first floating electrode 18, the second floating electrode 9 and the second gate electrode 8 are connected together, so that the LDMOS device provided by the invention is still a three-terminal device.
Example 2:
FIG. 4 shows a cellular structure of a pLDMOS device manufactured on a bulk silicon substrate, which comprises a P-type substrate 1, an N-type source substrate region 2 positioned on one side of the top layer of the P-type substrate 1, a P-type drain region 10 positioned on the other side of the top layer of the P-type substrate 1, and a surface voltage-withstanding region positioned on the surface of the substrate 1 between the N-type source substrate region 2 and the P-type drain region 10, wherein the N-type source substrate region 2 is provided with a first N + body contact region 3 and a first P + source region which are independent from each other, the surface of the device, which is in contact with the first N + body contact region 3 and the first P + source region 4, is a source metal 7, the first P + source region 3, a part of the N-type source substrate 2 and the upper surface of the surface voltage-withstanding region are provided with a first gate dielectric layer 5, the upper surface of the first gate dielectric layer 5 is provided with a first gate 6, the N-type source substrate region 2, the first N + body contact region 3, the first P + source region 4, the source region, the source dielectric layer 5, the first gate dielectric layer 6 and the first P voltage-withstanding region are formed by the first surface voltage:
the surface voltage-withstanding region is formed by a second P-type semiconductor layer 21, a second N-type semiconductor layer 22 and an N-type top layer 20, part of the second N-type semiconductor layer 22 surrounds the second P-type semiconductor layer 21 and is arranged on the upper surface of the substrate 1, the second P-type semiconductor layer 21 is arranged close to the N-type source substrate region 2, the N-type top buried layer 20 is located at the top end of the second P-type semiconductor layer 21, the upper surface of the N-type top layer 20, the upper surface of part of the second P-type semiconductor layer 21 and the upper surface of part of the second N-type semiconductor layer 22 form a device surface, the two layers of semiconductor layers 21 and 22 in the surface voltage-withstanding region are both in contact with the N-type source substrate region 2, the second N-type semiconductor layer 22 in the surface voltage-withstanding region is in contact with the P-type drain region 10, the second P-type semiconductor layer 21 is not in contact with the P-type drain region 10, a first P + doped region 17 is arranged at the end, and a first empty electrode 18 is;
the P-type drain region 10 is provided with a second N + source region 13 and a second P + body contact region 14 which are independent of each other, the surface of a device is in contact with the second N + source region 13 and the second P + body contact region 14 through drain metal 11, the P-type drain region 10 is further provided with a second P + doped region 19, the upper surface of the second P + doped region 19 is provided with a second floating electrode 9, a P-type heavily doped semiconductor region which is used for communicating the second P + doped region 19 with the second P + body contact region 14 does not exist between the second P + doped region 19 and the second P + body contact region 14, the upper surfaces of the second N + source region 13, a part of the P-type drain region 10 and a part of the surface voltage-withstanding region are provided with a second gate dielectric layer 12, the upper surface of the second gate dielectric layer 12 is provided with a second gate 638, the second gate 8 is respectively connected with the first floating electrode 18 and the second floating electrode 9, the P-type drain region 10, the second N + source region 13, the second P + body contact region 14, the second P +, the second P doped region, the second P + doped region 19, the second floating electrode 19 and the second floating electrode 9 form a MOSFET near side channel-type drain region, and the second.
In the invention, the first floating electrode 18, the second floating electrode 9 and the second gate electrode 8 are connected together, so that the LDMOS device provided by the invention is still a three-terminal device.
example 3:
Fig. 5 shows a cell structure of a pLDMOS device fabricated on an SOI substrate according to the present invention, which is the same as embodiment 1 except that a P-type substrate 1 is replaced with an SOI substrate; the SOI substrate includes a substrate layer and an insulating medium layer 23 located on the substrate layer, the doping type of the substrate layer may be P-type or N-type, and the N-type substrate layer 24 is selected in this embodiment.
Example 4:
FIG. 6 shows a cell structure of a pLDMOS device fabricated on an SOI substrate according to the present invention, which is the same as that of embodiment 2 except that a P-type substrate 1 is replaced with an SOI substrate; the SOI substrate comprises a substrate layer and an insulating medium layer 23 positioned on the substrate layer, the doping type of the substrate layer can be P type or N type, and an N type substrate layer 24 is selected in the embodiment.
based on the embodiments disclosed above, the following detailed description will be made of the principles of the present invention with reference to the accompanying drawings:
When the first conduction type is P type and the second conduction type is N type, the first active region is internally provided with a source substrate region which is made of N type semiconductor material and is also provided with an independent P + type region and an N + type region, the P + type region and the N + type region are adjacent and are contacted with a metal conductor to form a source electrode of the MOSFET of the first conduction type, the partial P + type region, the partial N type source substrate region and the partial surface voltage-resisting region are provided with dielectric layers, the upper surface of the dielectric layer is provided with a metal conductor to form a gate electrode of the P type MOSFET, the second active region is a drain end of the P type MOSFET, the second active region is internally provided with a source substrate region which is made of P type semiconductor material, the source substrate region is also provided with another independent P + type region and another N + type region, the P + type region and the N + type region are adjacent and are contacted with the metal conductor to form a source region of the second conduction type MOSFET, the P type source region and the other N type source region are also provided with another P + type drain region and another N + type dielectric layer, the same as the P type source region, the P type semiconductor layer + type source region, and the upper surface of the other N type dielectric layer of the MOSFET, and the drain end of the first conduction type MOSFET are provided with;
when the first conductivity type is P-type and the second conductivity type is N-type, as shown in the drawing of the specification, the second P + body contact region 14 is used as an electrode contact region and has a second P + doped region 19 spaced apart from the electrode contact region, and since there is no heavily doped P + semiconductor region between the two, in other words, there is a large parasitic resistance in the P-type semiconductor region between the two (i.e., the drain region 10 between the two), when the P-type MOSFET is turned on under an external voltage, a P-type carrier (hole) in the P-type semiconductor layer 15 in the surface voltage-withstanding region needs to flow through the parasitic resistance of the P-type semiconductor region between the second P + doped region 19 and the second P + body contact region 14 if it wants to reach the drain electrode, a voltage difference generated by the second P + doped region 19 relative to the second P + body contact region 14 is a positive value due to the current on the parasitic resistance, and since the second P-type electrode 9 of the second P + doped region 19 is connected to the second floating gate electrode 8, the voltage difference between the second P-type floating gate electrode 9 and the N-type gate electrode is further used as a surface voltage-withstanding region of the N-type MOSFET, thereby realizing that the voltage difference of the N-type MOSFET (N-type semiconductor layer) is turned on the surface of the N-type.
Similarly, when the first conductivity type is N-type and the second conductivity type is P-type, the invention uses the second N + body contact region as the electrode contact region, and sets the second N + doped region isolated from the second N + body contact region, in other words, there is no heavily doped N + semiconductor region communicating the two between the two, and in the N-type semiconductor region between the two (i.e. the drain region 10 between the two), there is a larger parasitic resistance, so that after the N-type MOSFET is turned on under an applied voltage, if an N-type carrier (electron) in the N-type semiconductor layer in the surface voltage-withstanding region wants to reach the drain electrode 11, the electron must flow through the parasitic resistance of the N-type semiconductor region between the second N + doped region and the second N + body contact region, and the current on the parasitic resistance makes the voltage difference between the N + doped region and the N + body contact region negative, and because the floating electrode on the N + doped region is connected to the second gate electrode 8, thereby realizing that the P-type MOSFET (i.e. formed by the second active region and the P-type semiconductor layer) in the surface voltage-withstanding region is also used as the P-type channel semiconductor layer (P-type dielectric) under the P-type channel semiconductor layer).
Referring to the drawings of the specification, in order to reasonably design the distribution of each semiconductor region and electrode on the surface of the cell structure, according to the coordinate system in the drawing, in this embodiment, the second P + body contact region 14 and the second P + doped region 19 are both disposed in the z direction as shown in the drawing, the distance between the second P + body contact region 14 and the second P + doped region 19 is defined as W 2, the length of the second P + body contact region 14 in the z direction is defined as W 3, and since the P-type drain region 10 between the second P + body contact region 14 and the second P + doped region 19 has a substrate bias effect, and the P-type drain region 10 below the second P + body contact region 14 does not have a substrate bias effect, the larger the length of the second P + body contact region 14 in the z direction is, the larger the ratio of the electron current in the N-type semiconductor layer 15 in the surface voltage-withstanding region to the total current is, so that the average current density of the device is larger, and eventually tends to be saturated.
As a preferred embodiment, W 2 is not less than 20 μm;
Further, the length of the second heavily doped source region 13 in the z direction is defined as L 13, and the length of the second heavily doped body contact region 14 in the z direction is defined as L 14, L 13 may be greater than L 14, L 13 may be less than L 14, and L 13 may also be equal to L 14;
In order to avoid conductance modulation effects, L 14 and L 13 are chosen such that L 13 -L 14 ≦ 50 μm.
Fig. 7 shows a resistance 620V P LDMOS designed based on the dual layer RESURF technique according to the present invention as shown in fig. 3. it can be seen from fig. 7 that even without optimization, the voltage difference generated on the path from the second P + doped region 19 to the second P + body contact region 14 gradually increases as the source-drain voltage of the device turns on, when the device source-drain voltage increases to about 1.5V, the voltage drop causes the N-type channel under the second gate dielectric layer 12 to open, thereby causing a large amount of electrons in the N-type semiconductor layer 16 in the surface resistance region to participate in conduction, assuming that the nominal conduction voltage drop of the 620V LDMOS is around 5V, the current capability of the device is comparable to the "silicon limit" of the nLDMOS based on the dual layer RESURF technique, much greater than the "silicon limit" of the P-type LDMOS of the dual layer or even triple layer RESURF technique, as the current capability of the second P + body contact region 14 in the P-type region (i.e. the P-type drain region 10) between the first P + doped region 19, the P-type drain region 10, and the second P3514, and the P3514, the total current density of the second P-doped region tends to increase as shown in the P3514, the P19, and the average current density of the P19, and the P19, thus the current density of the P19, and.
On the other hand, as W 2 increases, the voltage difference between the second P + doped region 19 and the second P + body contact region 14 in the embodiment of fig. 7 is 28 μm, so that the electron channel under the second gate dielectric layer 12 is turned on at a lower source drain voltage, and at this time, the device will obtain a higher current at a lower source drain voltage.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto without departing from the scope and spirit of the invention as set forth in the claims that follow.
Claims (7)
1. an LDMOS device, the cellular structure of which comprises: the semiconductor device comprises a substrate, a second conductive type semiconductor source substrate region positioned on one side of the top layer of the substrate, a first conductive type semiconductor drain region positioned on the other side of the top layer of the substrate, and a surface voltage-resistant region positioned on the surface of the substrate between the second conductive type semiconductor source substrate region and the first conductive type semiconductor drain region; the second conductive type semiconductor source substrate region is provided with a first second conductive type heavily doped body contact region and a first conductive type heavily doped source region which are independent of each other; the device surface is contacted with the first heavily doped body contact region of the second conduction type and the first heavily doped source region of the first conduction type through source metal, the upper surfaces of the first heavily doped source region of the first conduction type, part of the substrate region of the second conduction type semiconductor and part of the surface voltage-resisting region are provided with first gate dielectric layers, and the upper surface of each first gate dielectric layer is provided with a first gate; the second conductive type semiconductor source substrate region, the first second conductive type heavily doped body contact region, the first conductive type heavily doped source region, the source metal, the first gate dielectric layer and the first gate form a first active region, and a first conductive type MOSFET is formed on the side close to the first active region and the surface voltage-resisting region; the method is characterized in that:
The surface voltage-withstanding region is formed by a first conduction type semiconductor layer and a second conduction type semiconductor layer, the second conduction type semiconductor layer partially surrounds the first conduction type semiconductor layer and is arranged on the upper surface of the substrate, the first conduction type semiconductor layer is arranged close to the second conduction type semiconductor source substrate region, two layers of semiconductor layers in the surface voltage-withstanding region are both contacted with the second conduction type semiconductor source substrate region, the second conduction type semiconductor layer in the surface voltage-withstanding region is contacted with the first conduction type semiconductor drain region, and the first conduction type semiconductor layer is not contacted with the first conduction type semiconductor drain region; one end of the first conduction type semiconductor layer, which is close to the first conduction type semiconductor drain region, is provided with a first conduction type heavily doped semiconductor region I, and the upper surface of the first conduction type heavily doped semiconductor region I is provided with a first floating electrode;
The first conductive type semiconductor drain region is provided with a second conductive type heavily doped source region and a second conductive type heavily doped body contact region which are independent of each other; the surface of the device is in contact with a second heavily doped source region of a second conductivity type and a second heavily doped body contact region of the first conductivity type, drain metal is arranged in the drain region of the semiconductor of the first conductivity type, a second heavily doped semiconductor region of the first conductivity type is arranged in the drain region of the semiconductor of the first conductivity type, a second floating electrode is arranged on the upper surface of the second heavily doped semiconductor region of the first conductivity type, a first heavily doped semiconductor region of the first conductivity type which is used for communicating the second heavily doped semiconductor region of the first conductivity type with the second heavily doped body contact region of the first conductivity type does not exist between the second heavily doped semiconductor region of the first conductivity type and the second heavily doped body contact region of the first conductivity type, a second gate dielectric layer is arranged on the upper surface of the second heavily doped source region of the second conductivity type, a part of the drain region of the semiconductor of the first conductivity; the first conductive type semiconductor drain region, the second conductive type heavily doped source region II, the first conductive type heavily doped body contact region II, the first conductive type heavily doped semiconductor region II, the drain metal, the second gate dielectric layer, the second gate and the second floating electrode form a second active region, and the second active region and the surface voltage-resisting region are close to form a second conductive type MOSFET.
2. The LDMOS device of claim 1, wherein the surface voltage withstand region further comprises a top layer of the second conductivity type partially enclosed in the semiconductor layer of the first conductivity type, and an upper surface of the top layer of the second conductivity type coincides with a device upper surface.
3. an LDMOS device as claimed in claim 1 or 2 wherein the second heavily doped source region of the second conductivity type and the second heavily doped body contact region of the first conductivity type are arranged in parallel, and the longitudinal lengths of the second heavily doped source region of the second conductivity type and the second heavily doped body contact region of the first conductivity type are defined as L 13 and L 14 respectively, which satisfy L 13 -L 14 ≦ 50 μm.
4. An LDMOS device as claimed in claim 3 wherein said substrate is a lightly doped semiconductor material of either the first or second conductivity type, said semiconductor material being bulk silicon, gallium nitride or silicon carbide.
5. An LDMOS device as in claim 3 wherein said substrate is an SOI substrate comprising a semiconductor layer of a first conductivity type or a second conductivity type and a dielectric layer thereon.
6. An LDMOS device as claimed in claim 4 or 5 characterized in that the first conductivity type is P-type and the second conductivity type is N-type.
7. an LDMOS device as claimed in claim 4 or 5 characterized in that the first conductivity type is N-type and the second conductivity type is P-type.
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| CN103426913A (en) * | 2013-08-09 | 2013-12-04 | 电子科技大学 | Partial SOI (silicon on insulator) super junction high-voltage power semiconductor device |
| CN103441147A (en) * | 2013-08-09 | 2013-12-11 | 电子科技大学 | Lateral direction SOI power semiconductor device |
| US9076671B2 (en) * | 2011-08-04 | 2015-07-07 | Texas Instruments Incorporated | Power integrated circuit including series-connected source substrate and drain substrate power mosfets |
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| US9076671B2 (en) * | 2011-08-04 | 2015-07-07 | Texas Instruments Incorporated | Power integrated circuit including series-connected source substrate and drain substrate power mosfets |
| CN103426913A (en) * | 2013-08-09 | 2013-12-04 | 电子科技大学 | Partial SOI (silicon on insulator) super junction high-voltage power semiconductor device |
| CN103441147A (en) * | 2013-08-09 | 2013-12-11 | 电子科技大学 | Lateral direction SOI power semiconductor device |
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