CN107359193A - A kind of LDMOS device - Google Patents
A kind of LDMOS device Download PDFInfo
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- CN107359193A CN107359193A CN201710631158.2A CN201710631158A CN107359193A CN 107359193 A CN107359193 A CN 107359193A CN 201710631158 A CN201710631158 A CN 201710631158A CN 107359193 A CN107359193 A CN 107359193A
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- 239000000758 substrate Substances 0.000 claims abstract description 87
- 238000007667 floating Methods 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims description 112
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 5
- 238000011982 device technology Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 210000004027 cell Anatomy 0.000 description 6
- 108091006146 Channels Proteins 0.000 description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000003796 beauty Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009510 drug design Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Abstract
The present invention provides a kind of LDMOS device, belongs to power device technology field.The structure cell of LDMOS device of the present invention includes：Substrate, the resistance to nip in surface positioned at first active area at substrate both ends and the second active area and between two active areas；The first active area nip resistance to surface mutually forms the MOSFET of the first conduction type close to side, and the second active area nip resistance to surface mutually forms the MOSFET of the second conduction type close to side；By setting floating area respectively in the pressure-resistant area in device drain region and surface, and Liang Ge floatings area and drain region grid are electrically connected to form three terminal device, and then realize in the case where additionally not increasing control signal, two kinds of carrier can be realized automatically while each participates in conduction as majority carrier, and does not form conductivity modulation effect.The present invention also achieves rapidly switching off for unipolar device, and the LDMOS that the present invention can integrate two kinds of different conduction-types under same technique but current capacity is close while device current capability is significantly increased.
Description
Technical field
The invention belongs to power semiconductor technologies field, and in particular to a kind of high voltage lateral semiconductor device.
Background technology
The minimizing of power electronic system, it is integrated be power semiconductor an important research direction.Intelligent work(
Rate integrated circuit (Smart Power Integrated Circuit, SPIC) or high voltage integrated circuit (High Voltage
Integrated Circuit, HVIC) low-voltage circuits such as protection, control, detection, driving and high voltage power device are integrated in together
On one chip, system bulk is so not only reduced, improves system reliability.Meanwhile in the workplace of upper frequency,
Due to the reduction of system lead-in inductance, for buffering with for protection circuit, its requirement can be significantly reduced.
Lateral double diffusion metal oxide field-effect transistor (Lateral Double-diffused Metal Oxide
Field Effect Transistor, LDMOS) be SPIC or HVIC key technology.With reduction surface field technology
The invention of (Reduce SURface Field, RESURF) technology, people no longer need to use thick extension to make high withstand voltage
Power semiconductor, and traditional low pressure integrated technology can be utilized to make high pressure and low pressure integrates simultaneously on thin epitaxial layer
Circuit.However, high pressure is born in the lateral power drift region that needs to grow very much, therefore it is than conducting resistance Ron,spIt is often higher.
So the key issue for designing lateral power is that：How breakdown voltage (Breakdown Voltage is optimized：BV)
With than conducting resistance Ron,spThe tradeoff of the two, and then alleviate the BV and R of high-voltage LDMOSon,spBetween contradictory relation.
For in BV and Ron,spBetween obtain more excellent tradeoff, J.S.Ajit et al. in June, 1993《Power semiconductor
The 5th international symposium of device and integrated circuit》In propose double-deck RESURF (double RESURF) technology.Such as Fig. 1 institutes
A kind of p-type LDMOS (referred to as pLDMOS) structure based on double-deck RESURF Technology designs is shown as, it is resistance to by doping compensation
Nip p type impurity dosage improves about 2 times, and than conducting resistance Ron,spDecline.Further to reduce the R of LDMOS deviceon,sp,
D.R.Disney was at 2 months 2001《The 13rd international symposium of power semiconductor and integrated circuit》In propose three layers
RESURF (Triple RESURF) technology.It is illustrated in figure 2 a kind of pLDMOS devices based on three layers of RESURF Technology designs
Structure.
However, the pLDMOS devices based on traditional RESURF Technology designs are only by hole conduction, so its Ron,spAbout N
3 times of type LDMOS (nLDMOS) device, this point are totally unfavorable for saving chip area and system power dissipation.Therefore,
In order to improve pLDMOS current capacity, B.Yi et al. in article《A 300V Ultra Low Specific On-
Resistance High-Side p-LDMOS with Auto-biased n-LDMOS for SPIC》(《One kind has extremely low
300V than conducting resistance carries automatic bias nLDMOS high side pLDMOS》) in propose a kind of electronics participate in it is conductive
PLDMOS devices, but above-mentioned pLDMOS devices need external diode and electric capacity, and need a phase inverter to realize electricity
Sub-channel is switched on and off；In addition, the shut-off of above-mentioned pLDMOS devices also has a delayed phase, which increases system
Loss.In summary, how to strengthen LDMOS device current capacity, especially strengthen the current capacity of pLDMOS devices, simultaneously
Realize that it becomes this area technical problem urgently to be resolved hurrily as rapidly switching off for unipolar device again, therefore, need one kind badly
The method that can solve the problem that above-mentioned technical problem.
The content of the invention
The technical problems to be solved by the invention are：LDMOS device current capacity can be significantly increased again by providing one kind
Energy realization rapidly switches off and the novel high-pressure LDMOS device of compatible existing RESURF technologies.
In order to solve the above-mentioned technical problem, the present invention provides following technical scheme：
A kind of LDMOS device, its structure cell include：Substrate, the second conduction type positioned at the substrate top layer side
Semiconductor source substrate zone, lead positioned at the first conductive type semiconductor drain region of the substrate top layer opposite side, positioned at described second
The resistance to nip in surface of substrate surface between electric type semiconductor source substrate zone and the first conductive type semiconductor drain region；Described second
Have the second separate conduction type heavy doping body contact zone one and first conductive in the substrate zone of conductive type semiconductor source
Type heavy doping source region one；Device surface and the second conduction type heavy doping body contact zone one and the first conduction type heavy-doped source
What area one contacted is source metal, the first conduction type heavy doping source region one, part the second conductive type semiconductor source substrate zone
There is the first gate dielectric layer with the upper surface of the resistance to nip of part surface, the upper surface of first gate dielectric layer has the first grid
Pole；The second conductive type semiconductor source substrate zone, the second conduction type heavy doping body contact zone one, the first conduction type weight
Doping source region, source metal, the first gate dielectric layer and first grid form the first active area, the resistance to nip of the first active area and surface
Mutually the first conduction type MOSFET is formed close to side；It is characterized in that：
The resistance to nip in surface is formed by the first conductive type semiconductor layer and second conductive type semiconductor layer, and described
Two conductive type semiconductor layer parts surround the upper surface that the first conductive type semiconductor layer is arranged at substrate, the first conduction type
Semiconductor layer is set close to the second conductive type semiconductor source substrate zone, and two layers of semiconductor layer is with described the in the resistance to nip in surface
Two conductive type semiconductor source substrate zones contact, second conductive type semiconductor layer and the first conduction type half in the resistance to nip in surface
Conductor drain contact, and in the resistance to nip in surface the first conductive type semiconductor not with the first conductive type semiconductor drain contact；
The first conductive type semiconductor layer has the first conduction close to the one end in the first conductive type semiconductor drain region in the resistance to nip in surface
Type heavily-doped semiconductor area one, the upper surface of the first conduction type heavily-doped semiconductor area one have the first floating electrode；
There is the separate He of the second conduction type heavy doping source region two in the first conductive type semiconductor drain region
First conduction type heavy doping body contact zone two；Device surface and the second conduction type heavy doping source region two and the first conduction type
What heavy doping body contact zone two contacted is drain metal, also has the first conductive-type in the first conductive type semiconductor drain region
Type heavily-doped semiconductor area two, the first conduction type heavily-doped semiconductor area upper surface has the second floating electrode, described
It is not present between first conduction type heavily-doped semiconductor area two and the first conduction type heavy doping body contact zone two and connects the two
The first logical conduction type heavily-doped semiconductor region, the second conduction type heavy doping source region two, the conduction type of part first half
Conductor drain region (10) and the upper surface of the resistance to nip of part surface have the second gate dielectric layer, the upper surface of second gate dielectric layer
With second grid, the second grid is connected with the first floating electrode and the second floating electrode respectively；Described first is conductive
Type semiconductor drain region, the second conduction type heavy doping source region two, the first conduction type heavy doping body contact zone two, first are conductive
It is active that type heavily-doped semiconductor area two, drain metal, the second gate dielectric layer, second grid and the second floating electrode form second
Area, the second active area and the resistance to nip in surface mutually form the second conduction type MOSFET close to side.
It is further that the resistance to nip in surface of the present invention also includes being additionally partially enclosed in first conductive type semiconductor layer
In the second conduction type top layer, the upper surface of the second conduction type top layer overlaps with device upper surface.
It is further the second conduction type heavy doping source region two and the first conduction type heavy doping body contact zone two
It is set up in parallel, defines the longitudinal length of the second conduction type heavy doping source region two and the first conduction type heavy doping body contact zone two
Respectively L13And L14, then the two meet：L13-L14≦50μm。
It is further that the first conduction type is p-type, the second conduction type is N-type.
It is further that the first conduction type is N-type, the second conduction type is p-type.
Further that the substrate is that semi-conducting material is lightly doped in p-type or N-type, usually body silicon, gallium nitride or
Carborundum.
Further, the substrate is SOI substrate, and the SOI substrate is p-type or N-type semiconductor including conduction type
Layer and dielectric layer disposed thereon.
Beneficial effects of the present invention are as follows：
The present invention proposes one kind and can integrate two kinds of conduction type carriers while each participate in leading as majority carrier
The LDMOS device of electricity.By forming two active areas on substrate, two active areas nip resistance to surface is mutually close to side difference shape
The MOSFET opposite into two conduction types, one of MOSFET grid are connected with floating electrode, and are mixed under floating electrode
The heavily doped region for connecting the two is not present between miscellaneous area and heavy doping body contact zone in the MOSFET, when a kind of conduction type
After carrier channels open conduction, a kind of carrier of conduction type of this in the resistance to nip in surface need to flow through parasitism to reach drain electrode
Resistance forms voltage drop, without increasing extra control signal, you can realize another conduction type carrier channels automatically
Open.The realization of this technological means of the invention significantly enhances the current capacity of device.In addition, the present invention passes through rational design
Device architecture.Conductivity modulation effect can be avoided the formation of, and then ensures rapidly switching off as unipolar device.The present invention makes
Technique is compatible with existing manufacture craft, therefore existing process need not be advised greatly in extensive manufacture for manufacturer
Mould transformation can make.The present invention can under same technique on chip SJ-nLDMOS and SJ- similar in integrated current ability
PLDMOS come make correlation power integrated circuit, and then improve by element manufacturing of the present invention power integrated circuit globality
Energy.
Brief description of the drawings
Fig. 1 is conventional double RESURF pLDMOS structural representations in the prior art；
Fig. 2 is traditional three layers of RESURF pLDMOS structural representations in the prior art；
Fig. 3 is a kind of double-deck RESURF pLDMOS being produced on body silicon substrate provided in an embodiment of the present invention；
Fig. 4 is a kind of three layers of RESURF pLDMOS being produced on body silicon substrate provided in an embodiment of the present invention；
Fig. 5 is a kind of double-deck RESURF pLDMOS made on soi substrates provided in an embodiment of the present invention；
Fig. 6 is a kind of three layers of RESURF pLDMOS made on soi substrates provided in an embodiment of the present invention；
Fig. 7 is pLDMOS and double-deck and three layer RESURF skill of the embodiment of the present invention to pressure-resistant 620V bilayers RESURF technologies
The nLDMOS and pLDMOS of art " the silicon limit " emulate to obtain current capacity comparison diagram；
In figure, 1 is P type substrate, and 2 be N-type source substrate zone, and 3 be the first N+Body contact zone, 4 be the first P+Source region, 5 be first
Gate dielectric layer, 6 be first grid, and 7 be source metal, and 8 be second grid, and 9 be the second floating electrode, and 10 be p-type drain region, and 11 are
Drain metal, 12 be the second gate dielectric layer, and 13 be the 2nd N+Source region, 14 be the 2nd P+Body contact zone, 15 be the first P-type semiconductor
Layer, 16 be the first n type semiconductor layer, and 17 be the first P+Doped region, 18 be the first floating electrode, and 19 be the 2nd P+Doped region, 20 are
N-type top layer, 21 be the second p type semiconductor layer, and 22 be the second n type semiconductor layer, and 23 be dielectric layer, and 24 be P type substrate layer.
Embodiment
The present invention is described more fully with reference to the accompanying drawings, in Figure of description, identical label represents phase
With either similar component or element, main idea of the present invention is to provide a kind of novel high-pressure LDMOS, and LDMOS device of the present invention can
To be N-type LDMOS (nLDMOS) or p-type LDMOS (pLDMOS), the embodiment of the present invention is specifically said with pLDMOS
Bright, correspondingly, nLDMOS principles are similar.
Embodiment 1：
Fig. 3 shows the structure cell for the pLDMOS devices that the present invention is produced on body silicon substrate, including：P type substrate 1,
N-type source substrate zone 2 positioned at the top layer side of P type substrate 1, positioned at the p-type drain region 10 of the top layer opposite side of P type substrate 1,
The resistance to nip in surface on the surface of substrate 1 between N-type source substrate zone 2 and p-type drain region 10；Have in N-type source substrate zone 2
There is the first separate N+The P of body contact zone 3 and the first+Source region 4；Device surface and the first N+The P of body contact zone 3 and the first+Source region
4 contacts are source metals 7, the first P+The upper surface of source region 4, part N-type source substrate zone 2 and the resistance to nip of part surface has the
One gate dielectric layer 5, the upper surface of first gate dielectric layer 5 have first grid 6；N-type source substrate zone 2, the first N+Body
Contact zone 3, the first P+Source region 4, source metal 7, the first gate dielectric layer 5 and first grid 6 form the first active area, and first is active
Area mutually forms the MOSFET of P-type channel with the resistance to nip in surface close to side；It is characterized in that：
The resistance to nip in surface is formed by the first p type semiconductor layer 15 and the first n type semiconductor layer 16, first N-type
The part of semiconductor layer 16 surrounds the upper surface that the first p type semiconductor layer 15 is arranged at substrate 1, and the first p type semiconductor layer 15 is close
N-type source substrate zone 2 is set, and the upper surface of the first p type semiconductor layer 15 and the portion of upper surface of the first n type semiconductor layer 16 are formed
Device surface；Two layers of semiconductor layer 15,16 contacts with N-type source substrate zone 2 in the resistance to nip in surface, in the resistance to nip in surface
One n type semiconductor layer 16 contacts with p-type drain region 10, and the first p type semiconductor layer 15 does not contact with p-type drain region 10；First p-type half
Conductor layer 15 has the first P close to the one end in p-type drain region 10+Doped region 17, the first P+The upper surface of doped region 17 has the
One floating electrode 18；
There is the 2nd separate N in the p-type drain region 10+The P of source region 13 and the 2nd+Body contact zone 14；Device surface with
2nd N+The P of source region 13 and the 2nd+What body contact zone 14 contacted is drain metal 11, also has the 2nd P in the p-type drain region 10+Mix
Miscellaneous area 19, the 2nd P+The upper surface of doped region 19 has the second floating electrode 9, the 2nd P+The P of doped region 19 and the 2nd+
It is not present the p-type heavily-doped semiconductor region of the two connection, the 2nd N between body contact zone 14+Source region 13, part p-type drain region
10 and the upper surface of the resistance to nip of part surface there is the second gate dielectric layer 12, the upper surface of second gate dielectric layer 12 has the
Two grids 8, the second grid 8 are connected with the first floating electrode 18 and the second floating electrode 9 respectively；The p-type drain region 10,
2nd N+Source region 13, the 2nd P+Body contact zone 14, the 2nd P+Doped region 19, drain metal 11, the second gate dielectric layer 12, second gate
The floating electrode 9 of pole 8 and second forms the second active area, and the second active area mutually forms N-type channel with the resistance to nip in surface close to side
MOSFET。
First floating electrode 18 in the present invention, the second floating electrode 9 and second grid 8 interconnect, because
This, LDMOS device proposed by the present invention is still a three terminal device.
Embodiment 2：
Fig. 4 shows that the present invention is produced on the structure cell of pLDMOS devices on body silicon substrate, including：P type substrate 1, position
N-type source substrate zone 2 in the top layer side of P type substrate 1, positioned at p-type drain region 10, the position of the top layer opposite side of P type substrate 1
The resistance to nip in surface on the surface of substrate 1 between N-type source substrate zone 2 and p-type drain region 10；Have in N-type source substrate zone 2
The first separate N+The P of body contact zone 3 and the first+Source region；Device surface and the first N+The P of body contact zone 3 and the first+Source region 4 connects
Tactile is source metal 7, the first P+The upper surface of source region 3, part N-type source substrate 2 and the resistance to nip of part surface has the first grid
Dielectric layer 5, the upper surface of first gate dielectric layer 5 have first grid 6；N-type source substrate zone 2, the first N+Body contacts
Area 3, the first P+Source region 4, source metal 7, the first gate dielectric layer 5 and first grid 6 form the first active area, the first active area and
The resistance to nip in surface mutually forms the MOSFET of P-type channel close to side；It is characterized in that：
The resistance to nip in surface is formed by the second p type semiconductor layer 21, the second n type semiconductor layer 22 and N-type top layer 20, institute
State the part of the second n type semiconductor layer 22 and surround the upper surface that the second p type semiconductor layer 21 is arranged at substrate 1, the second P-type semiconductor
Layer 21 is set close to N-type source substrate zone 2, and N-type top buried regions 20 is located at the top of the second p type semiconductor layer 21, N-type top layer 20
Upper surface, the portion of upper surface of the second p type semiconductor layer 21 and the portion of upper surface of the second n type semiconductor layer 22 form device surface；
Two layers of semiconductor layer 21,22 is contacted with N-type source substrate zone 2 in the resistance to nip in surface, and the second N-type is partly led in the resistance to nip in surface
Body layer 22 contacts with p-type drain region 10, and the second P-type semiconductor 21 does not contact with p-type drain region 10；Second p type semiconductor layer 21 leans on
The nearly end of p-type drain region 10 has the first P+Doped region 17, the first P+The upper surface of doped region 17 has the first floating electrode 18；
There is the 2nd separate N in the p-type drain region 10+The P of source region 13 and the 2nd+Body contact zone 14；Device surface with
2nd N+The P of source region 13 and the 2nd+What body contact zone 14 contacted is drain metal 11, also has the 2nd P in the p-type drain region 10+Mix
Miscellaneous area 19, the 2nd P+The upper surface of doped region 19 has the second floating electrode 9, the 2nd P+The P of doped region 19 and the 2nd+
It is not present the p-type heavily-doped semiconductor region of the two connection, the 2nd N between body contact zone 14+Source region 13, part p-type drain region
10 and the upper surface of the resistance to nip of part surface there is the second gate dielectric layer 12, the upper surface of second gate dielectric layer 12 has the
Two grids 8, the second grid 8 are connected with the first floating electrode 18 and the second floating electrode 9 respectively；The p-type drain region 10,
2nd N+Source region 13, the 2nd P+Body contact zone 14, the 2nd P+Doped region 19, drain metal 11, the second gate dielectric layer 12, second gate
The floating electrode 9 of pole 8 and second forms the second active area, and the second active area mutually forms N-type channel with the resistance to nip in surface close to side
MOSFET。
First floating electrode 18 in the present invention, the second floating electrode 9 and second grid 8 interconnect, because
This, LDMOS device proposed by the present invention is still a three terminal device.
Embodiment 3：
Fig. 5 shows that the present invention makes the structure cell of pLDMOS devices on soi substrates, this implementations and except by p-type
Substrate 1 is replaced with beyond SOI substrate, and remaining structure is same as Example 1；Wherein, SOI substrate includes substrate layer and positioned at institute
The insulating medium layer 23 on substrate layer is stated, the doping type of the substrate layer can be p-type, or N-type, the present embodiment
From N-type substrate layer 24.
Embodiment 4：
Fig. 6 shows that the present invention makes the structure cell of pLDMOS devices on soi substrates, this implementations and except by p-type
Substrate 1 is replaced with beyond SOI substrate, and remaining structure is same as Example 2；SOI substrate includes substrate layer and positioned at the lining
Insulating medium layer 23 on bottom, the doping type of the substrate layer can be p-type, or N-type, the present embodiment are selected
N-type substrate layer 24.
Based on embodiment disclosed above, the principle of the invention is described in detail with reference to Figure of description：
The first active area forms the MOSFET of the first conduction type with the resistance to nip in surface in the present invention, when the first conductive-type
Type is p-type, when the second conduction type is N-type：Source substrate zone, institute are formed using N-type semiconductor material in first active area
The source substrate zone of stating also has independent P+Type area and N+Type area, the P+Type area and N+Type area is adjacent and is contacted with metallic conductor
Form the MOSFET of the first conduction type source electrode, the part P+Type area, part N-type source substrate zone and part surface are pressure-resistant
There is dielectric layer, the dielectric layer upper surface has the gate electrode that metallic conductor forms p-type MOSFET, and now second is active in area
Area is p-type MOSFET drain terminal；Source substrate zone, the source substrate are formed using p-type semiconductor material in second active area
Area equally has independent another P+Type area and another N+Type area, the P+Type area and N+Type area is adjacent and is connect with metallic conductor
Touch the source electrode for the MOSFET for forming second of conduction type, the part P+It is same on type area, p-type drain region and the resistance to nip of part surface
Sample has another dielectric layer, and the dielectric layer upper surface has the gate electrode that metallic conductor forms N-type MOSFET, and now first has
Source region is N-type MOSFET drain terminal；
When the first conduction type is p-type, and the second conduction type is N-type, from the point of view of Figure of description, the present invention uses
2nd P+Body contact zone 14 is used as electrode contact region, and with the 2nd P for separating setting therewith+Doped region 19, due to the two it
Between be not present by the two connection heavy doping P+Semiconductor region, in other words, P-type semiconductor region therebetween is (namely
Therebetween drain region 10) larger dead resistance be present, thus, after p-type MOSFET is opened under applied voltage, surface is pressure-resistant
P-type carrier (hole) if wanting to reach drain electrode, has to flow through the 2nd P in p type semiconductor layer 15 in area+Doped region 19 with
2nd P+The dead resistance of P-type semiconductor region between body contact zone 14, the electric current during this in dead resistance make
Obtain the 2nd P+Doped region 19 is relative to the 2nd P+Voltage difference caused by body contact zone 14 be on the occasion of；Again due to the 2nd P+Doped region 19
The second floating electrode 9 be connected with the second gate electrode 8, above-mentioned voltage difference causes the N-type channel under the second gate dielectric layer 12 to open,
It is achieved thereby that the N-type MOSFET that the second active area is formed with n type semiconductor layer 16 in the resistance to nip in surface is automatically turned on, and then
So that N-type carrier (electronics) participates in conduction as majority carrier in the resistance to nip in surface.
Similarly, when the first conduction type is N-type, and the second conduction type is p-type, the present invention uses the 2nd N+Body contact zone
As electrode contact region, and the 2nd N being isolated therewith is set+Doped region, the two is connected due to being not present therebetween
Heavy doping N+Semiconductor region, in other words, N-type semiconductor region (drain region 10 namely therebetween) therebetween are deposited
In larger dead resistance, thus, after N-type MOSFET is opened under applied voltage, N-type in n type semiconductor layer in the resistance to nip in surface
Carrier (electronics) has to flow through the 2nd N if wanting to reach drain electrode 11+Doped region and the 2nd N+N-type half between body contact zone
The dead resistance of conductive region, the electric current during this in dead resistance cause N+Doped region is relative to N+Body contact zone
Caused voltage difference is negative value, and due to N+Floating electrode on doped region is connected with the second gate electrode 8, it is achieved thereby that automatically
P type semiconductor layer is formed in the second active area and the resistance to nip in surface p-type MOSFET is opened (under namely the second gate medium 12
P-type channel), and then make it that p-type carrier (hole) participates in conductive as majority carrier in the resistance to nip in surface.
From the point of view of Figure of description, in order to rationally design point of each semiconductor regions and electrode on structure cell surface
Cloth, according to coordinate system in figure, the 2nd P in the present embodiment+The P of body contact zone 14 and the 2nd+Doped region 19 is arranged at as schemed institute
Show z directions, define the 2nd P+The P of body contact zone 14 and the 2nd+The distance between doped region 19 is W2, define the 2nd P+Body contact zone
14 length in a z-direction is W3, due to the 2nd P+The P of body contact zone 14 and the 2nd+P-type drain region 10 between doped region 19 is present
Body bias effect, and the 2nd P+Body bias effect is not present in the p-type drain region 10 of the lower section of body contact zone 14, so, the 2nd P+Body contact zone 14
Length in z directions is bigger, and the electronic current for participating in conduction in the resistance to nip in surface in n type semiconductor layer 15 accounts for total current ratio and got over
Greatly, so so that the average current density of device is bigger, and saturation is finally tended to.
Preferably, W2Not less than 20 μm；
Further, it is L to define the length of the second heavy doping source region 13 in a z-direction13, the second heavy doping body contact zone 14
Length in a z-direction is L14；L13L can be more than14, L13L can be less than14, L13L can also be equal to14；
In order to avoid conductivity modulation effect, L14And L13Value should meet：L13-L14≦50μm。
Fig. 7 gives an a kind of pressure-resistant 620V based on double-deck RESURF Technology designs as shown in Fig. 3 of the present invention
pLDMOS.As can be seen from Figure 7：In the case of not optimized, as source-drain voltage during break-over of device raises, the
Two P+The P of doped region 19 to the 2nd+Caused voltage difference gradually rises on the path of body contact zone 14.When device source-drain voltage is increased to
During about 1.5V, above-mentioned pressure drop causes 12 times N-types of the second gate dielectric layer (electronics) raceway groove to open, so that N-type in the resistance to nip in surface
A large amount of electronics in semiconductor layer 16 participate in conductive.Assuming that 620V LDMOS specified conduction voltage drop is in 5V or so, then now
The current capacity of device has matched in excellence or beauty " the silicon limit " of the nLDMOS based on double-deck RESURF technologies, even more much larger than double-deck even three
The pLDMOS of layer RESURF technologies " the silicon limit ".Due to the 2nd P+The P of body contact zone 14 and the first+P type island region domain between doped region 19
There is body bias effect in interior (i.e. p-type drain region 10), from the 2nd P+Doped region 19 is to the 2nd P+Body contact zone 14 and 10, p-type drain region shape
Into interface, the 2nd P+The P of body contact zone 14 and the 2nd+Electronic current between doped region 19 in region is by 0 gradually increase.And the
Two P+Body bias effect is not present in the p-type drain region 10 of the lower section of body contact zone 14, so the regional Electronic current density can reach maximum
And uniformly.Therefore, as can be seen from Figure 7：With W3Increase, the total average current density of device gradually increases, finally becomes
In saturation.
On the other hand, W in Fig. 7 the present embodiment2=28 μm.With W2Increase, the 2nd P+The P of doped region 19 to the 2nd+Body connects
The voltage difference touched on the path of area 14 will cause 12 times electron channels of the second gate dielectric layer to open under lower device source-drain voltage,
Now, device will obtain higher electric current under lower source-drain voltage.It is important to note that now device is still single
Polarity conductivity, the bipolar device rather than IGBT etc forms conductance modulation conduction, so the LDMOS of the present invention is greatly being carried
While high current ability, the turn-off time still as unipolar device, can turn off as quick as thought.
Embodiments of the invention are set forth above in association with accompanying drawing, but the invention is not limited in above-mentioned specific
Embodiment, above-mentioned embodiment is only schematical, rather than restricted.One of ordinary skill in the art exists
Under the enlightenment of the present invention, in the case of present inventive concept and scope of the claimed protection is not departed from, many shapes can be also made
Formula, these are belonged within the protection of the present invention.
Claims (7)
1. a kind of LDMOS device, its structure cell includes：Substrate, the second conduction type half positioned at the substrate top layer side
Conductor source substrate zone, positioned at the first conductive type semiconductor drain region of the substrate top layer opposite side, it is conductive positioned at described second
The resistance to nip in surface of substrate surface between type semiconductor source substrate zone and the first conductive type semiconductor drain region；Described second leads
There is separate the second conduction type heavy doping body contact zone one and the first conductive-type in the substrate zone of electric type semiconductor source
Type heavy doping source region one；Device surface and the second conduction type heavy doping body contact zone one and the first conduction type heavy doping source region
One contact is source metal, the first conduction type heavy doping source region one, part the second conductive type semiconductor source substrate zone and
The upper surface of the resistance to nip of part surface has the first gate dielectric layer, and the upper surface of first gate dielectric layer has first grid；
The second conductive type semiconductor source substrate zone, the second conduction type heavy doping body contact zone one, the first conduction type are heavily doped
Miscellaneous source region, source metal, the first gate dielectric layer and first grid form the first active area, the resistance to nip phase of the first active area and surface
The first conduction type MOSFET is formed close to side；It is characterized in that：
The resistance to nip in surface is formed by the first conductive type semiconductor layer and second conductive type semiconductor layer, and described second leads
Electric type semiconductor layer segment surrounds the upper surface that the first conductive type semiconductor layer is arranged at substrate, and the first conduction type is partly led
Body layer is set close to the second conductive type semiconductor source substrate zone, and two layers of semiconductor layer is led with described second in the resistance to nip in surface
Electric type semiconductor source substrate zone contacts, second conductive type semiconductor layer and the first conductive type semiconductor in the resistance to nip in surface
Drain contact, and the first conductive type semiconductor not with the first conductive type semiconductor drain contact；First conduction type is partly led
Body floor has the first conduction type heavily-doped semiconductor area one close to the one end in the first conductive type semiconductor drain region, and described first
The upper surface of conduction type heavily-doped semiconductor area one has the first floating electrode；
There is the second separate conduction type heavy doping source region two and first in the first conductive type semiconductor drain region
Conduction type heavy doping body contact zone two；Device surface and the second conduction type heavy doping source region two and the first conduction type are heavily doped
What miscellaneous body contact zone two contacted is drain metal, also has the first conduction type weight in the first conductive type semiconductor drain region
Doped semiconductor area two, the first conduction type heavily-doped semiconductor area upper surface have the second floating electrode, and described first
It is not present connect the two between conduction type heavily-doped semiconductor area two and the first conduction type heavy doping body contact zone two
First conduction type heavily-doped semiconductor region, the second conduction type heavy doping source region two, the conductive type semiconductor of part first
Drain region and the upper surface of the resistance to nip of part surface have the second gate dielectric layer, and the upper surface of second gate dielectric layer has second
Grid, the second grid are connected with the first floating electrode and the second floating electrode respectively；First conduction type is partly led
Body drain area, the second conduction type heavy doping source region two, the first conduction type heavy doping body contact zone two, the first conduction type are heavily doped
Miscellaneous semiconductor region two, drain metal, the second gate dielectric layer, second grid and the second floating electrode the second active area of formation, second
Active area mutually forms the second conduction type MOSFET with the resistance to nip in surface close to side.
2. a kind of LDMOS device according to claim 1, it is characterised in that the resistance to nip in surface also includes by part
The second conduction type top layer being enclosed in first conductive type semiconductor layer, the upper table of the second conduction type top layer
Face overlaps with device upper surface.
A kind of 3. LDMOS device according to claim 1 or 2, it is characterised in that the second conduction type heavy-doped source
The conduction type heavy doping body contact zone two of area two and first is set up in parallel, and defines the second conduction type heavy doping source region two and first
The longitudinal length of conduction type heavy doping body contact zone two is respectively L13And L14, then the two meet：L13-L14≦50μm。
A kind of 4. LDMOS device according to claim 3, it is characterised in that the substrate be the first conduction type or
Semi-conducting material is lightly doped in second conduction type, and the semi-conducting material is body silicon, gallium nitride or carborundum.
5. a kind of LDMOS device according to claim 3, it is characterised in that the substrate is SOI substrate, the SOI linings
Bottom includes semiconductor layer and the dielectric layer disposed thereon of the first conduction type or the second conduction type.
6. a kind of LDMOS device according to claim 4 or 5, it is characterised in that the first conduction type is p-type, and second leads
Electric type is N-type.
7. a kind of LDMOS device according to claim 4 or 5, it is characterised in that the first conduction type is N-type, and second leads
Electric type is p-type.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110400840A (en) * | 2019-08-06 | 2019-11-01 | 电子科技大学 | A kind of RC-LIGBT device inhibiting voltage inflection phenomenon |
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| CN103441147A (en) * | 2013-08-09 | 2013-12-11 | 电子科技大学 | Lateral direction SOI power semiconductor device |
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| JP2011129701A (en) * | 2009-12-17 | 2011-06-30 | Asahi Kasei Toko Power Device Corp | Mos transistor |
| US20120104492A1 (en) * | 2010-10-29 | 2012-05-03 | Macronix International Co., Ltd. | Low on-resistance resurf mos transistor |
| US9076671B2 (en) * | 2011-08-04 | 2015-07-07 | Texas Instruments Incorporated | Power integrated circuit including series-connected source substrate and drain substrate power mosfets |
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