CN107359191B - A kind of super junction LDMOS device - Google Patents
A kind of super junction LDMOS device Download PDFInfo
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- CN107359191B CN107359191B CN201710630457.4A CN201710630457A CN107359191B CN 107359191 B CN107359191 B CN 107359191B CN 201710630457 A CN201710630457 A CN 201710630457A CN 107359191 B CN107359191 B CN 107359191B
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The present invention provides a kind of super junction LDMOS device, belongs to power device technology field.The structure cell of super junction LDMOS device of the present invention includes: substrate, the resistance to pressure area in superjunction surface positioned at first active area at substrate both ends and the second active area and between two active areas；First active area mutually depends on the MOSFET of nearside the first conduction type of formation with the resistance to pressure area in surface, and second active area mutually depends on the MOSFET of nearside the second conduction type of formation with the resistance to pressure area in surface；The present invention is realized in the case where not increasing control signal additionally, after a kind of type of carrier channel unlatching is conductive, can realize that another type of carrier participates in conductive in the resistance to pressure area in superjunction surface automatically, and do not form conductivity modulation effect.So the present invention ensure that rapidly switching off for unipolar device, and the super junction LDMOS that the present invention can integrate two kinds of different conduction-types under same technique but current capacity is close while significantly increasing current capacity.
Description
Technical field
The invention belongs to power semiconductor technologies fields, and in particular to a kind of high pressure transverse direction super-junction semiconductor device.
Background technique
The miniaturization of power electronic system, it is integrated be power semiconductor an important research direction.Intelligent function
Rate integrated circuit (Smart Power Integrated Circuit, SPIC) or high voltage integrated circuit (High Voltage
Integrated Circuit, HVIC) low-voltage circuits such as protection, control, detection, driving and high voltage power device are integrated in together
On one chip, system bulk is not only reduced in this way, improves system reliability.Meanwhile in the workplace of upper frequency,
Due to the reduction of system lead-in inductance, the requirement to buffering and protecting circuit can be significantly reduced.
Lateral double diffusion metal oxide field effect transistor (Lateral Double-diffused Metal Oxide
Field Effect Transistor, LDMOS) be SPIC or HVIC key technology.However since high pressure resistant lateral device is necessary
The requirement for meeting its breakdown voltage there are the drift region of certain lateral dimension (resistance to pressure area), which results in the conductings of the ratio of device
Resistance (Ron,sp) larger.Compared with the vertical nMOSFET of identical voltage and current grade, the resistance of LDMOS often compares vertical nMOSFET
It is much larger.So the key for designing lateral power be that and how to optimize breakdown voltage (Breakdown Voltage:
BV) and than conducting resistance Ron,spThe compromise of the two, so alleviate high-voltage LDMOS breakdown voltage and than contradiction between conducting resistance
Relationship.
Superjunction Withstand voltage layer is first in the patent of Coe " High voltage semiconductor devices " (" high pressure half
Conductor device ") and Chen patent " Semiconductor power devices with alternating
Conductivity type high-voltage breakdown regions " (" high-voltage breakdown with alternating conductivity type
The semiconductor power device in region ") in proposed respectively, its feature is to replace using alternate N-type and P-type semiconductor area
The originally N-type or P-type semiconductor of drift region single type.Here alternately arranged N-type and P-type semiconductor area are known as superjunction column.
Pass through the dopant dose for mutually exhausting compensation optimizing drift region field distribution and improving N-type and p type island region between superjunction column, energy
It enough improves the breakdown voltage of device and reduces the R of deviceon,sp.Superjunction structure of voltage-sustaining layer takes the lead in being applied to vertical nMOSFET skill
In art.Later, article " SJ/RESURF LDMOST " (" superjunction high pressure that researcher Nassif-Khalil et al. was delivered
LDMOS ") in propose device architecture as shown in Figure 1, this article, which is proposed, to be applied to LDMOS for the principle of superjunction Withstand voltage layer and (claims
It is super junction LDMOS or Super Junction-LDMOS or SJ-LDMOS) to obtain low Ron,sp。
Although SJ-LDMOS can optimize BV and R to a certain extenton,spTradeoff, but for p-type SJ-LDMOS
(SJ-pLDMOS) but rarely has research.This phenomenon Producing reason, in addition to due to its principle and N-shaped SJ-LDMOS (SJ-
It is nLDMOS) similar, it is often more important that: since SJ-pLDMOS utilizes hole conduction, current capacity is very weak, only SJ-nLDMOS
1/3 or so, so its high-voltage applications is largely limited.
Due to 3 times bigger than p-type LDMOS of the current capacity of N-shaped LDMOS or so, currently, the power output of high pressure applications
Grade generallys use two as shown in Figure 2 concatenated nLDMOS and constitutes totem output.But such circuit usually requires additionally
Auxiliary circuit be just able to achieve function, auxiliary circuit include high voltage level displacement (M1, R1, Cd and drive module are constituted) and
The modules such as high voltage level bootstrapping (low-tension supply VCC, Db and Cb are constituted).These circuit modules greatly increase system bulk
And complexity, and system power dissipation with higher.To solve the above-mentioned problems, researcher M.Nakano et al. is in article
" Full-complementary high-voltage driver ICs for flat display panels " (" plate is aobvious
Show the complete complementary high-voltage driving circuit of device ") and W.Sun et al. in article " High-voltage power IC
technology with nVDMOS,RESURF pLDMOS,and novel level-shift circuit for PDP
Scan-driver IC " (" high-voltage power integrated circuit technology and one kind based on nVDMOS and RESURF pLDMOS are used for
The novel level shift circuit of PDP scanner driver integrated circuit ") propose a kind of high pressure of full complementation as shown in Figure 3
Shift circuit and CMOS export structure.The high voltage level displaced portion of the structure uses high side for the high pressure p-type LDMOS of thick grid oxygen
(referred to as: Field PMOS or FPMOS), downside use conventional high-pressure nLDMOS.The output stage of the structure by high side thick grid
The FPMOS of oxygen and the nLDMOS of downside constitute CMOS power output.
Although the structure solves the problems, such as to need high voltage level bootstrapping and larger system power dissipation in traditional structure,
Due to introducing multiple FPMOS using hole conduction, current capacity very little, so chip area is difficult to decrease.And it is high
The mismatch of cross-sectional area of side FPMOS and downside nLDMOS can also make high and low side device output impedance mismatch.Due to FPMOS electric current
Ability is too small, which also limits the structure higher voltage grade application.Document disclosed in M.Denison et al.
《Investigation of a Dual Channel N/P-LDMOS and Application to LDO Linear
Voltage Regulation " it proposes in (" double channel N/P-LDMOS is in the application study in LDO linear voltage regulators ")
SJ-LDMOS a kind of while using P column and N column conduction, but the SJ-LDMOS needs two independent gate signals to P-channel
It is controlled with N-channel, and the voltage between two control signals floats zero to operating voltage, this needs additional circuit
Module realizes control.This will greatly increase circuit design difficulty and reduce system reliability, while also result in the device
Part is only practically applicable to this kind of low pressure applications occasion of LDO.
Summary of the invention
Technical problem to be solved by the present invention lies in: a kind of existing manufacture craft of compatibility is provided and device can be significantly increased
The novel high-pressure super junction LDMOS device of part current capacity.
In order to solve the above technical problem, the present invention provides following technical solutions:
A kind of super junction LDMOS device, structure cell include: substrate, the second conduction positioned at substrate top layer side
Type semiconductor source substrate zone, positioned at the substrate top layer other side the first conductive type semiconductor drain region, be located at described the
The resistance to pressure area in superjunction surface of substrate surface between two conductive type semiconductor source substrate zones and the first conductive type semiconductor drain region,
The resistance to pressure area in superjunction surface, which has, is parallel to the first conductiving type semiconductor area that device transverse direction alternates setting
With the second conductiving type semiconductor area, there is mutually independent second conduction type in the substrate zone of second conduction type source
Heavy doping body contact zone one and the first conduction type heavy doping source region one；Device surface is contacted with the second conduction type heavy doping body
What area one and the first conduction type heavy doping source region one contacted is source metal, the first conduction type heavy doping source region one, part
The upper surface of the resistance to pressure area of second conductive type semiconductor source substrate zone and part superjunction surface has the first gate dielectric layer, and described the
The upper surface of one gate dielectric layer has first grid；Second conductive type semiconductor source substrate zone, the second conduction type weight
Adulterate body contact zone one, the first conduction type heavy doping source region one, source metal, the first gate dielectric layer and first grid form the
One active area, the first active area and the resistance to pressure area in superjunction surface mutually lean on nearside to form the first conduction type MOSFET；It is characterized by:
There is mutually independent second conduction type heavy doping source region, two He in first conductive type semiconductor drain region
First conduction type heavy doping body contact zone two；Device surface and the second conduction type heavy doping source region two and the first conduction type
What heavy doping body contact zone two contacted is drain metal, also there is heavy doping partly to lead in first conductive type semiconductor drain region
Body area, the heavily-doped semiconductor area be the first conductive type semiconductor area or the second conductive type semiconductor area, it is described heavy
Doped semiconductor area upper surface has floating electrode, the heavily-doped semiconductor area and the first conduction type heavy doping body contact zone
There is no the first conduction type heavily-doped semiconductor region for being connected to the two, the second conduction type heavy doping source regions between two
Two, the upper surface of the resistance to pressure area in the first conductivity type drain region of part and part superjunction surface have the second gate dielectric layer, described second
The upper surface of gate dielectric layer has second grid, and the second grid is connected with the floating electrode；First conductive-type
Type semiconductor drain region, the second conduction type heavy doping source region two, the first conduction type heavy doping body contact zone two, heavy doping are partly led
Body area, drain metal, the second gate dielectric layer, second grid and floating electrode form the second active area, the second active area and superjunction
The resistance to pressure area in surface mutually leans on nearside to form the second conduction type MOSFET.
Further, the first conduction type is p-type, the second conduction type is N-type.
Further, the first conduction type is N-type, the second conduction type is p-type.
Further, the second conduction type heavy doping source region two and the first conduction type heavy doping in drain region of the present invention
Body contact zone two is set side by side, and defines the second conduction type heavy doping source region two and the first conduction type heavy doping body contact zone two
Longitudinal length be sequentially L19And L20, then the two meets: L19-L20≦50μm。
Further, substrate is that semiconductor material is lightly doped in p-type or N-type in the present invention, usually body silicon, nitridation
Gallium or silicon carbide.
Further, substrate is SOI substrate in the present invention, the SOI substrate includes that conduction type is p-type or N-type
Semiconductor layer and dielectric layer disposed thereon.
Further, also having substrate-assisted depletion layer in the present invention between the resistance to pressure area of substrate and superjunction surface.
Beneficial effects of the present invention are as follows:
Two kinds of conduction type carriers can be integrated the invention proposes one kind while majority carrier being used as respectively to participate in leading
The SJ-LDMOS device of electricity.By the way that two active areas are formed on the substrate, two active areas and the resistance to pressure area in superjunction surface are mutually close
The grid that side is respectively formed two conduction types opposite MOSFET, one of MOSFET is connected with floating electrode, and floating
Work as one kind there is no the heavily doped region for being connected to the two between doped region and heavy doping body contact zone in the MOSFET under electrode
After conduction type carrier channels open conduction, a kind of carrier of conduction type of this in the resistance to pressure area in superjunction surface is leaked to reach
Pole need to form voltage drop by distributed resistance can realize another conduction type without increasing additional control signal automatically
The unlatching of carrier channels.The realization of this technological means of the invention significantly enhances the current capacity of device.In addition, of the invention
By rationally designing device architecture.It can be avoided to form conductivity modulation effect, and then guarantee the quick pass as unipolar device
It is disconnected.Manufacture craft of the present invention is compatible with existing manufacture craft, therefore is not necessarily in extensive manufacture to existing for manufacturer
Having technique to carry out large-scale redevelopment can make.The present invention can be under same technique on chip similar in integrated current ability
SJ-nLDMOS and SJ-pLDMOS makes relevant power integrated circuit, and then improves the power collection by element manufacturing of the present invention
At the overall performance of circuit.
Detailed description of the invention
Fig. 1 tradition SJ-LDMOS structural schematic diagram.
Fig. 2 conventional high-tension level displacement circuit and totem power output structure.
Fig. 3 complementation high voltage level shift circuit and CMOS power output structure.
Fig. 4 embodiment of the present invention proposes the structural schematic diagram for the SJ-LDMOS device being produced on body silicon substrate；
Fig. 5 embodiment of the present invention proposes to be produced on body silicon substrate and the SJ-LDMOS with substrate-assisted depletion layer
The structural schematic diagram of device；
Fig. 6 embodiment of the present invention proposes to make the structural schematic diagram of SJ-LDMOS device on soi substrates；
Fig. 7 embodiment of the present invention proposes to make on soi substrates and has the SJ-LDMOS of substrate-assisted depletion layer
The structural schematic diagram of device；
Fig. 8 is that the embodiment of the present invention passes of the invention design under gained pressure resistance 600V SJ-pLDMOS and identical structural parameters
The comparison diagram that the current capacity of system SJ-pLDMOS and tradition SJ-nLDMOS is emulated；
In figure, 1 is substrate, and 2 be N-type source substrate zone, and 3 be the first N+Body contact zone, 4 be the first P+Source region, 5 be the first grid
Dielectric layer, 6 be first grid, and 7 be source metal, and 8 be P-type semiconductor area, and 9 be N-type semiconductor area, and 10 be p-type drain region, and 11 are
Drain metal, 12 be substrate-assisted depletion layer, and 13 be dielectric layer, and 14 be substrate layer, and 15 be the resistance to pressure area in superjunction surface, and 16 be second
Gate dielectric layer, 17 be second grid, and 18 be floating electrode, and 19 be the 2nd N+Source region, 20 be the 2nd P+Body contact zone, 21 be heavily doped
Miscellaneous semiconductor region.
Specific embodiment
With reference to the accompanying drawings to invention is more fully described, in Figure of description, identical label indicates phase
Same or similar component or element, main idea of the present invention are to provide a kind of novel high pressure SJ-LDMOS, SJ- of the present invention
LDMOS device can be N-type SJ-LDMOS (SJ-nLDMOS), be also possible to p-type SJ-LDMOS (SJ-pLDMOS), and the present invention is real
It applies example to be specifically illustrated with SJ-pLDMOS, correspondingly, SJ-nLDMOS principle is similar.
Embodiment 1:
Fig. 4 shows the structure cell for the SJ-pLDMOS device that the present invention is produced on body silicon substrate, comprising: p-type
Substrate 1, the N-type source substrate zone 2 positioned at the 1 top layer side of P type substrate, the p-type positioned at the 1 top layer other side of P type substrate
Drain region 10, the resistance to pressure area 15 in the superjunction surface on 1 surface of substrate between N-type source substrate zone 2 and p-type drain region 10, in which: P
The material of type substrate 1 is also possible to N-type semiconductor material, is not limited to P-type semiconductor disclosed in the present embodiment, the superjunction
The resistance to pressure area 15 in surface, which has, is parallel to P-type semiconductor area 8 and N-type semiconductor area 9 that device transverse direction alternates setting, institute
Stating has mutually independent first N in N-type source substrate zone 2+Body contact zone 3 and the first P+Source region 4；Device surface and the first N+Body
Contact zone 3 and the first P+That source region 4 contacts is source metal 7, the first N+Body contact zone 3, part N-type source substrate zone 2 and part are super
The upper surface for tying the resistance to pressure area 15 in surface has the first gate dielectric layer 5, and the upper surface of first gate dielectric layer 5 has first grid
6；N-type source substrate zone 2, the first N+Body contact zone 3, the first P+Source region 4, source metal 7, the first gate dielectric layer 5 and the first grid
Pole 6 forms the first active area, and the first active area mutually forms the MOSFET of P-type channel with the resistance to pressure area 15 in superjunction surface by nearside；Its
It is characterized in that:
There is mutually independent 2nd N in the p-type drain region 10+Source region 19 and the 2nd P+Body contact zone 20；Device surface with
2nd N+Source region 19 and the 2nd P+What body contact zone 20 contacted is drain metal 11, also has heavy doping half in the p-type drain region 10
Conductor region 21, the conduction type of the heavily-doped semiconductor 21 can be p-type, or N-type, so the present invention does not do this
It limits, 21 upper surface of heavily-doped semiconductor area has floating electrode 18, the heavily-doped semiconductor area 21 and the 2nd P+Body
There is no the p-type heavily-doped semiconductor region for being connected to the two, the 2nd N between contact zone 20+Source region 19, part p-type drain region 10
And the upper surface of the resistance to pressure area 15 in part superjunction surface has the second gate dielectric layer 16, the upper surface of second gate dielectric layer 16 has
There is second grid 17, the grid 17 is connected with the floating electrode 18；The p-type drain region 10, the 2nd N+ source region 19, second
P+Body contact zone 20, P+Semiconductor region 21, drain metal 11, the second gate dielectric layer 16, second grid 17 and the formation of floating electrode 18
Second active area, the second active area and the resistance to pressure area 15 in superjunction surface mutually form the MOSFET of N-type channel by nearside.
The floating electrode 18 is connected with second grid, and therefore, LDMOS device proposed by the present invention is still three ends
Device.
Embodiment 2:
Fig. 5 shows the structure cell for the SJ-pLDMOS device that the present invention is produced on body silicon substrate, this implementation removes
Also have except substrate-assisted depletion layer 12 between the resistance to pressure area 15 of P type substrate 1 and superjunction surface, remaining structure with implementation
Example 1 is identical.
Specifically, when substrate is that semiconductor is lightly doped in p-type, substrate between the substrate and the resistance to pressure area in superjunction surface
The conduction type of assisted depletion layer is N-type；N-type substrate assisted depletion layer the direction x as shown in the figure be by Uniform Doped, it is linear gradually
Varying doping or the N-type semiconductor of subsection gradual doping are formed, and doping concentration is gradually dropped from N-type source substrate zone to p-type drain region
It is low.
Specifically, when substrate is that semiconductor is lightly doped in N-type, substrate between the substrate and the resistance to pressure area in superjunction surface
The conduction type of assisted depletion layer is p-type；P type substrate assisted depletion layer is adulterated by Uniform Doped, linear gradient or is segmented gradually
The P-type semiconductor of varying doping is formed, and doping concentration gradually rises from N-type source substrate zone to p-type drain region.
Similarly, according to general knowledge known in this field: for SJ-nLDMOS, when substrate is that semiconductor is lightly doped in p-type
When, the conduction type of substrate-assisted depletion layer is N-type, N-type substrate auxiliary between the substrate and the resistance to pressure area in superjunction surface
Depletion layer is formed by the N-type semiconductor of Uniform Doped, linear gradient doping or subsection gradual doping, and doping concentration is from p-type
Source substrate zone to N-type drain region gradually rises；When substrate is that semiconductor is lightly doped in N-type, the substrate and the superjunction surface are resistance to
The conduction type of substrate-assisted depletion layer is p-type between pressure area；N-type substrate assisted depletion layer is mixed by Uniform Doped, linear gradient
The P-type semiconductor of miscellaneous or subsection gradual doping is formed, and doping concentration is gradually decreased from p-type source substrate zone to N-type drain region.
Embodiment 3:
Fig. 6 shows the specific embodiment of the pLDMOS device cellular of present invention production on soi substrates, this implementation
With other than P type substrate 1 is replaced with SOI substrate, remaining structure is same as Example 1；Wherein, SOI substrate includes lining
Bottom 14 and the insulating medium layer 13 on the substrate layer 14, the doping type of the substrate layer 14 can be p-type,
It can be N-type, the present embodiment selects P type substrate layer.
Embodiment 4:
Fig. 7 shows the specific embodiment of the pLDMOS device cellular of present invention production on soi substrates, this implementation
With other than P type substrate 1 is replaced with SOI substrate, remaining structure is same as Example 2；Wherein, SOI substrate includes lining
Bottom 14 and the insulating medium layer 13 on the substrate layer 14, the doping type of the substrate layer 14 can be p-type,
It can be N-type, the present embodiment selects N-type substrate layer.
Embodiment 5:
The present embodiment in addition between the resistance to pressure area of SOI substrate and superjunction surface also have substrate-assisted depletion layer other than,
Remaining structure is same as Example 3.
Specifically, if the SOI substrate connects maximum potential, substrate is assisted between substrate and the resistance to pressure area in superjunction surface
The conduction type of depletion layer is p-type, and P type substrate assisted depletion layer is mixed by Uniform Doped, linear gradient doping or subsection gradual
Miscellaneous p-type semiconductor material is formed, and doping concentration gradually rises from N-type source substrate zone to p-type drain region；If the SOI substrate
Potential minimum is connect, then the conduction type of substrate-assisted depletion layer is N-type between substrate and the resistance to pressure area in superjunction surface；N-type lining
Bottom assisted depletion layer is formed by the N-type semiconductor material of Uniform Doped, linear gradient doping or subsection gradual doping, is adulterated
Concentration is gradually decreased from N-type source substrate zone to p-type drain region.
Similarly, according to general knowledge known in this field: for SJ-nLDMOS, if the SOI substrate connects highest electricity
Position, then the conduction type of substrate-assisted depletion layer is p-type, P type substrate auxiliary consumption between substrate and the resistance to pressure area in superjunction surface
Layer is formed by the p-type semiconductor material of Uniform Doped, linear gradient doping or subsection gradual doping to the greatest extent, and doping concentration is from P
Type source substrate zone to N-type drain region gradually decreases；If the SOI substrate connects potential minimum, substrate and superjunction surface pressure resistance
The conduction type of substrate-assisted depletion floor is N-type between area；N-type substrate assisted depletion layer is adulterated by Uniform Doped, linear gradient
Or the N-type semiconductor material of subsection gradual doping is formed, doping concentration gradually rises from p-type source substrate zone to N-type drain region.
Based on embodiment disclosed above, the principle of the invention is described in detail with reference to the accompanying drawings of the specification:
Such as the specific embodiment that provides of the present invention, when the first conduction type is p-type, and the second conduction type is N-type: this
The resistance to pressure area of the first active area and superjunction surface constitutes p-type MOSFET in invention, uses N-type semiconductor material in first active area
Material forms source substrate zone, and the source substrate zone also has independent P+Type area and N+Type area, the P+Type area and N+Type area is adjacent simultaneously
And the source electrode for constituting the MOSFET of the first conduction type, the part P are contacted with metallic conductor+Type area, part N-type source substrate
There is dielectric layer on the resistance to pressure area in area and part superjunction surface, there is metallic conductor to form gate electrode for the dielectric layer upper surface, this
When the second active area be p-type MOSFET drain terminal；Source substrate zone is formed using p-type semiconductor material in second active area,
The source substrate zone equally has independent another P+Type area and another N+Type area, the P+Type area and N+Type Qu Xianglin and with
Metallic conductor contact constitutes the source electrode of N-type MOSFET, the part P+Type area, part p-type drain region and the pressure resistance of part superjunction surface
Equally there is another transfer floor, there is metallic conductor to form gate electrode for another transfer layer upper surface, and first has at this time in area
Source region is the drain terminal of N-type MOSFET；
When the first conduction type is p-type, and the second conduction type is N-type, from the point of view of Figure of description, the present invention is used
2nd P+Body contact zone 20 is used as drain electrode contact area, and has the heavily-doped semiconductor area 21 for separating setting therewith, due to
Therebetween there is no the heavily-doped semiconductor regions that are connected to the two, in other words, P-type semiconductor region between the two (
It is exactly p-type drain region 10) there are biggish distributed resistances.Thus, after p-type MOSFET is opened under applied voltage, superjunction surface
P-type carrier (hole) has to flow through heavy doping and partly leads if wanting to reach drain electrode in P-type semiconductor area 8 in resistance to pressure area 15
Body area 21 and the 2nd P+The distributed resistance of P-type semiconductor region between body contact zone 20, during this on distributed resistance
Electric current makes heavily-doped semiconductor area 21 relative to the 2nd P+The voltage difference that body contact zone 20 generates is positive value；Again due to heavy doping
Floating electrode 18 on semiconductor region 21 is connected with the second gate electrode 17, and above-mentioned voltage difference makes the N under the second gate dielectric layer 16
Type channel is opened, and is formed by N-type MOSFET with the resistance to pressure area 15 in superjunction surface to realize and automatically turn on the second active area, into
And make N-type carrier (electronics) in the resistance to pressure area 15 in superjunction surface conductive as majority carrier participation.
Similarly, when the first conduction type is N-type, and the second conduction type is p-type, the present invention uses the 2nd N+Body contact zone
As drain electrode contact area, and there is the heavily-doped semiconductor area for separating setting therewith, due to being not present two therebetween
Person connection heavily-doped semiconductor region, in other words, N-type semiconductor region (namely N-type drain region) between the two exist compared with
Big distributed resistance, thus, after N-type MOSFET is opened under applied voltage, N-type in n type semiconductor layer in the resistance to pressure area in surface
Carrier (electronics) has to flow through heavily-doped semiconductor area and the 2nd N if wanting to reach drain electrode+N-type between body contact zone
The distributed resistance of the semiconductor regions in drain region, the electric current during this on distributed resistance make heavily-doped semiconductor area relative to
N+The voltage difference that body contact zone generates is negative value, and due to the floating electrode and the second gate electrode phase in heavily-doped semiconductor area
Even, above-mentioned voltage difference opens the P-type channel under the second gate dielectric layer, automatically turns on the second active area to realize and surpasses
The knot resistance to pressure area in surface is formed by p-type MOSFET, so that p-type carrier (hole) is as most in the resistance to pressure area in superjunction surface
Carrier participates in conductive.
From the point of view of Figure of description, in order to rationally design each semiconductor regions and electrode in point on structure cell surface
Cloth, according to coordinate system in figure, the 2nd P in the present embodiment+Body contact zone 20 and heavily-doped semiconductor area 21 be arranged at as
The direction z shown in scheming defines the 2nd P+The distance between body contact zone 20 and heavily-doped semiconductor area 21 are W2, define the 2nd P+Body
The length of contact zone 20 in a z-direction is W3, due to the 2nd P+P-type leakage between body contact zone 20 and heavily-doped semiconductor area 21
Area 10 is there are body bias effect, and the 2nd P+Body bias effect is not present in the p-type drain region 10 of 20 lower section of body contact zone, so, the 2nd P+Body
Length of the contact zone 20 in the direction z is bigger, participates in conductive electronic current in the resistance to pressure area 15 in superjunction surface in N-type semiconductor area 9
It accounts for that total current ratio is bigger, so making the average current density of device bigger, and finally tends to be saturated.
According to test: when device is SJ-nLDMOS, the current capacity of device architecture of the present invention compares traditional devices
Improve one third or so.When device is SJ-pLDMOS, the current capacity of device architecture of the present invention is improved compared to traditional devices
Three times or so.
Preferably, W2Not less than 20 μm；
Further, defining the length of the 2nd N+ source region 19 in a z-direction is L19, the 2nd P+Body contact zone 20 is in the direction z
On length be L20；L19L can be greater than20, L19L can be less than20, L19L can also be equal to20；
In order to avoid conductivity modulation effect, L19And L20Value should meet: L19-L20≦50μm。
Fig. 8 give the pressure resistance 600V designed according to the present invention SJ-pLDMOS and identical parameters under traditional devices
Simulation comparison result figure.As can be seen from Figure 8: even if source and drain in the case where not optimized, when with break-over of device
Voltage increases, 21 to the 2nd P of heavily-doped semiconductor area+Voltage difference on 20 path of body contact zone gradually rises.When device source and drain
When voltage is increased to about 2.3V, the voltage difference on above-mentioned path opens N-type electron channel, so that superjunction surface is pressure-resistant
A large amount of electronics participate in conductive in N-type semiconductor area 9 in area 15.Assuming that the specified conduction voltage drop of 600V LDMOS is in 5V or so,
So the current capacity of device of the present invention has been greater than SJ-nLDMOS at this time, even more much larger than the SJ-pLDMOS under same process.
Due to the 2nd P+There is part N-type carrier (electronics) to deposit in p-type drain region 10 between body contact zone 20 and heavily-doped semiconductor area 21
In body bias effect, from heavily-doped semiconductor area 21 to the 2nd P+Body contact zone 20 and the formed interface in p-type drain region 10, the 2nd P+
Electronic current between body contact zone 20 and heavily-doped semiconductor area 21 in region is gradually increased by 0.And the 2nd P+Body contact zone
Body bias effect is not present in 20 lower sections p-type drain region 10, so the electron current density in the region can reach maximum and uniform, because
This, as can be seen from Figure 8: with W3Increase, the total average current density of device is gradually increased, finally tends to be saturated.
On the other hand, the W when embodiment of the present invention emulates2It is 28 μm, and with W2Increase, heavily-doped semiconductor area 21 to
2nd P+Voltage difference on 20 path of body contact zone will make under the second gate dielectric layer 16 under lower device source-drain voltage
Electron channel is opened, at this point, device will obtain higher electric current under lower source-drain voltage, is anticipated as indicated by the dotted lines in figure 8.
It is important to note that device is still unipolarity conduction at this time, the bipolar device rather than IGBT etc forms conductance
Modulation is conductive, so LDMOS of the invention is while being greatly improved current capacity, the turn-off time still with unipolar device one
Sample can turn off as quick as thought.
The embodiment of the present invention is expounded in conjunction with attached drawing above, but the invention is not limited to above-mentioned specific
Embodiment, above-mentioned specific embodiment is only schematical, rather than restrictive.Those skilled in the art exist
Under enlightenment of the invention, without breaking away from the scope protected by the purposes and claims of the present invention, many shapes can be also made
Formula, all of these belong to the protection of the present invention.
Claims (6)
1. a kind of super junction LDMOS device, structure cell includes: substrate, the second conductive-type positioned at substrate top layer side
Type semiconductor source substrate zone, positioned at the substrate top layer other side the first conductive type semiconductor drain region, be located at described second
The resistance to pressure area in superjunction surface of substrate surface, institute between conductive type semiconductor source substrate zone and the first conductive type semiconductor drain region
State the resistance to pressure area in superjunction surface have be parallel to device transverse direction alternate setting the first conductiving type semiconductor area and
Second conductiving type semiconductor area has in the substrate zone of second conductive type semiconductor source mutually independent second conductive
Type heavy doping body contact zone one and the first conduction type heavy doping source region one；Device surface and the second conduction type heavy doping body
Contact zone one and the contact of the first conduction type heavy doping source region one are source metals, the first conduction type heavy doping source region one,
The upper surface of the resistance to pressure area of part the second conductive type semiconductor source substrate zone and part superjunction surface has the first gate dielectric layer, institute
The upper surface for stating the first gate dielectric layer has first grid；Second conductive type semiconductor source substrate zone, the second conductive-type
Type heavy doping body contact zone one, the first conduction type heavy doping source region one, source metal, the first gate dielectric layer and first grid shape
At the first active area, the first active area mutually leans on nearside to form the first conduction type MOSFET with the resistance to pressure area in superjunction surface；Its feature
It is:
There is mutually independent second conduction type heavy doping source region two and first in first conductive type semiconductor drain region
Conduction type heavy doping body contact zone two；Device surface and the second conduction type heavy doping source region two and the first conduction type are heavily doped
What miscellaneous body contact zone two contacted is drain metal, also has heavily-doped semiconductor in first conductive type semiconductor drain region
Area, the heavily-doped semiconductor area be the first conductive type semiconductor area or the second conductive type semiconductor area, it is described heavily doped
Miscellaneous semiconductor region upper surface has floating electrode, the heavily-doped semiconductor area and the first conduction type heavy doping body contact zone two
Between there is no the first conduction type heavily-doped semiconductor region for being connected to the two, the second conduction type heavy doping source region two,
The upper surface of the resistance to pressure area in the first conductivity type drain region of part and part superjunction surface has the second gate dielectric layer, and the second gate is situated between
The upper surface of matter layer has second grid, and the second grid is connected with the floating electrode；First conduction type half
Conductor drain region, the second conduction type heavy doping source region two, the first conduction type heavy doping body contact zone two, heavily-doped semiconductor
Area, drain metal, the second gate dielectric layer, second grid and floating electrode form the second active area, the second active area and superjunction table
The resistance to pressure area in face mutually leans on nearside to form the second conduction type MOSFET.
2. a kind of super junction LDMOS device according to claim 1, which is characterized in that the second conduction type heavy doping
Source region two and the first conduction type heavy doping body contact zone two are set side by side；Define the second conduction type heavy doping source region two
Longitudinal length with the first conduction type heavy doping body contact zone two is sequentially L19And L20, then the two meets: L19-L20≦50μm。
3. a kind of super junction LDMOS device according to claim 1 or 2, which is characterized in that the first conduction type is p-type, the
Two conduction types are N-type.
4. a kind of super junction LDMOS device according to claim 1 or 2, which is characterized in that the first conduction type is N-type, the
Two conduction types are p-type.
5. a kind of super junction LDMOS device according to claim 1 or 2, which is characterized in that the substrate is p-type or N-type
Be lightly doped semiconductor material, the semiconductor material is body silicon, gallium nitride or silicon carbide.
6. a kind of super junction LDMOS device according to claim 1 or 2, which is characterized in that the substrate is SOI substrate, institute
State the semiconductor layer and dielectric layer disposed thereon that SOI substrate includes p-type or N-type.
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| CN104201206A (en) * | 2014-08-29 | 2014-12-10 | 电子科技大学 | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device |
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| CN104201206A (en) * | 2014-08-29 | 2014-12-10 | 电子科技大学 | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device |
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