CN107359191A - A kind of super junction LDMOS device - Google Patents
A kind of super junction LDMOS device Download PDFInfo
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- CN107359191A CN107359191A CN201710630457.4A CN201710630457A CN107359191A CN 107359191 A CN107359191 A CN 107359191A CN 201710630457 A CN201710630457 A CN 201710630457A CN 107359191 A CN107359191 A CN 107359191A
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Abstract
The present invention provides a kind of super junction LDMOS device, belongs to power device technology field.The structure cell of super junction LDMOS device of the present invention includes：Substrate, the resistance to nip in superjunction surface positioned at first active area at substrate both ends and the second active area and between two active areas；The first active area nip resistance to surface mutually forms the MOSFET of the first conduction type close to side, and the second active area nip resistance to surface mutually forms the MOSFET of the second conduction type close to side；The present invention is realized in the case where additionally not increasing control signal, after a kind of type of carrier raceway groove opens conduction, can realize that another type of carrier participates in conductive in the resistance to nip in superjunction surface automatically, and do not form conductivity modulation effect.So the present invention ensure that rapidly switching off for unipolar device, and the super junction LDMOS that the present invention can integrate two kinds of different conduction-types under same technique but current capacity is close while current capacity is significantly increased.
Description
Technical field
The invention belongs to power semiconductor technologies field, and in particular to a kind of high pressure transverse direction super-junction semiconductor device.
Background technology
The minimizing of power electronic system, it is integrated be power semiconductor an important research direction.Intelligent work(
Rate integrated circuit (Smart Power Integrated Circuit, SPIC) or high voltage integrated circuit (High Voltage
Integrated Circuit, HVIC) low-voltage circuits such as protection, control, detection, driving and high voltage power device are integrated in together
On one chip, system bulk is so not only reduced, improves system reliability.Meanwhile in the workplace of upper frequency,
Due to the reduction of system lead-in inductance, the requirement to buffering and protection circuit can be significantly reduced.
Lateral double diffusion metal oxide field-effect transistor (Lateral Double-diffused Metal Oxide
Field Effect Transistor, LDMOS) be SPIC or HVIC key technology.It is necessary yet with high pressure resistant horizontal device
In the presence of certain lateral dimension drift region (resistance to nip) to meet the requirement of its breakdown voltage, which results in device ratio conducting
Resistance (Ron,sp) larger.Compared with the vertical nMOSFET of identical voltage x current grade, LDMOS resistance often compares vertical nMOSFET
It is much larger.So the key for designing lateral power is that：How breakdown voltage (Breakdown Voltage is optimized：
BV) and than conducting resistance Ron,spThe compromise of the two, so alleviate high-voltage LDMOS breakdown voltage and than contradiction between conducting resistance
Relation.
Superjunction Withstand voltage layer is first in Coe patent《High voltage semiconductor devices》(《High pressure half
Conductor device》) and Chen patent《Semiconductor power devices with alternating
conductivity type high-voltage breakdown regions》(《High-voltage breakdown with alternating conductivity type
The semiconductor power device in region》) in proposed respectively, its feature is to replace using alternate N-type and P-type semiconductor area
The originally N-type or P-type semiconductor of drift region single type.Here the N-type and P-type semiconductor area being alternately arranged are referred to as superjunction post.
Pass through the dopant dose for mutually exhausting compensation optimizing drift region Electric Field Distribution and improving N-type and p type island region between superjunction post, energy
Enough improve the breakdown voltage of device and reduce the R of deviceon,sp.Superjunction structure of voltage-sustaining layer takes the lead in being applied to vertical nMOSFET skill
In art.Later, the article that researcher Nassif-Khalil et al. is delivered《SJ/RESURF LDMOST》(《Superjunction high pressure
LDMOS》) in propose device architecture as shown in Figure 1, this article, which proposes, to be applied to LDMOS by the principle of superjunction Withstand voltage layer and (claims
For super junction LDMOS or Super Junction-LDMOS or SJ-LDMOS) to obtain low Ron,sp。
Although SJ-LDMOS can optimize BV and R to a certain extenton,spTradeoff, but for p-type SJ-LDMOS
(SJ-pLDMOS) but rarely has research.This phenomenon Producing reason, except due to its principle and n-type SJ-LDMOS (SJ-
It is nLDMOS) similar, it is often more important that：Because SJ-pLDMOS utilizes hole conduction, its current capacity is very weak, only SJ-nLDMOS
1/3 or so, so its high-voltage applications is largely limited.
Due to 3 times bigger than p-type LDMOS or so of n-type LDMOS current capacity, at present, the power output of high pressure applications
The nLDMOS of level generally use two series connection as shown in Figure 2 forms totem output.But such circuit usually requires additionally
Auxiliary circuit could realize function, auxiliary circuit include high voltage level displacement (M1, R1, Cd and drive module are formed) and
The modules such as high voltage level bootstrapping (low-tension supply VCC, Db and Cb are formed).These circuit modules greatly increase system bulk
And complexity, and there is higher system power dissipation.In order to solve the above problems, researcher M.Nakano et al. is in article
《Full-complementary high-voltage driver ICs for flat display panels》(《Flat board shows
Show the complete complementary high-voltage driving circuit of device》) and W.Sun et al. in article《High-voltage power IC
technology with nVDMOS,RESURF pLDMOS,and novel level-shift circuit for PDP
scan-driver IC》(《High-voltage power integrated circuit technology and one kind based on nVDMOS and RESURF pLDMOS are used for
The new level shift circuit of PDP scanner driver integrated circuits》) propose a kind of complete complementary high pressure as shown in Figure 3
Shift circuit and CMOS export structures.The high voltage level displaced portion of the structure uses high pressure p-type LDMOS of the high side for thick grid oxygen
(it is referred to as：Field PMOS or FPMOS), downside uses conventional high-pressure nLDMOS.The output stage of the structure by high side thick grid
The FPMOS of oxygen and the nLDMOS of downside form CMOS power outputs.
Although the structure solves the problems, such as to need high voltage level bootstrapping and larger system power dissipation in traditional structure,
Due to introducing multiple FPMOS using hole conduction, its current capacity very little, so chip area is difficult to reduce.It is and high
Side FPMOS and downside nLDMOS mismatch of cross-sectional area can also cause high and low side device output impedance to mismatch.Due to FPMOS electric currents
Ability is too small, which also limits the structure higher voltage grade application.Document disclosed in M.Denison et al.
《Investigation of a Dual Channel N/P-LDMOS and Application to LDO Linear
Voltage Regulation》(《Application studies of the double channel N/P-LDMOS in LDO linear voltage regulators》) in propose
A kind of SJ-LDMOS of while utilization P posts and N posts conduction, but the SJ-LDMOS needs two independent gate signals to P-channel
It is controlled with N-channel, and the voltage between two control signals floats zero to operating voltage, and this needs extra circuit
Module realizes control.This will greatly increase circuit design difficulty and reduce system reliability, while also result in the device
Part is only practically applicable to this kind of low pressure applications occasions of LDO.
The content of the invention
The technical problems to be solved by the invention are：A kind of compatible existing manufacture craft is provided and device can be significantly increased
The novel high-pressure super junction LDMOS device of part current capacity.
In order to solve the above-mentioned technical problem, the present invention provides following technical scheme：
A kind of super junction LDMOS device, its structure cell include：Substrate, the second conduction positioned at the substrate top layer side
Type semiconductor source substrate zone, positioned at the first conductive type semiconductor drain region of the substrate top layer opposite side, positioned at described
The resistance to nip in superjunction surface of substrate surface between two conductive type semiconductor source substrate zones and the first conductive type semiconductor drain region,
The resistance to nip in superjunction surface has the first conductiving type semiconductor area that setting is alternateed parallel to device horizontal direction
With the second conductiving type semiconductor area, there is the second separate conduction type in the second conduction type source substrate zone
The conduction type heavy doping source region one of heavy doping body contact zone one and first；Device surface contacts with the second conduction type heavy doping body
What area one and first conduction type heavy doping source region one contacted is source metal, the first conduction type heavy doping source region one, part
The upper surface of the resistance to nip of second conductive type semiconductor source substrate zone and part superjunction surface has the first gate dielectric layer, and described
The upper surface of one gate dielectric layer has first grid；The second conductive type semiconductor source substrate zone, the second conduction type weight
Adulterate body contact zone one, the first conduction type heavy doping source region one, source metal, the first gate dielectric layer and first grid form the
One active area, the first active area and the resistance to nip in superjunction surface mutually form the first conduction type MOSFET close to side；It is characterized in that：
There is the separate He of the second conduction type heavy doping source region two in the first conductive type semiconductor drain region
First conduction type heavy doping body contact zone two；Device surface and the second conduction type heavy doping source region two and the first conduction type
What heavy doping body contact zone two contacted is drain metal, also there is heavy doping partly to lead in the first conductive type semiconductor drain region
Body area, the heavily-doped semiconductor area are the first conductive type semiconductor area or the second conductive type semiconductor area, described heavy
Doped semiconductor area upper surface has floating electrode, the heavily-doped semiconductor area and the first conduction type heavy doping body contact zone
It is not present the first conduction type heavily-doped semiconductor region of the two connection, the second conduction type heavy doping source region between two
2nd, the upper surface of the resistance to nip in the conductivity type drain region of part first and part superjunction surface has the second gate dielectric layer, and described second
The upper surface of gate dielectric layer has second grid, and the second grid is connected with the floating electrode；First conductive-type
Type semiconductor drain region, the second conduction type heavy doping source region two, the first conduction type heavy doping body contact zone two, heavy doping are partly led
Body area, drain metal, the second gate dielectric layer, second grid and floating electrode form the second active area, the second active area and superjunction
The resistance to nip in surface mutually forms the second conduction type MOSFET close to side.
It is further that the first conduction type is p-type, the second conduction type is N-type.
It is further that the first conduction type is N-type, the second conduction type is p-type.
It is further the second conduction type heavy doping source region two and the first conduction type heavy doping in drain region of the present invention
Body contact zone two is set up in parallel, and defines the second conduction type heavy doping source region two and the first conduction type heavy doping body contact zone two
Longitudinal length be sequentially L19And L20, then the two meet：L19-L20≦50μm。
It is further that substrate is that semi-conducting material is lightly doped in p-type or N-type in the present invention, usually body silicon, nitridation
Gallium or carborundum.
It is further that substrate is SOI substrate in the present invention, and it is p-type or N-type that the SOI substrate, which includes conduction type,
Semiconductor layer and dielectric layer disposed thereon.
It is further that also there is substrate-assisted depletion layer between the resistance to nip of substrate and superjunction surface in the present invention.
Beneficial effects of the present invention are as follows：
The present invention proposes one kind and can integrate two kinds of conduction type carriers while each participate in leading as majority carrier
The SJ-LDMOS devices of electricity.By forming two active areas on substrate, two active areas and the resistance to nip in superjunction surface are mutually close
The grid that side forms two conduction types opposite MOSFET, one of MOSFET respectively is connected with floating electrode, and floating
The heavily doped region for connecting the two is not present under electrode between doped region and heavy doping body contact zone in the MOSFET, works as one kind
After conduction type carrier channels open conduction, a kind of carrier of conduction type of this in the resistance to nip in superjunction surface leaks to reach
Pole need to pass through distributed resistance and form voltage drop, without increasing extra control signal, you can realize another conduction type automatically
The unlatching of carrier channels.The realization of this technological means of the invention significantly enhances the current capacity of device.It is in addition, of the invention
By rationally designing device architecture.Conductivity modulation effect can be avoided the formation of, and then ensures the quick pass as unipolar device
It is disconnected.Manufacture craft of the present invention is compatible with existing manufacture craft, therefore need not be to existing in extensive manufacture for manufacturer
Having technique to carry out large-scale redevelopment can make.The present invention can be under same technique on chip similar in integrated current ability
SJ-nLDMOS makes related power integrated circuit to SJ-pLDMOS, and then improves the power collection by element manufacturing of the present invention
Into the overall performance of circuit.
Brief description of the drawings
Fig. 1 tradition SJ-LDMOS structural representations.
Fig. 2 conventional high-tensions level displacement circuit and totem power output structure.
Fig. 3 complementations high voltage level shift circuit and CMOS power output structures.
Fig. 4 embodiment of the present invention proposes the structural representation for the SJ-LDMOS devices being produced on body silicon substrate；
Fig. 5 embodiment of the present invention proposes to be produced on body silicon substrate and the SJ-LDMOS with substrate-assisted depletion layer
The structural representation of device；
Fig. 6 embodiment of the present invention proposes to make the structural representation of SJ-LDMOS devices on soi substrates；
Fig. 7 embodiment of the present invention proposes to make on soi substrates and has the SJ-LDMOS of substrate-assisted depletion layer
The structural representation of device；
Fig. 8 is to be passed under pressure-resistant 600V SJ-pLDMOS obtained by the embodiment of the present invention is designed the present invention and identical structural parameters
System SJ-pLDMOS and traditional SJ-nLDMOS current capacity is emulated obtained comparison diagram；
In figure, 1 is substrate, and 2 be N-type source substrate zone, and 3 be the first N+Body contact zone, 4 be the first P+Source region, 5 be the first grid
Dielectric layer, 6 be first grid, and 7 be source metal, and 8 be P-type semiconductor area, and 9 be N-type semiconductor area, and 10 be p-type drain region, and 11 are
Drain metal, 12 be substrate-assisted depletion layer, and 13 be dielectric layer, and 14 be substrate layer, and 15 be the resistance to nip in superjunction surface, and 16 be second
Gate dielectric layer, 17 be second grid, and 18 be floating electrode, and 19 be the 2nd N+Source region, 20 be the 2nd P+Body contact zone, 21 be heavily doped
Miscellaneous semiconductor region.
Embodiment
The present invention is described more fully with reference to the accompanying drawings, in Figure of description, identical label represents phase
With either similar component or element, main idea of the present invention is to provide a kind of new high pressure SJ-LDMOS, SJ- of the present invention
LDMOS device can be N-type SJ-LDMOS (SJ-nLDMOS) or p-type SJ-LDMOS (SJ-pLDMOS), and the present invention is real
Apply example specifically to illustrate with SJ-pLDMOS, correspondingly, SJ-nLDMOS principles are similar.
Embodiment 1：
Fig. 4 shows the structure cell for the SJ-pLDMOS device that the present invention is produced on body silicon substrate, including：P-type
Substrate 1, the N-type source substrate zone 2 positioned at the top layer side of P type substrate 1, the p-type positioned at the top layer opposite side of P type substrate 1
Drain region 10, the resistance to nip 15 in the superjunction surface on the surface of substrate 1 between N-type source substrate zone 2 and p-type drain region 10, wherein：P
The material of type substrate 1 can also be N-type semiconductor material, be not limited to the P-type semiconductor disclosed in the present embodiment, the superjunction
The resistance to nip 15 in surface has the P-type semiconductor area 8 and N-type semiconductor area 9 that setting is alternateed parallel to device horizontal direction, institute
Stating has the first separate N in N-type source substrate zone 2+The P of body contact zone 3 and the first+Source region 4；Device surface and the first N+Body
The P of contact zone 3 and the first+What source region 4 contacted is source metal 7, the first N+Body contact zone 3, part N-type source substrate zone 2 and part are super
The upper surface of the knot resistance to nip 15 in surface has the first gate dielectric layer 5, and the upper surface of first gate dielectric layer 5 has first grid
6；N-type source substrate zone 2, the first N+Body contact zone 3, the first P+Source region 4, source metal 7, the first gate dielectric layer 5 and the first grid
Pole 6 forms the first active area, and the resistance to phase of nip 15 of the first active area and superjunction surface forms the MOSFET of P-type channel close to side；Its
It is characterised by：
There is the 2nd separate N in the p-type drain region 10+The P of source region 19 and the 2nd+Body contact zone 20；Device surface with
2nd N+The P of source region 19 and the 2nd+What body contact zone 20 contacted is drain metal 11, also has heavy doping half in the p-type drain region 10
Conductor region 21, the conduction type of the heavily-doped semiconductor 21 can be p-type, or N-type, so the present invention is not done to this
Limit, the upper surface of heavily-doped semiconductor area 21 has floating electrode 18, the P of heavily-doped semiconductor area 21 and the 2nd+Body
It is not present the p-type heavily-doped semiconductor region of the two connection, the 2nd N between contact zone 20+Source region 19, part p-type drain region 10
And the upper surface of the resistance to nip 15 in part superjunction surface has the second gate dielectric layer 16, the upper table mask of second gate dielectric layer 16
There is second grid 17, the grid 17 is connected with the floating electrode 18；The p-type drain region 10, the 2nd N+ source regions 19, second
P+Body contact zone 20, P+Semiconductor region 21, drain metal 11, the second gate dielectric layer 16, second grid 17 and floating electrode 18 are formed
Second active area, the resistance to phase of nip 15 of the second active area and superjunction surface form the MOSFET of N-type channel close to side.
The floating electrode 18 is connected with second grid, and therefore, LDMOS device proposed by the present invention is still three ends
Device.
Embodiment 2：
Fig. 5 shows the structure cell for the SJ-pLDMOS device that the present invention is produced on body silicon substrate, and this implementation removes
Also have outside substrate-assisted depletion layer 12 between the resistance to nip 15 of P type substrate 1 and superjunction surface, remaining structure with implementation
Example 1 is identical.
Specifically, when substrate is that semiconductor is lightly doped in p-type, substrate between the substrate and the resistance to nip in superjunction surface
The conduction type of assisted depletion layer is N-type；N-type substrate assisted depletion layer in x directions be as shown in the figure by Uniform Doped, it is linear gradually
Varying doping or the N-type semiconductor of subsection gradual doping are formed, and its doping concentration gradually drops from N-type source substrate zone to p-type drain region
It is low.
Specifically, when substrate is that semiconductor is lightly doped in N-type, substrate between the substrate and the resistance to nip in superjunction surface
The conduction type of assisted depletion layer is p-type；P type substrate assisted depletion layer is adulterated or is segmented gradually by Uniform Doped, linear gradient
The P-type semiconductor of varying doping is formed, and its doping concentration gradually rises from N-type source substrate zone to p-type drain region.
Similarly, it can be seen from general knowledge known in this field：For SJ-nLDMOS, when substrate is that semiconductor is lightly doped in p-type
When, the conduction type of substrate-assisted depletion layer is N-type between the substrate and the resistance to nip in superjunction surface, and N-type substrate aids in
Depletion layer is formed by the N-type semiconductor of Uniform Doped, linear gradient doping or subsection gradual doping, and its doping concentration is from p-type
Source substrate zone to N-type drain region gradually rises；When substrate is that semiconductor is lightly doped in N-type, the substrate and the superjunction surface are resistance to
The conduction type of substrate-assisted depletion layer is p-type between nip；N-type substrate assisted depletion layer is mixed by Uniform Doped, linear gradient
The P-type semiconductor of miscellaneous or subsection gradual doping is formed, and its doping concentration gradually reduces from p-type source substrate zone to N-type drain region.
Embodiment 3：
Fig. 6 shows that the present invention makes the specific embodiment of a pLDMOS device cellular on soi substrates, this implementation
With in addition to P type substrate 1 is replaced with into SOI substrate, remaining structure is same as Example 1；Wherein, SOI substrate includes lining
Bottom 14 and the insulating medium layer 13 on the substrate layer 14, the doping type of the substrate layer 14 can be p-type,
Can be N-type, the present embodiment selects P type substrate layer.
Embodiment 4：
Fig. 7 shows that the present invention makes the specific embodiment of a pLDMOS device cellular on soi substrates, this implementation
With in addition to P type substrate 1 is replaced with into SOI substrate, remaining structure is same as Example 2；Wherein, SOI substrate includes lining
Bottom 14 and the insulating medium layer 13 on the substrate layer 14, the doping type of the substrate layer 14 can be p-type,
Can be N-type, the present embodiment selects N-type substrate layer.
Embodiment 5：
The present embodiment except between the resistance to nip of SOI substrate and superjunction surface also have substrate-assisted depletion layer in addition to, its
Remaining structure is same as Example 3.
Specifically, if the SOI substrate connects maximum potential, substrate aids between substrate and the resistance to nip in superjunction surface
The conduction type of depletion layer is p-type, and P type substrate assisted depletion layer is mixed by Uniform Doped, linear gradient doping or subsection gradual
Miscellaneous p-type semiconductor material is formed, and its doping concentration gradually rises from N-type source substrate zone to p-type drain region；If the SOI substrate
Potential minimum is connect, then the conduction type of substrate-assisted depletion layer is N-type between substrate and the resistance to nip in superjunction surface；N-type serves as a contrast
Bottom assisted depletion layer is formed by the N-type semiconductor material of Uniform Doped, linear gradient doping or subsection gradual doping, and it is adulterated
Concentration gradually reduces from N-type source substrate zone to p-type drain region.
Similarly, it can be seen from general knowledge known in this field：For SJ-nLDMOS, if the SOI substrate connects highest electricity
Position, then the conduction type of substrate-assisted depletion layer is p-type between substrate and the resistance to nip in superjunction surface, and P type substrate auxiliary consumes
Layer is formed by the p-type semiconductor material of Uniform Doped, linear gradient doping or subsection gradual doping to the greatest extent, and its doping concentration is from P
Type source substrate zone to N-type drain region gradually reduces；If the SOI substrate connects potential minimum, substrate and the superjunction surface are pressure-resistant
The conduction type of substrate-assisted depletion floor is N-type between area；N-type substrate assisted depletion layer is adulterated by Uniform Doped, linear gradient
Or the N-type semiconductor material of subsection gradual doping is formed, its doping concentration gradually rises from p-type source substrate zone to N-type drain region.
Based on embodiment disclosed above, the principle of the invention is described in detail with reference to Figure of description：
Such as the embodiment that provides of the present invention, when the first conduction type is p-type, and the second conduction type is N-type：This
The first active area forms p-type MOSFET with the resistance to nip in superjunction surface in invention, and N-type semiconductor material is used in first active area
Material forms source substrate zone, and the source substrate zone also has independent P+Type area and N+Type area, the P+Type area and N+Type area is adjacent simultaneously
And the source electrode for the MOSFET for forming the first conduction type, the part P are contacted with metallic conductor+Type area, part N-type source substrate
There is dielectric layer on the resistance to nip in area and part superjunction surface, there is metallic conductor to form gate electrode for the dielectric layer upper surface, this
When the second active area be p-type MOSFET drain terminal；Source substrate zone is formed using p-type semiconductor material in second active area,
The source substrate zone equally has independent another P+Type area and another N+Type area, the P+Type area and N+Type area it is adjacent and with
Metallic conductor contact forms N-type MOSFET source electrode, the part P+Type area, part p-type drain region and part superjunction surface are pressure-resistant
Equally there is another dielectric layer, there is metallic conductor to form gate electrode for another dielectric layer upper surface, and now first has in area
Source region is N-type MOSFET drain terminal；
When the first conduction type is p-type, and the second conduction type is N-type, from the point of view of Figure of description, the present invention uses
2nd P+Body contact zone 20 is used as drain electrode contact area, and has the heavily-doped semiconductor area 21 for separating setting therewith, due to
Therebetween be not present by the two connection heavily-doped semiconductor region, in other words, therebetween P-type semiconductor region (
It is exactly p-type drain region 10) larger distributed resistance be present.Thus, after p-type MOSFET is opened under applied voltage, superjunction surface
P-type carrier (hole) if wanting to reach drain electrode, has to flow through heavy doping and partly led in P-type semiconductor area 8 in resistance to nip 15
The P of body area 21 and the 2nd+The distributed resistance of P-type semiconductor region between body contact zone 20, during this on distributed resistance
Electric current causes heavily-doped semiconductor area 21 relative to the 2nd P+Voltage difference caused by body contact zone 20 be on the occasion of；Again due to heavy doping
Floating electrode 18 on semiconductor region 21 is connected with the second gate electrode 17, and above-mentioned voltage difference causes the N under the second gate dielectric layer 16
Type raceway groove is opened, it is achieved thereby that automatically turning on the N-type MOSFET that the second active area is formed with the resistance to nip 15 in superjunction surface, is entered
And make it that N-type carrier (electronics) participates in conductive as majority carrier in the resistance to nip 15 in superjunction surface.
Similarly, when the first conduction type is N-type, and the second conduction type is p-type, the present invention uses the 2nd N+Body contact zone
As drain electrode contact area, and with the heavily-doped semiconductor area for separating setting therewith, due to being not present two therebetween
Person connection heavily-doped semiconductor region, in other words, therebetween N-type semiconductor region (namely N-type drain region) exist compared with
Big distributed resistance, thus, after N-type MOSFET is opened under applied voltage, N-type in n type semiconductor layer in the resistance to nip in surface
Carrier (electronics) has to flow through heavily-doped semiconductor area and the 2nd N if wanting to reach drain electrode+N-type between body contact zone
The distributed resistance of the semiconductor regions in drain region, the electric current during this on distributed resistance cause heavily-doped semiconductor area relative to
N+Voltage difference caused by body contact zone is negative value, and due to the floating electrode in heavily-doped semiconductor area and the second gate electrode phase
Even, above-mentioned voltage difference causes the P-type channel under the second gate dielectric layer to open, it is achieved thereby that automatically turning on the second active area with surpassing
The p-type MOSFET that the knot resistance to nip in surface is formed, and then make it that p-type carrier (hole) is as most in the resistance to nip in superjunction surface
Carrier participates in conductive.
From the point of view of Figure of description, in order to rationally design point of each semiconductor regions and electrode on structure cell surface
Cloth, according to coordinate system in figure, the 2nd P in the present embodiment+Body contact zone 20 and heavily-doped semiconductor area 21 be arranged at as
Z directions shown in figure, define the 2nd P+The distance between body contact zone 20 and heavily-doped semiconductor area 21 are W2, define the 2nd P+Body
The length of contact zone 20 in a z-direction is W3, due to the 2nd P+P-type leakage between body contact zone 20 and heavily-doped semiconductor area 21
There is body bias effect in area 10, and the 2nd P+Body bias effect is not present in the p-type drain region 10 of the lower section of body contact zone 20, so, the 2nd P+Body
Length of the contact zone 20 in z directions is bigger, participates in the electronic current of conduction in the resistance to nip 15 in superjunction surface in N-type semiconductor area 9
Account for that total current ratio is bigger, so so that the average current density of device is bigger, and finally tend to saturation.
Understood according to experiment：When device is SJ-nLDMOS, the current capacity of device architecture of the present invention compares traditional devices
Improve 1/3rd or so.When device is SJ-pLDMOS, the current capacity of device architecture of the present invention improves compared to traditional devices
Three times or so.
Preferably, W2Not less than 20 μm；
Further, it is L to define the length of the 2nd N+ source regions 19 in a z-direction19, the 2nd P+Body contact zone 20 is in z directions
On length be L20；L19L can be more than20, L19L can be less than20, L19L can also be equal to20；
In order to avoid conductivity modulation effect, L19And L20Value should meet：L19-L20≦50μm。
Fig. 8 gives traditional devices under SJ-pLDMOS and identical parameters according to the pressure-resistant 600V of the invention designed
Simulation comparison result figure.As can be seen from Figure 8：In the case of not optimized, with source and drain during break-over of device
Voltage raises, the P of heavily-doped semiconductor area 21 to the 2nd+Voltage difference on the path of body contact zone 20 gradually rises.When device source and drain
When voltage is increased to about 2.3V, the voltage difference on above-mentioned path causes N-type electron channel to open, so that superjunction surface is pressure-resistant
A large amount of electronics participate in conductive in N-type semiconductor area 9 in area 15.Assuming that 600V LDMOS specified conduction voltage drop is in 5V or so,
So now the current capacity of device of the present invention is more than SJ-nLDMOS, even more much larger than the SJ-pLDMOS under same process.
Due to the 2nd P+There is part N-type carrier (electronics) to deposit in p-type drain region 10 between body contact zone 20 and heavily-doped semiconductor area 21
In body bias effect, from heavily-doped semiconductor area 21 to the 2nd P+Body contact zone 20 forms interface, the 2nd P with p-type drain region 10+
Electronic current between body contact zone 20 and heavily-doped semiconductor area 21 in region is by 0 gradually increase.And the 2nd P+Body contact zone
Body bias effect is not present in 20 lower sections p-type drain region 10, so the electron current density in the region can reach maximum and uniform, because
This, as can be seen from Figure 8：With W3Increase, the total average current density of device gradually increases, and finally tends to saturation.
On the other hand, the W when embodiment of the present invention emulates2For 28 μm, and with W2Increase, heavily-doped semiconductor area 21 to
2nd P+Voltage difference on the path of body contact zone 20 will cause under the second gate dielectric layer 16 under lower device source-drain voltage
Electron channel is opened, and now, device will obtain higher electric current under lower source-drain voltage, anticipate as indicated by the dotted lines in figure 8.
It is important to note that now device is still unipolarity conduction, the bipolar device rather than IGBT etc forms conductance
Modulation is conductive, so the LDMOS of the present invention is while current capacity is greatly improved, the turn-off time still with unipolar device one
Sample, it can turn off as quick as thought.
Embodiments of the invention are set forth above in association with accompanying drawing, but the invention is not limited in above-mentioned specific
Embodiment, above-mentioned embodiment is only schematical, rather than restricted.One of ordinary skill in the art exists
Under the enlightenment of the present invention, in the case of present inventive concept and scope of the claimed protection is not departed from, many shapes can be also made
Formula, these are belonged within the protection of the present invention.
Claims (6)
1. a kind of super LDMOS device, its structure cell include：Substrate, the second conductive-type positioned at the substrate top layer side
Type semiconductor source substrate zone, positioned at the first conductive type semiconductor drain region of the substrate top layer opposite side, positioned at described second
The resistance to nip in superjunction surface of substrate surface, institute between conductive type semiconductor source substrate zone and the first conductive type semiconductor drain region
State the resistance to nip in superjunction surface have parallel to device horizontal direction alternate setting the first conductiving type semiconductor area and
Second conductiving type semiconductor area, have in the second conductive type semiconductor source substrate zone separate second conductive
Type heavy doping body contact zone one and the first conduction type heavy doping source region one；Device surface and the second conduction type heavy doping body
What contact zone one and first conduction type heavy doping source region one contacted is source metal, the first conduction type heavy doping source region one,
The upper surface of the resistance to nip of part the second conductive type semiconductor source substrate zone and part superjunction surface has the first gate dielectric layer, institute
The upper surface for stating the first gate dielectric layer has first grid；The second conductive type semiconductor source substrate zone, the second conductive-type
Type heavy doping body contact zone one, the first conduction type heavy doping source region one, source metal, the first gate dielectric layer and first grid shape
Into the first active area, the first active area mutually forms the first conduction type MOSFET with the resistance to nip in superjunction surface close to side；Its feature
It is：
There is the second separate conduction type heavy doping source region two and first in the first conductive type semiconductor drain region
Conduction type heavy doping body contact zone two；Device surface and the second conduction type heavy doping source region two and the first conduction type are heavily doped
What miscellaneous body contact zone two contacted is drain metal, also has heavily-doped semiconductor in the first conductive type semiconductor drain region
Area, the heavily-doped semiconductor area are the first conductive type semiconductor area or the second conductive type semiconductor area, described heavily doped
Miscellaneous semiconductor region upper surface has floating electrode, the heavily-doped semiconductor area and the first conduction type heavy doping body contact zone two
Between be not present by the two connection the first conduction type heavily-doped semiconductor region, the second conduction type heavy doping source region two,
The upper surface of the resistance to nip in the conductivity type drain region of part first and part superjunction surface has the second gate dielectric layer, and the second gate is situated between
The upper surface of matter layer has second grid, and the second grid is connected with the floating electrode；First conduction type half
Conductor drain region, the second conduction type heavy doping source region two, the first conduction type heavy doping body contact zone two, heavily-doped semiconductor
Area, drain metal, the second gate dielectric layer, second grid and floating electrode form the second active area, the second active area and superjunction table
The resistance to nip in face mutually forms the second conduction type MOSFET close to side.
A kind of 2. LDMOS device according to claim 1, it is characterised in that the second conduction type heavy doping source region
Two and the first conduction type heavy doping body contact zone two be set up in parallel；Define the second conduction type heavy doping source region two and
The longitudinal length of one conduction type heavy doping body contact zone two is sequentially L19And L20, then the two meet：L19-L20≦50μm。
A kind of 3. super junction LDMOS device according to claim 1 or 2, it is characterised in that the first conduction type is p-type, the
Two conduction types are N-type.
A kind of 4. super junction LDMOS device according to claim 1 or 2, it is characterised in that the first conduction type is N-type, the
Two conduction types are p-type.
5. a kind of super junction LDMOS device according to claim 1 or 2, it is characterised in that the substrate is p-type or N-type
Semi-conducting material is lightly doped, the semi-conducting material is body silicon, gallium nitride or carborundum.
6. a kind of super junction LDMOS device according to claim 1 or 2, it is characterised in that the substrate is SOI substrate, institute
Stating SOI substrate includes semiconductor layer and the dielectric layer disposed thereon of p-type or N-type.
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| CN108365006A (en) * | 2018-02-10 | 2018-08-03 | 重庆大学 | A kind of high speed super-junction laterally insulated gate bipolar transistor |
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| JP2000114520A (en) * | 1998-10-07 | 2000-04-21 | Toshiba Corp | Semiconductor device for electric power |
| CN101771082A (en) * | 2009-12-30 | 2010-07-07 | 四川长虹电器股份有限公司 | Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate |
| CN104201206A (en) * | 2014-08-29 | 2014-12-10 | 电子科技大学 | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000114520A (en) * | 1998-10-07 | 2000-04-21 | Toshiba Corp | Semiconductor device for electric power |
| CN101771082A (en) * | 2009-12-30 | 2010-07-07 | 四川长虹电器股份有限公司 | Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate |
| CN104201206A (en) * | 2014-08-29 | 2014-12-10 | 电子科技大学 | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108365006A (en) * | 2018-02-10 | 2018-08-03 | 重庆大学 | A kind of high speed super-junction laterally insulated gate bipolar transistor |
| CN108365006B (en) * | 2018-02-10 | 2020-12-01 | 重庆大学 | High-speed super-junction lateral insulated gate bipolar transistor |
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