CN101771085A - High-voltage semi-conductor device and manufacturing method thereof - Google Patents
High-voltage semi-conductor device and manufacturing method thereof Download PDFInfo
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- CN101771085A CN101771085A CN201010028147A CN201010028147A CN101771085A CN 101771085 A CN101771085 A CN 101771085A CN 201010028147 A CN201010028147 A CN 201010028147A CN 201010028147 A CN201010028147 A CN 201010028147A CN 101771085 A CN101771085 A CN 101771085A
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Abstract
The invention provides a high-voltage semi-conductor device and a manufacturing method thereof, belonging to the technical field of semi-conductor power device. On the basis of the existing lateral high-voltage DMOS device structure with a reduced-field layer structure, a layer of second conduction type semi-conductor epitaxial layer (5) is added between a field oxidation layer (7) and a first conduction type semi-conductor reduced-field layer (3); and simultaneously a layer of first conduction type semi-conductor burial layer body region (4) is added between a first conduction type semi-conductor body region (6) and a first conduction type semi-conductor substrate (1). In the invention, the second conduction type semi-conductor epitaxial layer (5) is added through the epitaxial technique, thus providing an extra surface conducting channel for the device; compared with conventional high-voltage semi-conductor device with the reduced-field layer, the high-voltage semi-conductor device provided in the invention has less on resistance under the condition of having the same chip area (or has smaller chip area under the condition of having the same conducting capability). The invention can be used in the products such as consumer electronics and display drivers and the like.
Description
Technical field
The invention belongs to the semiconductor power device technology field.
Background technology
Laterally high pressure DMOS (Double-diffused MOSFET) device is widely used in the high-voltage power integrated circuit because its source electrode, drain and gate all at chip surface, are easy to connect with low voltage logic circuit monolithic by inside integrated.But because there are Ron ∝ BV in the conducting resistance Ron and the device withstand voltage BV of DMOS device
2.3～2.6Relation, make device when high-voltage applications, conducting resistance sharply rises, this has just limited the application of horizontal high pressure DMOS device in high-voltage power integrated circuit, especially in the circuit that requires low conduction loss and little chip area.In order to overcome the problem of high conducting resistance, people such as J.A.APPLES have proposed RESURF (Reduced SURface Field) and have reduced the surface field technology, are widely used in the design of high tension apparatus, but still can not effectively solve the problem of high conducting resistance.
Summary of the invention
The high-voltage semi-conductor device and the manufacture method thereof that the purpose of this invention is to provide a kind of novel low conduction loss.Described high-voltage semi-conductor device has a high-voltage semi-conductor device that falls the field layer with routine to be compared, and has littler conducting resistance (or having littler chip area under the situation of identical ducting capacity) under the situation of identical chips area.Described manufacture method is simple, and technology difficulty is relatively low.
The objective of the invention is to reach like this: the invention provides a kind of high-voltage semi-conductor device, as shown in Figure 2, comprise the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 2, a layer 3 falls in first conductive type semiconductor, the first conductive type semiconductor tagma 6, field oxide 7, gate oxide 8, grid 9, the second conductive type semiconductor drain region (or first conductive type semiconductor anode region) 10, the second conductive type semiconductor source region (or second conductive type semiconductor cathodic region) 11, the first conductive type semiconductor body contact zone 12, medium 13 before the metal, source metal (or cathodic metal) 14, drain metal (or anode metal) 15; It is characterized in that, described high-voltage semi-conductor device also comprises the first conductive type semiconductor buried regions tagma 4 and the second conductive type semiconductor epitaxial loayer 5, and the described second conductive type semiconductor epitaxial loayer 5 falls between the layer 3 at the field oxide 7 and first conductive type semiconductor; The described first conductive type semiconductor buried regions tagma 4 is between the first conductive type semiconductor tagma 6 and the first conductive type semiconductor substrate 1.
Operation principle of the present invention:
The invention provides a kind of high-voltage semi-conductor device, its operation principle and traditional horizontal high pressure DMOS device are similar, all are to use the puncture voltage that charge balance concept improves device, but the break-over of device loss among the present invention is lower than laterally high pressure DMOS device of tradition.Fig. 1 is traditional horizontal high pressure DMOS device, comprises that layer 3, first a conductive type semiconductor tagma 6, field oxide 7, gate oxide 8, grid 9, the second conductive type semiconductor drain region 10, the second conductive type semiconductor source region 11, the first conductive type semiconductor body contact zone 12, the preceding medium 13 of metal, source metal 14, drain metal 15 fall in the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 2, first conductive type semiconductor.Electric current flows to the second conductive type semiconductor drain region 10 from the second conductive type semiconductor source region 11 through the second conductive type semiconductor drift region 2 during break-over of device, because an existence of layer 3 falls in first conductive type semiconductor, electric current can not pass through from device surface, the path that electric current flows is elongated, it is big that the conducting resistance of device becomes, and conduction loss increases.Fig. 2 is a high-voltage semi-conductor device of the present invention, have a horizontal high pressure DMOS who falls layer structure and compare with existing, device provided by the invention has increased by the second conductive type semiconductor epitaxial loayer 5, an extra surface conductance passage is provided by epitaxy technique, and reduced the path that surface current flows, reduced break-over of device resistance.Fig. 3 is that Fig. 4 is 60 microns positions CONCENTRATION DISTRIBUTION longitudinally for its lateral separation by the grid chart of a kind of traditional horizontal high pressure DMOS device of the MEDICI of two-dimensional device simulation software definition.Fig. 5 is the provided by the invention a kind of high voltage semiconductor device structure figure by the MEDICI of two-dimensional device simulation software definition, and Fig. 6 is 60 microns positions CONCENTRATION DISTRIBUTION longitudinally for its lateral separation.Fig. 7 has provided the contrast of traditional down laterally high pressure DMOS device of the identical bias voltage of same size and high-voltage semi-conductor device linear zone electric current provided by the invention, as seen break-over of device electric current provided by the invention is higher than laterally high pressure DMOS device of tradition, thereby the conducting resistance of device is lower than traditional horizontal high pressure DMOS device.Therefore, in power integrated circuit was used, under the condition of same output current ability, the area of high-voltage semi-conductor device was minimized.
High-voltage semi-conductor device manufacture method provided by the invention may further comprise the steps:
The first step: adopt photoetching and ion implantation technology in the first conductive type semiconductor substrate 1, to inject second conductive type semiconductor, and diffuse to form the second conductive type semiconductor drift region 2; The resistivity of the described first conductive type semiconductor substrate 1 is 10～200 ohmcms, and the implantation dosage of the second conductive type semiconductor drift region 2 is 1E12cm
-2～1E13cm
-2
Second step: adopt photoetching and ion implantation technology, in the second conductive type semiconductor drift region 2, inject first conductive type semiconductor and form first conductive type semiconductor and fall a layer 3, in the first conductive type semiconductor substrate 1, form the first conductive type semiconductor buried regions tagma 4 simultaneously; It is 5E11cm that an implantation dosage in the layer 3 and first conductive type semiconductor buried regions tagma 4 falls in described first conductive type semiconductor
-2～1E13cm
-2
The 3rd step: the chip upper surface epitaxial growth second conductive type semiconductor epitaxial loayer 5 after handling through first and second step; The thickness of the described second conductive type semiconductor epitaxial loayer 5 is that 1 micron～5 microns, concentration are 1E15cm
-3～1E16cm
-3
The 4th step: adopt photoetching and ion implantation technology, on the second conductive type semiconductor epitaxial loayer 5, inject first conductive type semiconductor, form the first conductive type semiconductor tagma 6; The implantation dosage in the described first conductive type semiconductor tagma 6 is 1E12cm
-2～1E14cm
-2
The 5th step: adopt silicon selective oxidation LOCOS (LOCal Oxidation of Silicon) technology to form field oxide 7;
The 6th step: form the gate oxide 8 of device, the thickness of described gate oxide 8 is 7nm～100nm;
The 7th step: form the polysilicon gate 9 of device, the square resistance of described polysilicon gate 9 is 10～40 ohms/square;
The 8th step: adopt photoetching and ion implantation technology, form 11, the first conductive type semiconductor body contact zone 12,10, the second conductive type semiconductor source region, the second conductive type semiconductor drain region (or first conductive type semiconductor anode region) (or second conductive type semiconductor cathodic region) of device; The implantation dosage of 11, the first conductive type semiconductor body contact zone 12,10, the second conductive type semiconductor source region, the described second conductive type semiconductor drain region (or first conductive type semiconductor anode region) (or second conductive type semiconductor cathodic region) is 1E15cm
-2～2E16cm
-2
The 9th step: form the preceding medium 13 of metal;
The tenth step: form source metal (or cathodic metal) 14 and drain metal (or anode metal) 15.
Need to prove that the buried regions tagma 4 of a described class impurity when the thin or first conductive type semiconductor tagma, 6 junction depths are dark at the second conductive type semiconductor epitaxial loayer 5, can not done.Described first conductive type semiconductor falls a buried regions tagma 4 of layer 3 and one class impurity and can form step by step, also can form simultaneously.
Advantage of the present invention is: the present invention increases by the second conductive type semiconductor epitaxial loayer 5, an extra surface conductance passage is provided by epitaxy technique, with the second conductive type semiconductor drift region 2, for device provides two conductive channels.Owing to adopt epitaxy technique to increase an extra surface conductance passage, reduced the path that surface current flows, therefore reduced the conducting resistance of device.Have a high-voltage semi-conductor device that falls the field layer with routine and compare, high-voltage semi-conductor device provided by the invention has littler conducting resistance (or having littler chip area under the situation of identical ducting capacity) under the situation of identical chips area.High-voltage semi-conductor device provided by the invention can be applicable in the multiple products such as consumer electronics, display driver.
Description of drawings
Fig. 1 is the existing horizontal high pressure DMOS device architecture schematic diagram that falls field layer structure that has.
Wherein, 1 be the first conductive type semiconductor substrate, 2 be the second conductive type semiconductor drift region, 3 be first conductive type semiconductor to fall layer, 6 are first conductive type semiconductor tagmas, the 7th, field oxide, the 8th, gate oxide, the 9th, grid, 10 are that the second conductive type semiconductor drain region, 11 is second conductive type semiconductor source regions, the 12nd, medium, the 14th before the body contact zone, the 13rd, metal, source metal, the 15th, drain metal.
Fig. 2 is a kind of high voltage semiconductor device structure schematic diagram provided by the invention.
Wherein, 1 is the first conductive type semiconductor substrate, 2 is second conductive type semiconductor drift regions, 3 is that a layer falls in first conductive type semiconductor, 4 is first conductive type semiconductor buried regions tagmas, 5 is second conductive type semiconductor epitaxial loayers, 6 is first conductive type semiconductor tagmas, the 7th, field oxide, the 8th, gate oxide, the 9th, grid, 10 is the second conductive type semiconductor drain region (or first conductive type semiconductor anode regions), 11 is the second conductive type semiconductor source region (or second conductive type semiconductor cathodic regions), 12 is first conductive type semiconductor body contact zones, the 13rd, medium before the metal, the 14th, source metal (or cathodic metal), the 15th, drain metal (or anode metal).
Fig. 3 is the existing grid chart with the horizontal high pressure DMOS device that falls field layer structure by the MEDICI of two-dimensional device simulation software definition.
Fig. 4 has by the MEDICI of two-dimensional device simulation software definition existing that to fall a horizontal high pressure DMOS device of layer structure be 60 microns positions CONCENTRATION DISTRIBUTION longitudinally in lateral separation.
Fig. 5 is the grid chart by the high-voltage semi-conductor device provided by the invention of the MEDICI of two-dimensional device simulation software definition.
Fig. 6 is that the high-voltage semi-conductor device provided by the invention that defines by the MEDICI of two-dimensional device simulation software is 60 microns positions CONCENTRATION DISTRIBUTION longitudinally in lateral separation.
Fig. 7 is when Vgs=5V, existing relation curve schematic diagram with the horizontal high pressure DMOS device that falls layer structure and high-voltage semi-conductor device provided by the invention drain-source current and drain-source voltage when linear zone.Wherein dotted line is an existing horizontal high pressure DMOS device drain-source current and the drain-source voltage relation curve that falls field layer structure that have, and solid line is high-voltage semi-conductor device drain-source current provided by the invention and drain-source voltage relation curve.As seen from the figure, when Vds=10V, an existing electric current with the horizontal high pressure DMOS device that falls field layer structure is 41 μ A/ μ m; Device current provided by the invention is 53 μ A/ μ m, and current capacity has improved 29% than traditional structure.
Embodiment
The invention provides a kind of a kind of high-voltage semi-conductor device of realizing with epitaxy technique, its technology difficulty is low, and is workable, selects dissimilar substrates and impurity can produce the high-voltage semi-conductor device of n raceway groove and p raceway groove.
The invention provides a kind of high-voltage semi-conductor device, as shown in Figure 2, comprise the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 2, a layer 3 falls in first conductive type semiconductor, the first conductive type semiconductor tagma 6, field oxide 7, gate oxide 8, grid 9, the second conductive type semiconductor drain region (or first conductive type semiconductor anode region) 10, the second conductive type semiconductor source region (or second conductive type semiconductor cathodic region) 11, the first conductive type semiconductor body contact zone 12, medium 13 before the metal, source metal (or cathodic metal) 14, drain metal (or anode metal) 15; It is characterized in that, described high-voltage semi-conductor device also comprises the first conductive type semiconductor buried regions tagma 4 and the second conductive type semiconductor epitaxial loayer 5, and the described second conductive type semiconductor epitaxial loayer 5 falls between the layer 3 at the field oxide 7 and first conductive type semiconductor; The described first conductive type semiconductor buried regions tagma 4 is between the first conductive type semiconductor tagma 6 and the first conductive type semiconductor substrate 1.
High-voltage semi-conductor device manufacture method provided by the invention may further comprise the steps:
The first step: adopt photoetching and ion implantation technology in the first conductive type semiconductor substrate 1, to inject second conductive type semiconductor, and diffuse to form the second conductive type semiconductor drift region 2; The resistivity of the described first conductive type semiconductor substrate 1 is 10～200 ohmcms, and the implantation dosage of the second conductive type semiconductor drift region 2 is 1E12cm
-2～1E13cm
-2
Second step: adopt photoetching and ion implantation technology, in the second conductive type semiconductor drift region 2, inject first conductive type semiconductor and form first conductive type semiconductor and fall a layer 3, in the first conductive type semiconductor substrate 1, form the first conductive type semiconductor buried regions tagma 4 simultaneously; It is 5E11cm that an implantation dosage in the layer 3 and first conductive type semiconductor buried regions tagma 4 falls in described first conductive type semiconductor
-2～1E13cm
-2
The 3rd step: the chip upper surface epitaxial growth second conductive type semiconductor epitaxial loayer 5 after handling through first and second step; The thickness of the described second conductive type semiconductor epitaxial loayer 5 is that 1 micron～5 microns, concentration are 1E15cm
-3～1E16cm
-3
The 4th step: adopt photoetching and ion implantation technology, on the second conductive type semiconductor epitaxial loayer 5, inject first conductive type semiconductor, form the first conductive type semiconductor tagma 6; The implantation dosage in the described first conductive type semiconductor tagma 6 is 1E12cm
-2～1E14cm
-2
The 5th step: adopt silicon selective oxidation LOCOS (LOCal Oxidation of Silicon) technology to form field oxide 7;
The 6th step: form the gate oxide 8 of device, the thickness of described gate oxide 8 is 7nm～100nm;
The 7th step: form the polysilicon gate 9 of device, the square resistance of described polysilicon gate 9 is 10～40 ohms/square;
The 8th step: adopt photoetching and ion implantation technology, form 11, the first conductive type semiconductor body contact zone 12,10, the second conductive type semiconductor source region, the second conductive type semiconductor drain region (or first conductive type semiconductor anode region) (or second conductive type semiconductor cathodic region) of device; The implantation dosage of 11, the first conductive type semiconductor body contact zone 12,10, the second conductive type semiconductor source region, the described second conductive type semiconductor drain region (or first conductive type semiconductor anode region) (or second conductive type semiconductor cathodic region) is 1E15cm
-2～2E16cm
-2
The 9th step: form the preceding medium 13 of metal;
The tenth step: form source metal (or cathodic metal) 14 and drain metal (or anode metal) 15.
The present invention increases by the second conductive type semiconductor epitaxial loayer 5, an extra surface conductance passage is provided by epitaxy technique, with the second conductive type semiconductor drift region 2, for device provides two conductive channels.Owing to adopt epitaxy technique to increase an extra surface conductance passage, reduced the path that surface current flows, therefore reduced the conducting resistance of device.Have a high-voltage semi-conductor device that falls the field layer with routine and compare, high-voltage semi-conductor device provided by the invention has littler conducting resistance (or having littler chip area under the situation of identical ducting capacity) under the situation of identical chips area.High-voltage semi-conductor device provided by the invention can be applicable in the multiple products such as consumer electronics, display driver.
Claims (2)
1. a high-voltage semi-conductor device comprises the first conductive type semiconductor substrate (1), the second conductive type semiconductor drift region (2), a layer (3) falls in first conductive type semiconductor, the first conductive type semiconductor tagma (6), field oxide (7), gate oxide (8), grid (9), the second conductive type semiconductor drain region or the first conductive type semiconductor anode region (10), the second conductive type semiconductor source region or the second conductive type semiconductor cathodic region (11), the first conductive type semiconductor body contact zone (12), medium (13) before the metal, source metal or cathodic metal (14), drain metal or anode metal (15); It is characterized in that, described high-voltage semi-conductor device also comprises the first conductive type semiconductor buried regions tagma (4) and the second conductive type semiconductor epitaxial loayer (5), and the described second conductive type semiconductor epitaxial loayer (5) is positioned at field oxide (7) and first conductive type semiconductor falls between the layer (3); The described first conductive type semiconductor buried regions tagma (4) is positioned between the first conductive type semiconductor tagma (6) and the first conductive type semiconductor substrate (1).
2. a high-voltage semi-conductor device manufacture method may further comprise the steps:
The first step: adopt photoetching and ion implantation technology in the first conductive type semiconductor substrate (1), to inject second conductive type semiconductor, and diffuse to form the second conductive type semiconductor drift region (2); The resistivity of the described first conductive type semiconductor substrate (1) is 10～200 ohmcms, and the implantation dosage of the second conductive type semiconductor drift region (2) is 1E12cm
-2～1E13cm
-2
Second step: adopt photoetching and ion implantation technology, in the second conductive type semiconductor drift region (2), inject first conductive type semiconductor and form first conductive type semiconductor and fall a layer (3), simultaneously the formation first conductive type semiconductor buried regions tagma (4) in the first conductive type semiconductor substrate (1); The implantation dosage that a layer (3) and the first conductive type semiconductor buried regions tagma (4) fall in described first conductive type semiconductor is 5E11cm
-2～1E13cm
-2
The 3rd step: the chip upper surface epitaxial growth second conductive type semiconductor epitaxial loayer (5) after handling through first and second step; The thickness of the described second conductive type semiconductor epitaxial loayer (5) is that 1 micron～5 microns, concentration are 1E15cm
-3～1E16cm
-3
The 4th step: adopt photoetching and ion implantation technology, go up at the second conductive type semiconductor epitaxial loayer (5) and inject first conductive type semiconductor, form the first conductive type semiconductor tagma (6); The implantation dosage in the described first conductive type semiconductor tagma (6) is 1E12cm
-2～1E14cm
-2
The 5th step: adopt silicon selective oxidation LOCOS technology to form field oxide (7);
The 6th step: form the gate oxide (8) of device, the thickness of described gate oxide (8) is 7nm～100nm;
The 7th step: form the polysilicon gate (9) of device, the square resistance of described polysilicon gate (9) is 10～40 ohms/square;
The 8th step: adopt photoetching and ion implantation technology, the second conductive type semiconductor drain region of formation device or the first conductive type semiconductor anode region (10), the second conductive type semiconductor source region or the second conductive type semiconductor cathodic region (11), the first conductive type semiconductor body contact zone (12); The implantation dosage of the described second conductive type semiconductor drain region or the first conductive type semiconductor anode region (10), the second conductive type semiconductor source region or the second conductive type semiconductor cathodic region (11), the first conductive type semiconductor body contact zone (12) is 1E15cm
-2～2E16cm
-2
The 9th step: form the preceding medium (13) of metal;
The tenth step: form source metal or cathodic metal (14) and drain metal or anode metal (15).
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Cited By (8)
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| CN102097389A (en) * | 2011-01-12 | 2011-06-15 | 深圳市联德合微电子有限公司 | LDMOS (laterally diffused metal oxide semiconductor), semiconductor device integrated with same and manufacturing method thereof |
| CN102148251A (en) * | 2011-01-10 | 2011-08-10 | 电子科技大学 | Semiconductor on insulator (SOI) lateral metal-oxide-semiconductor field-effect-transistor (MOSFET) device and integrated circuit |
| CN102709325A (en) * | 2012-06-25 | 2012-10-03 | 电子科技大学 | High-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device |
| CN102790092A (en) * | 2012-08-24 | 2012-11-21 | 电子科技大学 | Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device |
| CN103280457A (en) * | 2013-05-14 | 2013-09-04 | 电子科技大学 | Transverse high-voltage power device with ultralow specific on-conduction resistance and manufacturing method of transverse high-voltage power device |
| CN103413831A (en) * | 2013-08-30 | 2013-11-27 | 电子科技大学 | Horizontal high-voltage device and manufacturing method of horizontal high-voltage device |
| CN103413830A (en) * | 2013-08-16 | 2013-11-27 | 电子科技大学 | Laterally high-voltage MOSFET and manufacturing method thereof |
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| CN102148251A (en) * | 2011-01-10 | 2011-08-10 | 电子科技大学 | Semiconductor on insulator (SOI) lateral metal-oxide-semiconductor field-effect-transistor (MOSFET) device and integrated circuit |
| CN102148251B (en) * | 2011-01-10 | 2013-01-30 | 电子科技大学 | Semiconductor on insulator (SOI) lateral metal-oxide-semiconductor field-effect-transistor (MOSFET) device and integrated circuit |
| CN102097389A (en) * | 2011-01-12 | 2011-06-15 | 深圳市联德合微电子有限公司 | LDMOS (laterally diffused metal oxide semiconductor), semiconductor device integrated with same and manufacturing method thereof |
| CN102709325A (en) * | 2012-06-25 | 2012-10-03 | 电子科技大学 | High-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device |
| CN102790092A (en) * | 2012-08-24 | 2012-11-21 | 电子科技大学 | Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device |
| CN103280457A (en) * | 2013-05-14 | 2013-09-04 | 电子科技大学 | Transverse high-voltage power device with ultralow specific on-conduction resistance and manufacturing method of transverse high-voltage power device |
| CN103280457B (en) * | 2013-05-14 | 2016-03-23 | 电子科技大学 | A kind of horizontal high voltage power device of Ultra-low Specific conducting resistance and manufacture method |
| CN103413830A (en) * | 2013-08-16 | 2013-11-27 | 电子科技大学 | Laterally high-voltage MOSFET and manufacturing method thereof |
| CN103413830B (en) * | 2013-08-16 | 2016-08-31 | 电子科技大学 | A kind of laterally high-voltage MOSFET and manufacture method thereof |
| CN103413831A (en) * | 2013-08-30 | 2013-11-27 | 电子科技大学 | Horizontal high-voltage device and manufacturing method of horizontal high-voltage device |
| CN103474466A (en) * | 2013-09-13 | 2013-12-25 | 电子科技大学 | High-voltage device and manufacturing method thereof |
| CN103474466B (en) * | 2013-09-13 | 2016-06-08 | 电子科技大学 | A kind of high tension apparatus and manufacture method thereof |
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Application publication date: 20100707 |