WO2012094780A1 - Soi lateral mosfet device and integrated circuit thereof - Google Patents

Soi lateral mosfet device and integrated circuit thereof Download PDF

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Publication number
WO2012094780A1
WO2012094780A1 PCT/CN2011/000232 CN2011000232W WO2012094780A1 WO 2012094780 A1 WO2012094780 A1 WO 2012094780A1 CN 2011000232 W CN2011000232 W CN 2011000232W WO 2012094780 A1 WO2012094780 A1 WO 2012094780A1
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region
gate structure
buried layer
trench gate
semiconductor
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PCT/CN2011/000232
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French (fr)
Chinese (zh)
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WO2012094780A8 (en
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罗小蓉
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电子科技大学
姚国亮
雷天飞
王元刚
张波
李肇基
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Application filed by 电子科技大学, 姚国亮, 雷天飞, 王元刚, 张波, 李肇基 filed Critical 电子科技大学
Publication of WO2012094780A1 publication Critical patent/WO2012094780A1/en
Publication of WO2012094780A8 publication Critical patent/WO2012094780A8/en

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Definitions

  • the present invention relates to a semiconductor power device and an integrated circuit, and more particularly to an SOI (Semiconductor On Insulator) lateral MOSFET (Metal-Oxide-Semiconductor Field-Effect- for a power integrated circuit or a radio frequency power integrated circuit) Transistor, metal-oxide-semiconductor field effect transistor device and integrated circuit with the same.
  • SOI semiconductor On Insulator
  • MOSFET Metal-Oxide-Semiconductor Field-Effect- for a power integrated circuit or a radio frequency power integrated circuit
  • the SOI is to introduce a dielectric buried layer between a top-level semiconductor (referred to as an active layer) and a substrate layer (which may be a semiconductor or an insulating medium), and a semiconductor device or circuit is fabricated in the active layer.
  • the isolation trench 30 is usually used for isolation between the high voltage device and the low voltage circuit, and the active layer 3 and the substrate layer 1 are separated by the dielectric buried layer 2 (as shown in Fig. 1). Therefore, compared with bulk silicon technology, SOI technology has the advantages of small parasitic effect, small leakage current, high integration, strong radiation resistance and self-locking effect of thyristor, high speed, high temperature, low power consumption and radiation resistance. Such fields have received extensive attention and application.
  • SOI power integrated circuit technology is to achieve high withstand voltage, low power consumption, and effective isolation between the high voltage unit and the low voltage unit.
  • SOI lateral devices such as LDMOSFET (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor), because of their ease of integration and relatively low on-resistance Becoming a core component of SOI power ICs, it is favored in applications such as plasma display panels, motor drives, automotive electronics, portable power management products, and personal computers.
  • LDMOSFET Layer Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor
  • VDMOSFET Very Double-diffused Metal-Oxide- Semiconductor Field-Effect-Transistor, vertical double-diffused metal-oxide-semiconductor field effect transistor
  • the length of the drift region increases monotonically with the increase of the withstand voltage of the device, which not only increases the chip area, increases the cost, and is not conducive to miniaturization. More seriously, the on-resistance of the device is resistant to the device.
  • the increase in pressure increases (the relationship between on-resistance and device withstand voltage can be expressed as: BV 2 3 , where BV is the device withstand voltage, Ron is the on-resistance), the increase in on-resistance leads to an increase in the on-state power consumption, and the device switching speed also decreases.
  • the device of the trench gate structure has the following advantages: First, the package density can be increased to increase the channel density and current density; secondly, the channel length of the trench gate structure device is not limited by the photolithography process, and the channel can be made shorter , thereby reducing the on-resistance (the above two points will increase the trench gate structure device The current carrying capacity); Third, the trench gate MOSFET can avoid the JFET (Junction Field-Effect-Transistor) effect and the snapback (secondary breakdown) effect. However, for high voltage devices, since the drift region resistance accounts for a major portion of the device's on-resistance, the trench gate structure does not solve the silicon limit problem.
  • JFET Joint Field-Effect-Transistor
  • the reduced surface field is applied to the SOI device, which can completely deplete the drift region of the device during reverse bias and transfer the breakdown point from the surface to the body to obtain a higher breakdown voltage. This alleviates the problem of the silicon limit of the lateral high voltage device to some extent.
  • RP Zingg et al. applied dual RESURF (Double RESURF) technology to SOI high voltage devices, as shown in Figure 2, by inserting a lower-field layer of opposite conductivity type on the surface of the drift region to improve the surface electric field and obtain breakdown voltage and on-resistance. a good compromise.
  • This structure can double the optimized concentration of the drift region relative to a single RESURF (single RESURF), thereby reducing the specific on-resistance.
  • the present invention has been made to solve the above problems, and an object thereof is to provide an SOI lateral MOSFET device and an integrated circuit having the same, which can reduce the specific on-resistance and power consumption, and can improve the withstand voltage of the LDMOSFET. Reduces device lateral dimensions and chip area, and increases process tolerance.
  • the first aspect of the present invention is: an SOI lateral MOSFET device in which a substrate layer, a dielectric buried layer, and an active layer are stacked in this order from bottom to top, wherein
  • the source layer includes: body and drain regions respectively located on surfaces of the active layer and separated from each other, and a surface located on the body region and pressed from a side close to the drain region a planar gate channel region, a first source region, a body contact region, and a second source region; the active layer between the body region and the drain region is a drift region, and the drift region and
  • the body region has opposite conductivity types;
  • the active layer is provided with a semiconductor buried layer below the surface thereof, and the semiconductor buried layer and the body region have the same conductivity type;
  • the device has a trench gate structure and a planar gate structure a trench gate structure in contact with the body region and extending longitudinally from a surface of the active layer to the dielectric buried layer, the planar gate structure being formed above the body
  • the trench gate structure and the planar gate structure form a double gate structure, thereby forming a double conductive channel: under the planar gate structure, a planar gate channel region is formed on the surface of the body region, a body region or/and a semiconductor buried layer interface in contact with the trench gate structure forms a trench gate channel region, thereby reducing on-resistance; a vertically extending trench gate structure increases an effective conductive area, thereby reducing on-resistance;
  • the semiconductor buried layer increases the optimized concentration of the drift region to lower the specific on-resistance, and reduces the sensitivity of the device breakdown voltage to the buried position of the semiconductor; in addition, the device is used for a power integrated circuit, a trench of the device
  • the structure can also be used as an isolation trench between the high voltage region and the low voltage region, thereby reducing the isolation process steps and process cost of the SOI high voltage integrated circuit, and the trench gate structure reduces the JFET effect.
  • SOI LDM SOI LDM
  • the semiconductor buried layer is in contact with the body region, or the semiconductor buried layer is not in contact with the body region.
  • the third aspect of the present invention is: in the first or second aspect, the top view of the device is a symmetrical structure, the drain region is located at the center of the device, and the drain region is outwardly
  • the semiconductor buried layer, the body region, the first source region, the body contact region, the second source region, and the trench gate structure, the trench gate structure is located at a periphery of the device.
  • a fourth aspect of the present invention is:
  • the device is an axisymmetric structure, and a central axis of the drain region is an axis of symmetry of the device.
  • the device has a circular shape in a plan view, the semiconductor buried layer, the body region, and the first source region.
  • the body contact region, the second source region, and the trench gate structure are in the shape of a circular ring.
  • a sixth aspect of the present invention is: in the third aspect, the device is plane symmetrical
  • the trench gate structure is located on the periphery of the device,
  • the high potential from the center drain region of the device is terminated within the trench gate, facilitating isolation between the high voltage device and the low voltage control circuit outside the trench gate using the trench gate structure.
  • the symmetrical shape is optimal, and the curvature effect is attenuated, so that the withstand voltage is the highest and the chip area is saved.
  • a seventh aspect of the present invention is:
  • the device is used for a MOS controlled semiconductor device.
  • MOS controlled semiconductor device For example, it can be IGBT or LDMOS.
  • an eighth aspect of the present invention is: In the first or second aspect, the material of the active layer comprises Si, SiC, SiGe, GaAs or GaN.
  • the materials constituting the active layer are mature in technology and convenient in drawing, and can satisfy different device or circuit performance requirements.
  • the ninth aspect of the present invention is: in the first or second aspect, the material of the dielectric buried layer is SiO 2 , or the dielectric constant including SiOF or SiCOF is lower than SiO 2 and the critical breakdown The electric field is higher than three times the dielectric of the Si critical breakdown electric field.
  • the medium buried layer is made of a medium having a low dielectric constant, which can enhance the electric field of the buried layer of the medium, and is favorable for improving the withstand voltage of the device.
  • the tenth aspect of the present invention is: in the first or second aspect, the trench gate dielectric is Si0 2 , or is a dielectric including Si 3 N 4 , A1 2 0 3 , A1N or Hf0 2 coefficient is higher than the critical breakdown field Si0 2 and Si0 2 and comparable to or higher media.
  • the high dielectric constant trench gate dielectric can enhance the gate voltage control capability of the gate charge, increase the transconductance, or, in the same gate structure MIS (Metal-Insulator-Semiconductor, gate electrode -
  • MIS Metal-Insulator-Semiconductor, gate electrode -
  • the semiconductor under the gate dielectric-gate dielectric forms the MIS structure.
  • the trench gate dielectric Under the capacitor, the trench gate dielectric can be made thicker, the tunnel current can be reduced, the tunneling effect can be avoided, and the stability and reliability of the device or chip can be enhanced.
  • an eleventh aspect of the present invention is: in the first or second aspect, the lateral dual gate device of the present invention is used as a high voltage device of an SOI high voltage integrated circuit, in a high voltage integrated circuit, a high voltage device and a low voltage
  • the trench gate structure of the lateral double gate device of the present invention is directly used as an isolation trench for isolating the high and low voltage regions, or a trench formed simultaneously by the same process as the trench gate is used as the isolation trench.
  • the trench gate structure itself has a perfect isolation effect, thereby reducing the manufacturing cost and process difficulty of the integrated circuit.
  • a trench formed at the same time as the same process as the trench gate is used as the isolation trench, whereby the SOI high voltage integrated circuit can be manufactured without increasing the process difficulty.
  • a twelfth aspect of the present invention is: an integrated circuit, wherein the active device as the integrated circuit includes the device according to each of the above aspects.
  • the thirteenth aspect of the present invention is:
  • the integrated circuit is a power integrated circuit or a radio frequency power integrated circuit.
  • the structure of the present invention has a double gate to form a double conductive channel, in a forward conduction state, a current flowing through the planar gate channel region passes through an active layer above the buried layer of the semiconductor, flowing through the trench gate The current in the channel region passes through the active layer below the buried layer of the semiconductor, shortening the current flow path, and the extended trench gate further increases the effective conductive region.
  • the on-resistance and on-state power consumption of the device are reduced; at the same current, the area of the chip is saved.
  • the structure of the present invention has a reduced on-resistance of about 40% compared to the SOI LDMOS structure having a double RESURF structure.
  • the surface electric field peak of the PN junction formed in the body/active region can be effectively reduced, thereby improving the lateral breakdown voltage. Therefore, for the same device lateral dimension, the device withstand voltage can be improved; or for the same withstand voltage, the drift region and device length can be reduced, thereby reducing on-resistance and power consumption, which can reduce chip cost and miniaturization. Claim.
  • the trench gate structure also serves as a dielectric isolation trench, which not only saves the area of the dielectric isolation trench, but also simplifies the power integrated circuit process and saves cost.
  • FIG. 1 is a schematic view showing a sectional structure of a conventional SOI high voltage integrated circuit.
  • FIG. 2 is a schematic view showing the structure of an SOI LDMOS having a double RESURF structure.
  • 3 is a cross-sectional view showing the structure of a single-slot gate SOI high voltage LDMOS having a buried layer.
  • Fig. 4 (a) is a cross-sectional view showing the cell structure of the N-channel double-gate SOI lateral MOSFET device in which the P-type semiconductor buried layer and the body region of the present invention are in contact.
  • Fig. 4 (b) is a cross-sectional view showing the cell structure of the N-channel double-gate SOI lateral MOSFET device in which the P-type semiconductor buried layer and the body region of the present invention are not in contact.
  • Figure 5 is a cross-sectional view showing the cell structure of a P-channel double-gate SOI lateral MOSFET device having an N-type semiconductor buried layer of the present invention.
  • Figure 6 is a layout diagram showing the cell structure of an SOI lateral MOSFET device having an axisymmetric structure of the present invention.
  • Figure 7 is a layout diagram showing the cell structure of an SOI lateral MOSFET device having a plane symmetrical structure of the present invention.
  • Fig. 8 is a view showing the dependence of the breakdown voltage of three kinds of N-channel SOI LDMOS on the position of the semiconductor P buried layer.
  • Fig. 9 is a view showing a forward current-voltage characteristic curve of an N-channel SOI LDMOS of several structures.
  • Fig. 10 is a schematic diagram showing a comparison of two-dimensional current line distributions.
  • Figure 11 is a diagram showing the isolation of a high voltage SOI lateral MOSFET device from a low voltage circuit in the case where the present invention is used in an integrated circuit.
  • the technical solution of the present invention is to make full use of the trench gate, the planar gate and the semiconductor buried layer, that is, to utilize the double gate structure to cooperate with the semiconductor buried layer, and comprehensively improve and improve the electrical performance of the SOI lateral MOSFET device.
  • the SOI lateral MOSFET device of the present invention is sometimes simply referred to as a device.
  • Fig. 4 (a) is a cross-sectional view showing the cell structure of the N-channel double-gate SOI lateral MOSFET device in which the P-type semiconductor buried layer 4 of the present invention is in contact with the body region 9.
  • a substrate layer 1, a dielectric buried layer 2, and an active layer 3 are laminated in this order from bottom to top, and the active layer 3 has a surface on the active layer 3, respectively.
  • the active layer 3 between the body region 9 and the drain region 12 is a drift region, the conductivity type thereof is opposite to the conductivity type of the body region 9 , and the active layer 3 is provided with a semiconductor buried layer below the surface thereof 4.
  • the semiconductor buried layer 4 and the body region 9 have the same conductivity type.
  • the upper and lower relative positions of the semiconductor buried layer 4 and the body region 9 are not particularly limited, and may be located below the body region 9, or may be included in the longitudinal direction of the body region 9.
  • a trench gate structure 8 and a planar gate structure 8' are provided.
  • the trench gate structure 8 is composed of a trench gate dielectric 6 and a conductive material 5 surrounded by the trench gate structure 8 in contact with the body region 9, and
  • the semiconductor buried layer 4 is also in contact, and the trench gate structure 8 extends longitudinally from the surface of the active layer 3 to the dielectric buried layer 2, and the planar gate structure 8' is formed above the body region 9, from the planar gate dielectric 6' and above
  • the conductive material 5' is composed of a conductive material 5' which is polysilicon or/and metal.
  • the device structure of this example has a double gate structure (slot gate structure 8 and planar gate structure 8'), and the double gate electrode, that is, the trench gate electrode G and the planar gate electrode G' are electrically connected.
  • the semiconductor buried layer 4 is in contact with the body region 9. Compared with the structure shown in Fig. 3, the withstand voltage of the device in this example is improved and is insensitive to the position of the semiconductor buried layer 4.
  • Fig. 4 may be configured such that the semiconductor buried layer 4 is in contact with the body region 9, but is not in contact with the trench gate structure 8.
  • FIG. 4(b) is a cross-sectional view showing the cell structure of the N-channel double-gate SOI lateral MOSFET device in which the P-type semiconductor buried layer 4 of the present invention and the body region 9 are not in contact. As shown in FIG. 4(b), it differs from FIG. 4) only in that the semiconductor buried layer 4 is not in contact with the body region 9 and the trench gate structure 8. Due to the double gate structure, the effective conductive region can be increased, the current flow path can be shortened, and the on-resistance can be reduced by more than 30%, thereby reducing the static power consumption of the device. With the knot shown in Figure 3 Compared with the structure, the withstand voltage of the device is improved. Further, FIG. 4(b) may be configured such that the semiconductor buried layer 4 is not in contact with the body region 9, but is in contact with the trench gate structure 8.
  • Figure 5 is a cross-sectional view showing the cell structure of a P-channel double-gate SOI lateral MOSFET device having an N-type semiconductor buried layer 4 of the present invention. As shown in FIG. 5, it differs from FIG. 4(a) only in the active layer 3, the semiconductor buried layer 4, the source regions l la, l ib, the drain region 12, the body region 9 and the device of this example.
  • the material conductivity type of the body contact region 10 is opposite to that of the corresponding region of the N-channel double-gate SOI lateral MOSFET device, and the same technical effects as in Embodiment 1 can be obtained. That is, the present invention has a double-gate MOS controlled lateral SOI device with a semiconductor buried layer, which can be used for both N-channel devices and P-channel devices.
  • the top view of the device is a symmetrical structure
  • the drain region 12 is located at the center of the device
  • the drain region 12 is outwardly a semiconductor buried layer 4, a body region 9, a source region l la, a body contact region 10, and a source region.
  • the lb and trench gate structure 8, the trench gate structure 8 is located on the periphery of the device.
  • Fig. 6 is a view showing the layout of a cell layout of an SOI lateral MOSFET device having an axisymmetric structure of the present invention, i.e., an xz plan view, wherein ⁇ ' in the X direction, perpendicular to the longitudinal direction of the paper, is the y direction.
  • the layout of the layout is exemplified by the structure of Fig. 4a.
  • Fig. 6 shows an axisymmetric structure taking a circular shape in a plan view as an example.
  • the drain electrode D is located at the center of the device.
  • the device has a central axis of the drain region 12, i.e., the y-axis, as the axis of symmetry.
  • the planar gate electrode G' is taken out and electrically connected to the trench gate electrode G in the trench gate structure 8 at the outermost periphery of the device to constitute the gate electrode G? of the device.
  • the trench gate structure 8 is located on the outermost side of the device to provide isolation of the high and low voltage cells in the integrated circuit.
  • the top view of the drain region 12 may be a circular or regular polygon other than an equilateral triangle, matching the semiconductor ii layer 4, the source region la, the body contact region 10, the source
  • the top view of the region l ib and the trench gate structure 8 is a circular annulus or a regular polygonal annulus other than the equilateral triangular annulus.
  • the body region 9, the source region l la, the body contact region 10, the source region 1 ib, and the trench gate structure 8 are circular ring-shaped devices.
  • the top view pattern of the drain region 12 of the same device matches the top view of the periphery such as the trench gate structure 8 and the semiconductor buried layer 4, such as the drain region 12 being a regular hexagon, the semiconductor buried layer 4, the body region 9, and the source region
  • the la, body contact region 10, source region l ib and trench gate structure 8 are also regular hexagonal annulus.
  • Figure 7 is a diagram showing the cell layout layout of an SOI lateral MOSFET device having a plane symmetrical structure of the present invention. As shown in Fig.
  • the figure is an xz plan view, in which ⁇ ' is in the X direction, ⁇ ' is in the ⁇ direction, and perpendicular to the longitudinal direction of the paper is the y direction.
  • the symmetry plane of the device is the yz plane of the ⁇ '.
  • the figure includes a layout of the semiconductor buried layer 4 and the trench gate structure 8, and also has a layout of metal electrodes: a trench gate electrode 0, a planar gate electrode G', a gate electrode G? (a trench gate electrode G and a planar gate electrode G'
  • the electrical connection is made up of the same electrode G ⁇ connected to each other) source electrode S and drain electrode 0.
  • the electrically active source regions l la, l ib Fig. 6, Fig.
  • the top view pattern is strip-shaped.
  • the drain region 12 is located at the center of the device, and the drain electrode D is structured on both sides.
  • the left and right symmetry, the drain region 12 is evenly divided and the plane of the trench gate structure 8 is not symmetrical, and the semiconductor buried layer 4, the planar gate electrode G', the source electrode S, and the trench gate structure 8 are sequentially arranged from the drain region 12,
  • the trench gate structure 8 is located on the outermost side of the device to terminate the high potential (for N-channel devices) from the drain region 12 within the trench gate structure 8, thereby achieving isolation of the high and low voltage cells in the integrated circuit.
  • the planar gate structure 8' is led out by the planar gate electrode G', and the conductive material 5 in the trench gate structure 8 is taken out by the trench gate electrode G, and their common terminals are the gate electrodes of the device.
  • the gate electrode G ⁇ and the source electrode S have an interdigitated structure. Further, other plane symmetrical structures than those shown in FIG. 7 may be used.
  • the SOI lateral device of the present invention can be used for MOS controlled lateral power devices, and is most suitable for active devices for integrated circuits, particularly for power integrated circuits or RF power integrated circuits.
  • the device described in the above embodiments of the present invention can be made of Si, SiC, SiGe, GaAs or GaN as the material of the active layer 3, and the materials are mature and convenient, and can satisfy different devices or circuits. Performance requirements.
  • the conductive materials 5 and 5' are preferably polycrystalline silicon.
  • Trench gate and planar gate dielectric medium 6 selected 6 ' may be employed Si0 2, or Si0 2 is higher than the dielectric constant and the dielectric breakdown field threshold equal to or higher Si0 2: The Si 3 N 4, A1N, A1 2 0 3 or Hf ⁇ 2, etc.
  • the trench gate dielectric 6 adopts a higher dielectric constant, which can enhance the gate voltage control capability of the gate charge and increase the transconductance.
  • the trench gate dielectric 6 can be made thicker to reduce the tunnel current and avoid Tunneling effect, enhancement device or Chip stability and reliability.
  • the material of the dielectric buried layer 2 it may be Si0 2 , or a medium having a dielectric constant lower than Si0 2 and a critical breakdown electric field higher than three times the critical breakdown electric field of Si, such as SiOF or SiCOF.
  • the dielectric of the dielectric buried layer 2 can be enhanced by using a medium having a higher dielectric constant, which is advantageous for improving the withstand voltage of the device.
  • the technical solution of the present invention has almost no requirement for the substrate material, and may be an n-type or p-type semiconductor material, or even an insulating dielectric material, or the same dielectric material as the dielectric buried layer 2.
  • Fig. 8 is a view showing the dependence of the breakdown voltage of three kinds of N-channel SOI LDMOS on the buried position of the semiconductor P.
  • the abscissa D p is the distance of the P buried layer from the inner boundary of the trench gate dielectric (the drain region is the center of the device); the three devices compared include: a planar gate SOI LDMOS with a buried layer; a buried layer P
  • the trench gate SOI LDMOS is shown in Figure 3.
  • These two types of SOI LDMOS are single-gate structures; the dual-gate SOI LDMOS is the SOI LDMOS with P-semiconductor and double-gate structure of the present invention, as shown in Fig. 4(a).
  • the withstand voltage of the planar gate SOI LDMOS with P buried layer is sensitive to the buried position of the semiconductor, which is disadvantageous for the reliability of the device; the trench gate SOI LDMOS structure with the buried layer of the semiconductor P
  • the problem of the withstand voltage sensitivity to the buried layer of the semiconductor is solved, the position of the buried layer of the semiconductor is varied within a wide range, and the withstand voltage of the device is substantially unchanged; the double-gate SOI LDMOS structure having the semiconductor buried layer in the present invention, from the figure It can be seen that the problem of the sensitivity of the withstand voltage to the buried position of the semiconductor is solved.
  • Fig. 9 is a view showing a forward current-voltage characteristic curve of an N-channel SOI LDMOS of several structures.
  • a trench gate SOI LDMOS structure having a P buried layer is shown in FIG. 3;
  • a single RESURF planar gate SOI LDMOS is a conventional N-channel planar gate SOI LDMOS;
  • a double-gate SOI LDMOS having a P buried layer is the present invention having The P-buried N-channel double-gate SOI LDMOS is shown in Figure 4 (a); the double RESURF planar gate SOI LDMOS structure is shown in Figure 2. It can be seen from the figure that the double-gate structure with semiconductor buried layer of the present invention has the lowest forward voltage drop at a certain current density, and the single-slot gate SOI LDMOS with semiconductor buried layer
  • the SOI LDMOS structure is reduced by 49.3%, which is 64.2% lower than that of the single RESURF SOI LDMOS structure.
  • the specific on-resistance of the double gate structure of the semiconductor buried layer of the present invention can be greatly reduced, and the first is due to the buried of P The existence of the layer makes the optimized concentration of the drift region greatly improved.
  • the current path is shorter, and the effective conductive area of the active layer is expanded, so that the current distribution is relatively uniform, thereby reducing the current.
  • the specific on-resistance of the device due to the double gate structure, the current path is shorter, and the effective conductive area of the active layer is expanded, so that the current distribution is relatively uniform, thereby reducing the current.
  • Fig. 10 is a schematic diagram showing the comparison of the two-dimensional current line distribution (half cell), and the current intensity difference of two adjacent current lines is 4 ⁇ 1 ( ⁇ 7 ⁇ / ⁇ ⁇ .
  • Fig. 10 (a) indicates a single RESURF planar gate SOI LDMOS
  • Fig. 10(b) shows a double RESURF planar gate SOI LDMOS
  • Fig. 10(c) shows a single trench gate SOI device with a semiconductor buried layer
  • Fig. 10(d) shows a semiconductor buried layer of the present invention Double-gate SOI device.
  • the current distribution of the double-gate SOI device with semiconductor buried layer is the most uniform, and the current density is the highest under the same forward voltage drop; the semiconductor buried single-slot SOI device is the second. Both of them are superior to the other two structures. Since the current distribution is relatively uniform, the on-resistance of the forward conduction is small, and the temperature characteristics can be better. In summary, the present invention improves the withstand voltage of the device and solves the problem.
  • the device has a lower specific on-resistance;
  • the trench gate medium extending longitudinally to the upper surface of the dielectric buried layer terminates the high potential of the drain region from the center of the device within the trench gate, the influence of the high potential on the low voltage circuit other than the trench gate can be avoided.
  • Also used as a dielectric isolation trench which not only saves the area of the dielectric isolation trench, but also does not require a special process flow to form a dielectric isolation trench like a conventional SOI high voltage integrated circuit, which simplifies the power integrated circuit process and saves costs.
  • Fig. 11 is a view showing the isolation of a high voltage device from a low voltage circuit in the case where the present invention is used in an integrated circuit.
  • a special isolation trench such as the isolation trench 30 in FIG. 1
  • the trench gate structure 8 of the present invention is provided with the surrounding trench.
  • the shallow P+ region 13 grounded to the outer boundary of the gate can effectively avoid the influence of the switching transient of the gate on the low voltage circuit region, thereby having a perfect isolation function, thereby reducing the manufacturing cost and process difficulty of the integrated circuit.

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Abstract

A silicon-on-insulator (SOI) lateral MOSFET device and the integrated circuit thereof are provided. In said device, an active layer (3) includes a body region (9) and a drain region (12) which are located on the surface of the active layer (3) respectively and are separated from each other, and also a planar gate channel region (14'), a source region (11a), a body contact region (10) and a source region (11b) which are located on the surface of the body region (9) and are set in sequence from the side adjacent to the drain region (12). The active layer (3) located between the body region (9) and the drain region (12) is a drift region, wherein the drift region and the body region (9) have opposite conduction types. A semiconductor buried layer (4) is set beneath the surface of the active layer (3), wherein the semiconductor buried layer (4) and the body region (9) have the same conduction type. Said device has a trench gate structure (8) and a planar gate structure (8'), wherein the trench gate structure (8) contacts with the body region (9) and longitudinally extends from the surface of the active layer (3) to a dielectric buried layer (2), and the planar gate structure (8') is formed above the body region (9). Said device has the advantages of high withstand voltage, low specific on-resistance, low power consumption, low cost, and easy miniaturization and integration.

Description

SOI横向 MOSFET器件和集成电路 技术领域  SOI Transverse MOSFET Devices and Integrated Circuits
本发明涉及半导体功率器件和集成电路，特别是涉及一种用于功率集 成电路或射频功率集成电路的 SOI ( Semiconductor On Insulator, 绝缘衬 底上半导体） 横向 MOSFET ( Metal-Oxide-Semiconductor Field-Effect- Transistor,金属 -氧化物-半导体场效应晶体管）器件和具备其的集成电路。 背景技术  The present invention relates to a semiconductor power device and an integrated circuit, and more particularly to an SOI (Semiconductor On Insulator) lateral MOSFET (Metal-Oxide-Semiconductor Field-Effect- for a power integrated circuit or a radio frequency power integrated circuit) Transistor, metal-oxide-semiconductor field effect transistor device and integrated circuit with the same. Background technique
SOI是在顶层半导体（称为有源层）和衬底层（可以为半导体或绝缘 介质）之间引入介质埋层， 将半导体器件或电路制作在有源层中。 集成电 路中高压器件、 低压电路之间通常采用隔离槽 30进行隔离， 有源层 3与 衬底层 1之间则由介质埋层 2进行隔离 （如图 1所示）。 因此， 与体硅技 术相比， SOI技术具有寄生效应小、 泄漏电流小、 集成度高、 抗辐射能力 强以及无可控硅自锁效应等优点， 在高速、 高温、 低功耗以及抗辐射等领 域得到广泛关注和应用。  The SOI is to introduce a dielectric buried layer between a top-level semiconductor (referred to as an active layer) and a substrate layer (which may be a semiconductor or an insulating medium), and a semiconductor device or circuit is fabricated in the active layer. In the integrated circuit, the isolation trench 30 is usually used for isolation between the high voltage device and the low voltage circuit, and the active layer 3 and the substrate layer 1 are separated by the dielectric buried layer 2 (as shown in Fig. 1). Therefore, compared with bulk silicon technology, SOI technology has the advantages of small parasitic effect, small leakage current, high integration, strong radiation resistance and self-locking effect of thyristor, high speed, high temperature, low power consumption and radiation resistance. Such fields have received extensive attention and application.
SOI功率集成电路技术的关键是实现高耐压、低功耗以及高压单元和 低压单元之间的有效隔离。 SOI 横向器件， 如 LDMOSFET ( Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor , 横向双 扩散金属-氧化物-半导体场效应晶体管） 因其便于集成和相对较^ (氐的导通 电阻而成为 SOI功率集成电路的核心器件， 在等离子显示屏、 马达驱动、 汽车电子、 便携式电源管理产品以及个人电脑等应用中倍受青睐。 同时， 较之于 VDMOSFET ( Vertical Double-diffused Metal-Oxide- Semiconductor Field-Effect-Transistor, 垂直双扩散金属 -氧化物-半导体场效应晶体管） , 横向 MOSFET更高的开关速度， 使其还在射频领域应用广泛。  The key to SOI power integrated circuit technology is to achieve high withstand voltage, low power consumption, and effective isolation between the high voltage unit and the low voltage unit. SOI lateral devices, such as LDMOSFET (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor), because of their ease of integration and relatively low on-resistance Becoming a core component of SOI power ICs, it is favored in applications such as plasma display panels, motor drives, automotive electronics, portable power management products, and personal computers. Also, compared to VDMOSFET (Vertical Double-diffused Metal-Oxide- Semiconductor Field-Effect-Transistor, vertical double-diffused metal-oxide-semiconductor field effect transistor), the higher switching speed of the lateral MOSFET, makes it widely used in the RF field.
对于常规 LDMOSFET器件而言， 漂移区长度随器件耐压的升高单调 增加， 这不仅使芯片面积增加、成本增大、 不利于小型化， 更为严重的是， 器件的导通电阻随器件耐压的增加而增大（导通电阻与器件耐压的关系式 可以表达为：
Figure imgf000003_0001
BV 2 3 , 其中 BV为器件耐压， Ron为导通电阻） ， 导 通电阻的增加导致开态功耗增加， 且器件开关速度也随之降低。 For conventional LDMOSFET devices, the length of the drift region increases monotonically with the increase of the withstand voltage of the device, which not only increases the chip area, increases the cost, and is not conducive to miniaturization. More seriously, the on-resistance of the device is resistant to the device. The increase in pressure increases (the relationship between on-resistance and device withstand voltage can be expressed as:
Figure imgf000003_0001
BV 2 3 , where BV is the device withstand voltage, Ron is the on-resistance), the increase in on-resistance leads to an increase in the on-state power consumption, and the device switching speed also decreases.
槽栅结构的器件有如下优点： 首先， 可以增加封装密度， 从而提高沟 道密度和电流密度；其次，槽栅结构器件的沟道长度不受光刻工艺的限制， 沟道可以做得较短， 从而降低导通电阻（以上两点均会增加槽栅结构器件 的电流承受能力 ） ； 第三， 槽栅 MOSFET 能够避免 JFET(Junction Field-Effect-Transistor, 结型场效应晶体管）效应和 snapback (二次击穿） 效应。 但是， 对于高压器件来说， 由于漂移区电阻占器件导通电阻的主要 部分， 所以槽栅结构并没有解决硅极限的问题。 The device of the trench gate structure has the following advantages: First, the package density can be increased to increase the channel density and current density; secondly, the channel length of the trench gate structure device is not limited by the photolithography process, and the channel can be made shorter , thereby reducing the on-resistance (the above two points will increase the trench gate structure device The current carrying capacity); Third, the trench gate MOSFET can avoid the JFET (Junction Field-Effect-Transistor) effect and the snapback (secondary breakdown) effect. However, for high voltage devices, since the drift region resistance accounts for a major portion of the device's on-resistance, the trench gate structure does not solve the silicon limit problem.
Y. S. Huang , B. J. Baliga 等人在 1990 年首次提出将 RESU F Y. S. Huang, B. J. Baliga et al. first proposed RESU F in 1990.
( reduced surface field, 降低表面电场）理论应用到 SOI 器件上， 可使器 件在反偏时漂移区全部耗尽， 并把击穿点从表面转移到体内， 从而获得较 高的击穿电压。 这在一定程度上緩解了横向高压器件的硅极限的问题。 The reduced surface field is applied to the SOI device, which can completely deplete the drift region of the device during reverse bias and transfer the breakdown point from the surface to the body to obtain a higher breakdown voltage. This alleviates the problem of the silicon limit of the lateral high voltage device to some extent.
R. P. Zingg 等人将双 RESURF ( Double RESURF )技术应用于 SOI 高压器件， 如图 2所示， 即在漂移区表面插入导电类型相反的降场层来改 善表面电场， 获得击穿电压和导通电阻的良好折衷。 这种结构相对于单 RESURF ( single RESURF ) ， 漂移区的优化浓度可以提高一倍， 从而降 低了比导通电阻。  RP Zingg et al. applied dual RESURF (Double RESURF) technology to SOI high voltage devices, as shown in Figure 2, by inserting a lower-field layer of opposite conductivity type on the surface of the drift region to improve the surface electric field and obtain breakdown voltage and on-resistance. a good compromise. This structure can double the optimized concentration of the drift region relative to a single RESURF (single RESURF), thereby reducing the specific on-resistance.
2001年， D. R. Disney 等人在文献（【A new 800V lateral MOSFET with dual conduction paths] ISPSD, 2001 )中提出了在体硅材料上的具有双导电 通道的 LDMOS (也可叫做三 RESURF ( triple RESURF ) ) , 这种结构利 用埋 ρ层的调制作用，使漂移区的最优化浓度相对于双 RESURF LDMOS 提高了约 50%, 从而其比导通电阻相对于双 RESURF LDMOS下降大约 33%。  In 2001, DR Disney et al. ([A new 800V lateral MOSFET with dual conduction paths] ISPSD, 2001) proposed LDMOS with double conductive channels on bulk silicon materials (also known as triple RESURF). This structure utilizes the modulation of the buried layer to increase the optimum concentration of the drift region by approximately 50% relative to the double RESURF LDMOS, thereby reducing the specific on-resistance by approximately 33% relative to the dual RESURF LDMOS.
由于 SOI的特殊性， 将体硅结构的双导电通道结构用在于 SOI上的 电场分布和优化规律将有所不同， 且在常规平面栅结构中， 由于半导体埋 层、 栅极场板以及 PN结 （体区和漂移区的结） 的相互作用， 使器件的耐 压对半导体埋层的位置非常敏感， 工艺重复性很差 （如图 8所示） 。  Due to the particularity of SOI, the electric field distribution and optimization law of the dual-conductor channel structure of the bulk silicon structure used on the SOI will be different, and in the conventional planar gate structure, due to the semiconductor buried layer, the gate field plate, and the PN junction The interaction between the body region and the junction of the drift region makes the device's withstand voltage very sensitive to the position of the semiconductor buried layer, and the process repeatability is poor (as shown in Figure 8).
发明内容 Summary of the invention
本发明是为了解决上述问题而做出的， 其目的在于： 提供一种 SOI 横向 MOSFET器件和具备其的集成电路， 所述器件能够降低比导通电阻 和功耗，能够提高 LDMOSFET耐压，能够降低器件横向尺寸和芯片面积， 而且能够增大工艺容差。  The present invention has been made to solve the above problems, and an object thereof is to provide an SOI lateral MOSFET device and an integrated circuit having the same, which can reduce the specific on-resistance and power consumption, and can improve the withstand voltage of the LDMOSFET. Reduces device lateral dimensions and chip area, and increases process tolerance.
本发明为了达到上述目的的至少之一， 其第一方案是： 一种 SOI横 向 MOSFET器件， 其自下而上依次层叠有衬底层、 介质埋层和有源层， 其特征在于， 所述有源层包括： 分别位于所述有源层的表面并且相互分离 的体区和漏区、以及位于所述体区的表面并且从靠近所述漏区的一侧起按 顺序设置的平面栅沟道区、 第一源区、 体接触区和第二源区； 位于所述体 区和所述漏区之间的所述有源层为漂移区，所述漂移区和所述体区的导电 类型相反； 所述有源层在其表面以下设置有半导体埋层， 所述半导体埋层 和所述体区的导电类型相同； 所述器件具有槽栅结构和平面栅结构， 所迷 槽栅结构与所述体区接触，并且从所述有源层的表面纵向延伸至所述介质 埋层， 所述平面栅结构形成于所述体区的上方， 所述槽栅结构由槽栅介质 及其包围的导电材料构成，所述平面栅结构由平面栅介质及其上面的导电 材料构成。 In order to achieve at least one of the above objects, the first aspect of the present invention is: an SOI lateral MOSFET device in which a substrate layer, a dielectric buried layer, and an active layer are stacked in this order from bottom to top, wherein The source layer includes: body and drain regions respectively located on surfaces of the active layer and separated from each other, and a surface located on the body region and pressed from a side close to the drain region a planar gate channel region, a first source region, a body contact region, and a second source region; the active layer between the body region and the drain region is a drift region, and the drift region and The body region has opposite conductivity types; the active layer is provided with a semiconductor buried layer below the surface thereof, and the semiconductor buried layer and the body region have the same conductivity type; the device has a trench gate structure and a planar gate structure a trench gate structure in contact with the body region and extending longitudinally from a surface of the active layer to the dielectric buried layer, the planar gate structure being formed above the body region, the trench gate structure It consists of a trench gate dielectric and a conductive material surrounded by it, the planar gate structure being composed of a planar gate dielectric and a conductive material thereon.
根据本发明的第一方案， 所述的槽栅结构和平面栅结构形成双栅结 构， 因而形成双导电沟道： 在所述平面栅结构之下、 体区表面形成平面栅 沟道区， 在与所述槽栅结构接触的体区或 /和半导体埋层界面形成槽栅沟 道区， 因而降低导通电阻； 纵向延伸的槽栅结构增大了有效导电面积， 从 而降低导通电阻；所述半导体埋层提高漂移区的优化浓度进而降低比导通 电阻， 而且减小了器件击穿电压对半导体埋层位置的敏感性； 另外， 将所 述器件用于功率集成电路，器件的槽栅结构同时可用作高压区域与低压区 域之间的隔离槽， 由此， 减少了 SOI高压集成电路的隔离工艺步骤和工艺 成本， 并且槽栅结构减小了 JFET效应。 本发明与具有双 RESURF结构的 SOI LDMOS结构相比， 导通电阻下降约 40%, 且能使耐压上升。  According to the first aspect of the present invention, the trench gate structure and the planar gate structure form a double gate structure, thereby forming a double conductive channel: under the planar gate structure, a planar gate channel region is formed on the surface of the body region, a body region or/and a semiconductor buried layer interface in contact with the trench gate structure forms a trench gate channel region, thereby reducing on-resistance; a vertically extending trench gate structure increases an effective conductive area, thereby reducing on-resistance; The semiconductor buried layer increases the optimized concentration of the drift region to lower the specific on-resistance, and reduces the sensitivity of the device breakdown voltage to the buried position of the semiconductor; in addition, the device is used for a power integrated circuit, a trench of the device The structure can also be used as an isolation trench between the high voltage region and the low voltage region, thereby reducing the isolation process steps and process cost of the SOI high voltage integrated circuit, and the trench gate structure reduces the JFET effect. Compared with the SOI LDMOS structure having the double RESURF structure, the on-resistance is reduced by about 40%, and the withstand voltage can be increased.
另外， 本发明的第二方案是： 在所述第一方案中， 所述半导体埋层与 所述体区接触、 或所述半导体埋层与所述体区不接触。  Further, in a second aspect of the present invention, in the first aspect, the semiconductor buried layer is in contact with the body region, or the semiconductor buried layer is not in contact with the body region.
另外， 本发明的第三方案是： 在所述第一或第二方案中， 所述器件的 俯视图为对称结构， 所述漏区位于所述器件的中心， 由所述漏区向外依次 是所述半导体埋层、 所述体区、 所述第一源区、 所述体接触区、 所述第二 源区和所述槽栅结构， 所述槽栅结构位于所述器件的外围。  In addition, the third aspect of the present invention is: in the first or second aspect, the top view of the device is a symmetrical structure, the drain region is located at the center of the device, and the drain region is outwardly The semiconductor buried layer, the body region, the first source region, the body contact region, the second source region, and the trench gate structure, the trench gate structure is located at a periphery of the device.
另外， 本发明的第四方案是： 在所述第三方案中， 所述器件为轴对称 结构， 所述漏区的中心轴线为所述器件的对称轴。  Further, a fourth aspect of the present invention is: In the third aspect, the device is an axisymmetric structure, and a central axis of the drain region is an axis of symmetry of the device.
另外，本发明的第五方案是：在所述第四方案中，所述器件在俯视时， 所述漏区为圆形， 所述半导体埋层、 所述体区、 所述第一源区、 所述体接 触区、 所述第二源区和所述槽栅结构为圆形环带状。  According to a fifth aspect of the present invention, in the fourth aspect, the device has a circular shape in a plan view, the semiconductor buried layer, the body region, and the first source region. The body contact region, the second source region, and the trench gate structure are in the shape of a circular ring.
另外， 本发明的第六方案是： 在所述第三方案中， 所述器件为面对称  In addition, a sixth aspect of the present invention is: in the third aspect, the device is plane symmetrical
A根据本发明 '的第三至 ^六方案， 所述槽栅结构位于所述器件的外围， 将源于器件中心漏区的高电位终止于槽栅之内，便于利用槽栅结构实现高 压器件与槽栅之外的低压控制电路间的隔离。 特别是， 根据本发明的第五 方案， 具有最佳的对称型， 且减弱了曲率效应， 因而耐压最高， 并节省芯 片面积。 A according to the third to sixth aspects of the invention, the trench gate structure is located on the periphery of the device, The high potential from the center drain region of the device is terminated within the trench gate, facilitating isolation between the high voltage device and the low voltage control circuit outside the trench gate using the trench gate structure. In particular, according to the fifth aspect of the present invention, the symmetrical shape is optimal, and the curvature effect is attenuated, so that the withstand voltage is the highest and the chip area is saved.
另外， 本发明的第七方案是： 在所述第一或第二方案中， 所述器件用 于 MOS控制的半导体器件。 例如可为 IGBT、 LDMOS。  Further, a seventh aspect of the present invention is: In the first or second aspect, the device is used for a MOS controlled semiconductor device. For example, it can be IGBT or LDMOS.
另外， 本发明的第八方案是： 在所述第一或第二方案中， 所述有源层 的材料包括 Si、 SiC、 SiGe、 GaAs或 GaN。  Further, an eighth aspect of the present invention is: In the first or second aspect, the material of the active layer comprises Si, SiC, SiGe, GaAs or GaN.
根据本发明的第八方案，构成有源层的这些材料技术成熟，取材方便， 可以满足不同器件或电路性能要求。  According to the eighth aspect of the present invention, the materials constituting the active layer are mature in technology and convenient in drawing, and can satisfy different device or circuit performance requirements.
另外， 本发明的第九方案是： 在所述第一或第二方案中， 所述介质埋 层的材料为 Si02, 或者为包括 SiOF或 SiCOF的介电系数低于 Si02且临 界击穿电场高于 Si临界击穿电场的 3倍的介质。 In addition, the ninth aspect of the present invention is: in the first or second aspect, the material of the dielectric buried layer is SiO 2 , or the dielectric constant including SiOF or SiCOF is lower than SiO 2 and the critical breakdown The electric field is higher than three times the dielectric of the Si critical breakdown electric field.
根据本发明的第九方案， 介质埋层采用介电系数较低的介质， 可以增 强介质埋层的电场， 有利于器件耐压的提高。  According to the ninth aspect of the present invention, the medium buried layer is made of a medium having a low dielectric constant, which can enhance the electric field of the buried layer of the medium, and is favorable for improving the withstand voltage of the device.
另外， 本发明的第十方案是： 在所述第一或第二方案中， 所述槽栅介 质为 Si02, 或者为包括 Si3N4、 A1203、 A1N或 Hf02的介电系数高于 Si02 且临界击穿电场与 Si02相当或更高的介质。 In addition, the tenth aspect of the present invention is: in the first or second aspect, the trench gate dielectric is Si0 2 , or is a dielectric including Si 3 N 4 , A1 2 0 3 , A1N or Hf0 2 coefficient is higher than the critical breakdown field Si0 2 and Si0 2 and comparable to or higher media.
根据本发明的第十方案，高介电系数的槽栅介质可以增强栅电压对栅 电荷的控制能力 ， 增大跨导， 或者， 在相同 的栅结构 MIS ( Metal-Insulator-Semiconductor，栅电极-栅介质 -栅介质下的半导体形成 MIS结构） 电容下， 可以将槽栅介质做得更厚， 减小隧道电流， 避免隧穿 效应， 增强器件或芯片的稳定性与可靠性。  According to the tenth aspect of the present invention, the high dielectric constant trench gate dielectric can enhance the gate voltage control capability of the gate charge, increase the transconductance, or, in the same gate structure MIS (Metal-Insulator-Semiconductor, gate electrode - The semiconductor under the gate dielectric-gate dielectric forms the MIS structure. Under the capacitor, the trench gate dielectric can be made thicker, the tunnel current can be reduced, the tunneling effect can be avoided, and the stability and reliability of the device or chip can be enhanced.
另外， 本发明的第十一方案是： 在所述第一或第二方案中， 将本发明 的横向双栅器件用作 SOI高压集成电路的高压器件， 在高压集成电路中， 高压器件与低压控制电路之间隔离时，直接采用本发明的横向双栅器件的 槽栅结构作为隔离高、 低压间的隔离槽， 或者将利用与制作槽栅相同的工 艺同时形成的槽作为隔离槽。  In addition, an eleventh aspect of the present invention is: in the first or second aspect, the lateral dual gate device of the present invention is used as a high voltage device of an SOI high voltage integrated circuit, in a high voltage integrated circuit, a high voltage device and a low voltage When the control circuits are isolated from each other, the trench gate structure of the lateral double gate device of the present invention is directly used as an isolation trench for isolating the high and low voltage regions, or a trench formed simultaneously by the same process as the trench gate is used as the isolation trench.
根据本发明的第十一方案，槽栅结构本身就具有完善的隔离作用， 由 此降低了集成电路的制造成本和工艺难度。 此外， 将利用与制作槽栅相同 的工艺同时形成的槽作为隔离槽， 由此能够不增加其工艺难度地制造 SOI 高压集成电路。 另外， 本发明的第十二方案是： 一种集成电路， 其中， 作为所述集成 电路的有源器件， 包括根据上述各方案所述的器件。 According to the eleventh aspect of the present invention, the trench gate structure itself has a perfect isolation effect, thereby reducing the manufacturing cost and process difficulty of the integrated circuit. Further, a trench formed at the same time as the same process as the trench gate is used as the isolation trench, whereby the SOI high voltage integrated circuit can be manufactured without increasing the process difficulty. Further, a twelfth aspect of the present invention is: an integrated circuit, wherein the active device as the integrated circuit includes the device according to each of the above aspects.
另外， 本发明的第十三方案是： 在所述第十二方案中， 所述集成电路 为功率集成电路或射频功率集成电路。  Further, the thirteenth aspect of the present invention is: In the twelfth aspect, the integrated circuit is a power integrated circuit or a radio frequency power integrated circuit.
本发明的有益效果是：  The beneficial effects of the invention are:
( 1 ) 由于导电类型相反的半导体埋层引入在有源层中， 形成附加的 PN结， 使得有源层的优化浓度大大提高， 从而降低了导通电阻。  (1) Since a semiconductor buried layer of opposite conductivity type is introduced in the active layer, an additional PN junction is formed, so that the optimized concentration of the active layer is greatly increased, thereby lowering the on-resistance.
( 2 ) 由于本发明的结构中具有双栅， 形成双导电沟道， 在正向导通 状态下， 流过平面栅沟道区的电流经过半导体埋层之上的有源层， 流经槽 栅沟道区的电流经过半导体埋层之下的有源层， 缩短电流流通路径， 且延 伸的槽栅进一步增大有效导电区域。因而，降低器件导通电阻和开态功耗； 在相同电流下， 节省了芯片的面积。 本发明结构与具有双 RESURF 结构 的 SOI LDMOS结构相比， 导通电阻下降约 40%。  (2) Since the structure of the present invention has a double gate to form a double conductive channel, in a forward conduction state, a current flowing through the planar gate channel region passes through an active layer above the buried layer of the semiconductor, flowing through the trench gate The current in the channel region passes through the active layer below the buried layer of the semiconductor, shortening the current flow path, and the extended trench gate further increases the effective conductive region. Thus, the on-resistance and on-state power consumption of the device are reduced; at the same current, the area of the chip is saved. The structure of the present invention has a reduced on-resistance of about 40% compared to the SOI LDMOS structure having a double RESURF structure.
( 3 )在阻断状态下， 由于半导体埋层对表面电场的调制作用， 可以 有效地降低体区 /有源区形成 PN结的表面电场峰值，从而能提高横向击穿 电压。 因此， 对于相同的器件横向尺寸， 能够提高器件耐压； 或对于相同 的耐压， 能够减小漂移区和器件长度， 从而能降低导通电阻和功耗， 可以 满足降低芯片成本和小型化的要求。  (3) In the blocking state, due to the modulation effect of the semiconductor buried layer on the surface electric field, the surface electric field peak of the PN junction formed in the body/active region can be effectively reduced, thereby improving the lateral breakdown voltage. Therefore, for the same device lateral dimension, the device withstand voltage can be improved; or for the same withstand voltage, the drift region and device length can be reduced, thereby reducing on-resistance and power consumption, which can reduce chip cost and miniaturization. Claim.
( 4 )半导体埋层和体区接触， 使耐压对半导体埋层位置的敏感性降 低， 从而降低工艺难度， 能提高成品率。  (4) The contact between the semiconductor buried layer and the body region reduces the sensitivity of the withstand voltage to the buried position of the semiconductor, thereby reducing the process difficulty and improving the yield.
( 5 ) 当本发明的器件用作集成电路中的高压器件时， 所述器件处于 漏区的高电位终止于;曹栅以内 （以 N 沟道为例）、 , 能避免高电 ^对槽栅 以外低压电路的影响。 因此， 槽栅结构同时也作为介质隔离槽， 这不仅节 省了介质隔离槽的面积， 也简化了功率集成电路工艺， 节约了成本。  (5) When the device of the present invention is used as a high voltage device in an integrated circuit, the high potential of the device in the drain region is terminated; within the gate (taking the N channel as an example), the high voltage can be avoided. The effect of low voltage circuits outside the gate. Therefore, the trench gate structure also serves as a dielectric isolation trench, which not only saves the area of the dielectric isolation trench, but also simplifies the power integrated circuit process and saves cost.
因此， 根据本发明， 能够提供一种高耐压、 低比导通电阻和低功耗、 低成本、小型化以及便于与功率集成电路集成的 SOI横向 MOSFET器件。  Therefore, according to the present invention, it is possible to provide a SOI lateral MOSFET device which is high withstand voltage, low specific on-resistance and low power consumption, low cost, miniaturization, and easy to integrate with a power integrated circuit.
本发明的上述和其他目的、特征以及优点，根据与附图关联理解的有 关本发明的如下的详细说明就会变得清楚了。  The above and other objects, features and advantages of the present invention will become apparent from
附图说明 DRAWINGS
图 1 是表示常规 SOI高压集成电路的剖面结构的示意图。  BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a sectional structure of a conventional SOI high voltage integrated circuit.
图 2 是表示具有双 RESURF结构的 SOI LDMOS的结构示意图。 图 3是表示具有埋层的单槽栅 SOI高压 LDMOS的结构剖视图。 2 is a schematic view showing the structure of an SOI LDMOS having a double RESURF structure. 3 is a cross-sectional view showing the structure of a single-slot gate SOI high voltage LDMOS having a buried layer.
图 4 ( a )是表示本发明的 P型半导体埋层和体区接触的 N沟道双栅 SOI横向 MOSFET器件元胞结构的剖视图。  Fig. 4 (a) is a cross-sectional view showing the cell structure of the N-channel double-gate SOI lateral MOSFET device in which the P-type semiconductor buried layer and the body region of the present invention are in contact.
图 4 ( b )是表示本发明的 P型半导体埋层和体区不接触的 N沟道双 栅 SOI横向 MOSFET器件元胞结构的剖视图。  Fig. 4 (b) is a cross-sectional view showing the cell structure of the N-channel double-gate SOI lateral MOSFET device in which the P-type semiconductor buried layer and the body region of the present invention are not in contact.
图 5是表示本发明的具有 N型半导体埋层的 P沟道双栅 SOI横向 MOSFET器件元胞结构的剖视图。  Figure 5 is a cross-sectional view showing the cell structure of a P-channel double-gate SOI lateral MOSFET device having an N-type semiconductor buried layer of the present invention.
图 6是表示本发明的具有轴对称结构的 SOI 横向 MOSFET器件元胞 结构的版图示意图。  Figure 6 is a layout diagram showing the cell structure of an SOI lateral MOSFET device having an axisymmetric structure of the present invention.
图 7是表示本发明的具有面对称结构的 SOI 横向 MOSFET器件元胞 结构的版图示意图。  Figure 7 is a layout diagram showing the cell structure of an SOI lateral MOSFET device having a plane symmetrical structure of the present invention.
图 8是表示 3种 N沟道 SOI LDMOS的击穿电压对半导体 P埋层位 置依赖关系的示意图。  Fig. 8 is a view showing the dependence of the breakdown voltage of three kinds of N-channel SOI LDMOS on the position of the semiconductor P buried layer.
图 9是表示几种结构的 N沟道 SOI LDMOS正向电流-电压特性曲线 的示意图。  Fig. 9 is a view showing a forward current-voltage characteristic curve of an N-channel SOI LDMOS of several structures.
图 10是表示二维电流线分布的比较的示意图。  Fig. 10 is a schematic diagram showing a comparison of two-dimensional current line distributions.
图 11是表示本发明用于集成电路中的情况下高压 SOI横向 MOSFET 器件与低压电路的隔离的示意图。  Figure 11 is a diagram showing the isolation of a high voltage SOI lateral MOSFET device from a low voltage circuit in the case where the present invention is used in an integrated circuit.
附图标记说明：  Description of the reference signs:
1、 衬底层； 2、 介质埋层； 3、 有源层； 4、 半导体埋层； 5、 导电材 料； 5'、 导电材料； 6、 槽栅介质； 6'、 平面栅介质； 8、 槽栅结构； 8'、 平面栅结构； 9、 体区； 10、 体接触区； l la、 源区； l lb、 源区； 12、 漏 区； 13、 浅 P+区； 14、 槽栅沟道区； 14'、 平面栅沟道区； 30、 隔离槽； S、 源电极； D、 漏电极； G、 槽栅电极； G'、 平面栅电极； G〃 、 栅电极。 具体实施方式  1. Substrate layer; 2. Dielectric buried layer; 3. Active layer; 4. Semiconductor buried layer; 5. Conductive material; 5', conductive material; 6. Slot gate medium; 6', planar gate medium; Gate structure; 8', planar gate structure; 9, body region; 10, body contact region; l la, source region; l lb, source region; 12, drain region; 13, shallow P+ region; 14', planar gate channel region; 30, isolation trench; S, source electrode; D, drain electrode; G, trench gate electrode; G', planar gate electrode; G〃, gate electrode. detailed description
为了使本发明的技术方案更加清楚和明白，以下参照附图并结合具体 实施例， 对本发明进行更详细的描述。 附图是示意性的， 并不一定按比例 绘制， 贯穿附图相同的附图标记表示相同的部分。  In order to make the technical solutions of the present invention clearer and clear, the present invention will be described in more detail below with reference to the accompanying drawings. The drawings are schematic and are not necessarily to scale, the same reference
本发明的技术方案是， 充分利用槽栅、 平面栅以及半导体埋层， 即利 用双栅结构配合半导体埋层， 对 SOI横向 MOSFET器件的电气性能进行 了综合改进和提高。 为了方便描述， 本发明的 SOI横向 MOSFET器件有 时也简称为器件。 <实施例 1> The technical solution of the present invention is to make full use of the trench gate, the planar gate and the semiconductor buried layer, that is, to utilize the double gate structure to cooperate with the semiconductor buried layer, and comprehensively improve and improve the electrical performance of the SOI lateral MOSFET device. For convenience of description, the SOI lateral MOSFET device of the present invention is sometimes simply referred to as a device. <Example 1>
图 4 ( a )是表示本发明的 P型半导体埋层 4和体区 9接触的 N沟道 双栅 SOI横向 MOSFET器件元胞结构的剖视图。如图 4 ( a )所示， 在 SOI 横向 MOSFET器件中， 自下而上依次层叠有衬底层 1、 介质埋层 2和有 源层 3 , 有源层 3具有分别位于有源层 3的表面并且相互分离的体区 9和 漏区 12、 以及位于体区 9的表面并且从靠近漏区 12的一侧起按顺序设置 的平面栅沟道区 14'、 源区 l la、 体接触区 10和源区 l ib, 位于体区 9和 漏区 12之间的有源层 3为漂移区，其导电类型和体区 9的导电类型相反， 有源层 3在其表面以下设置有半导体埋层 4, 半导体埋层 4和体区 9的导 电类型相同。 在本发明中， 对于半导体埋层 4与体区 9的上下相对位置， 并不进行特别限定， 可以位于体区 9的下方， 也可以包含于体区 9的纵向 范围之中。 在 SOI横向 MOSFET器件中， 设置有槽栅结构 8和平面栅结 构 8' ， 槽栅结构 8由槽栅介质 6及其包围的导电材料 5构成， 槽栅结构 8与体区 9接触， 并与半导体埋层 4也接触， 并且槽栅结构 8从有源层 3 的表面纵向延伸至介质埋层 2, 平面栅结构 8'形成于体区 9的上方， 由平 面栅介质 6'及其上面的导电材料 5'构成， 导电材料 5'为多晶硅或 /和金属。 当器件导通时，在平面栅电极 G'之下的体区 9表面形成平面栅沟道区 14', 经过平面栅沟道区 14'的电流流经半导体埋层 4之上的有源层 3 , 并且， 在槽栅侧面形成槽栅沟道区 14, 且延伸的槽栅结构 8侧面在有源层 3 内 形成多子积累层， 经过槽栅沟道区 14的电流流经半导体埋层 4之下的有 源层 3。 和具有埋层的平面栅 SOI器件不同的是， 本例器件结构具有双栅 结构（槽栅结构 8和平面栅结构 8' )， 双栅电极即槽栅电极 G和平面栅电 极 G'电气连接， 且半导体埋层 4和体区 9接触。 与图 3所示的结构相比， 本例中器件的耐压得到提高， 且对半导体埋层 4的位置不敏感。 由于采用 了双栅结构， 所以能增大有效导电区域， 缩短电流流通路径， 使导通电阻 下降 30%以上， 降 4氏了器件的静态功 4€。 此外， 图 4 )也可以构成为： 半导体埋层 4与体区 9接触， 但不与槽栅结构 8接触。  Fig. 4 (a) is a cross-sectional view showing the cell structure of the N-channel double-gate SOI lateral MOSFET device in which the P-type semiconductor buried layer 4 of the present invention is in contact with the body region 9. As shown in FIG. 4(a), in the SOI lateral MOSFET device, a substrate layer 1, a dielectric buried layer 2, and an active layer 3 are laminated in this order from bottom to top, and the active layer 3 has a surface on the active layer 3, respectively. And the body region 9 and the drain region 12 separated from each other, and the planar gate channel region 14', the source region l la, and the body contact region 10 which are disposed on the surface of the body region 9 and are disposed in order from the side close to the drain region 12 And the source region l ib , the active layer 3 between the body region 9 and the drain region 12 is a drift region, the conductivity type thereof is opposite to the conductivity type of the body region 9 , and the active layer 3 is provided with a semiconductor buried layer below the surface thereof 4. The semiconductor buried layer 4 and the body region 9 have the same conductivity type. In the present invention, the upper and lower relative positions of the semiconductor buried layer 4 and the body region 9 are not particularly limited, and may be located below the body region 9, or may be included in the longitudinal direction of the body region 9. In the SOI lateral MOSFET device, a trench gate structure 8 and a planar gate structure 8' are provided. The trench gate structure 8 is composed of a trench gate dielectric 6 and a conductive material 5 surrounded by the trench gate structure 8 in contact with the body region 9, and The semiconductor buried layer 4 is also in contact, and the trench gate structure 8 extends longitudinally from the surface of the active layer 3 to the dielectric buried layer 2, and the planar gate structure 8' is formed above the body region 9, from the planar gate dielectric 6' and above The conductive material 5' is composed of a conductive material 5' which is polysilicon or/and metal. When the device is turned on, a planar gate channel region 14' is formed on the surface of the body region 9 below the planar gate electrode G', and a current passing through the planar gate channel region 14' flows through the active layer above the semiconductor buried layer 4. 3, and a trench gate channel region 14 is formed on the side of the trench gate, and a side of the extended trench gate structure 8 forms a multi-sub-accumulation layer in the active layer 3, and a current flowing through the trench gate channel region 14 flows through the semiconductor buried layer Active layer 3 below 4. Unlike the planar gate SOI device having a buried layer, the device structure of this example has a double gate structure (slot gate structure 8 and planar gate structure 8'), and the double gate electrode, that is, the trench gate electrode G and the planar gate electrode G' are electrically connected. And the semiconductor buried layer 4 is in contact with the body region 9. Compared with the structure shown in Fig. 3, the withstand voltage of the device in this example is improved and is insensitive to the position of the semiconductor buried layer 4. Due to the double-gate structure, the effective conductive area can be increased, the current flow path can be shortened, and the on-resistance can be reduced by more than 30%, which reduces the static power of the device. Further, Fig. 4) may be configured such that the semiconductor buried layer 4 is in contact with the body region 9, but is not in contact with the trench gate structure 8.
图 4 ( b )是表示本发明的 P型半导体埋层 4和体区 9不接触的 N沟 道双栅 SOI横向 MOSFET器件元胞结构的剖视图。 如图 4 ( b )所示， 其 与图 4 ) 的不同之处仅在于， 半导体埋层 4与体区 9和槽栅结构 8不 接触。 由于采用了双栅结构， 所以能增大有效导电区域， 缩短电流流通路 径， 使导通电阻下降 30%以上， 降低了器件的静态功耗。 与图 3所示的结 构相比， 器件耐压得到提高。 此外， 图 4 ( b )也可以构成为： 半导体埋 层 4与体区 9不接触， 但与槽栅结构 8接触。 4(b) is a cross-sectional view showing the cell structure of the N-channel double-gate SOI lateral MOSFET device in which the P-type semiconductor buried layer 4 of the present invention and the body region 9 are not in contact. As shown in FIG. 4(b), it differs from FIG. 4) only in that the semiconductor buried layer 4 is not in contact with the body region 9 and the trench gate structure 8. Due to the double gate structure, the effective conductive region can be increased, the current flow path can be shortened, and the on-resistance can be reduced by more than 30%, thereby reducing the static power consumption of the device. With the knot shown in Figure 3 Compared with the structure, the withstand voltage of the device is improved. Further, FIG. 4(b) may be configured such that the semiconductor buried layer 4 is not in contact with the body region 9, but is in contact with the trench gate structure 8.
<实施例 2>  <Example 2>
图 5是表示本发明的具有 N型半导体埋层 4的 P沟道双栅 SOI横向 MOSFET器件元胞结构的剖视图。 如图 5所示， 其与图 4(a)的不同之处仅 在于， 本例器件的有源层 3、 半导体埋层 4、 源区 l la、 l ib, 漏区 12、 体 区 9和体接触区 10的材料导电类型与 N沟道双栅 SOI横向 MOSFET器 件的相应区域相反， 并且， 也可获得与实施例 1同样的技术效果。 也就是 说， 本发明具有半导体埋层的双栅 MOS控制的横向 SOI 器件， 既可用于 制作 N沟道器件， 也可以制作 P沟道器件。  Figure 5 is a cross-sectional view showing the cell structure of a P-channel double-gate SOI lateral MOSFET device having an N-type semiconductor buried layer 4 of the present invention. As shown in FIG. 5, it differs from FIG. 4(a) only in the active layer 3, the semiconductor buried layer 4, the source regions l la, l ib, the drain region 12, the body region 9 and the device of this example. The material conductivity type of the body contact region 10 is opposite to that of the corresponding region of the N-channel double-gate SOI lateral MOSFET device, and the same technical effects as in Embodiment 1 can be obtained. That is, the present invention has a double-gate MOS controlled lateral SOI device with a semiconductor buried layer, which can be used for both N-channel devices and P-channel devices.
<实施例 3>  <Example 3>
在本实施例 3中， 器件的俯视图为对称结构， 漏区 12位于器件的中 心， 由漏区 12向外是半导体埋层 4、 体区 9、 源区 l la、 体接触区 10、 源 区】 lb和槽栅结构 8， 槽栅结构 8位于器件的外围。 下面， 根据图 6和图 7, 对本实施例 3进行说明。  In the third embodiment, the top view of the device is a symmetrical structure, the drain region 12 is located at the center of the device, and the drain region 12 is outwardly a semiconductor buried layer 4, a body region 9, a source region l la, a body contact region 10, and a source region. The lb and trench gate structure 8, the trench gate structure 8 is located on the periphery of the device. Next, the third embodiment will be described with reference to Figs. 6 and 7.
图 6是表示本发明的具有轴对称结构的一个 SOI横向 MOSFET器件 元胞版图布局的示意图， 即 xz平面图， 其中 ΑΑ' 沿 X方向， 垂直于纸面 的纵向即为 y方向。 该图版图布局以图 4a的结构为例。 图 6以俯视图形 为圆形为例描述轴对称结构。 漏电极 D位于器件中心。 器件以漏区 12的 中心轴线即 y轴为对称轴。 平面栅电极 G'引出， 与器件最外围的槽栅结构 8中的槽栅电极 G电气连接， 构成器件的栅电极 G〃 。 槽栅结构 8位于器 件最外侧以便实现集成电路中高、 低压单元的隔离。  Fig. 6 is a view showing the layout of a cell layout of an SOI lateral MOSFET device having an axisymmetric structure of the present invention, i.e., an xz plan view, wherein ΑΑ' in the X direction, perpendicular to the longitudinal direction of the paper, is the y direction. The layout of the layout is exemplified by the structure of Fig. 4a. Fig. 6 shows an axisymmetric structure taking a circular shape in a plan view as an example. The drain electrode D is located at the center of the device. The device has a central axis of the drain region 12, i.e., the y-axis, as the axis of symmetry. The planar gate electrode G' is taken out and electrically connected to the trench gate electrode G in the trench gate structure 8 at the outermost periphery of the device to constitute the gate electrode G? of the device. The trench gate structure 8 is located on the outermost side of the device to provide isolation of the high and low voltage cells in the integrated circuit.
对于轴对称结构， 在版图设计中， 漏区 12俯视图形可以为圆形或除 正三角形之外的正多边形， 与之匹配地， 半导体 ii层 4、 源区 l la、 体接 触区 10、 源区 l ib和槽栅结构 8的俯视图形则为圆形环带或除正三角形 环带之外的正多边形环带。 对于俯视图形为圆形的漏区 12 , 且半导体埋 层 4、 体区 9、 源区 l la、 体接触区 10、 源区 l ib和槽栅结构 8的俯视图 形为圆形环带的器件结构， 具有最佳的对称型， 且减弱了曲率效应， 因而 耐压最高， 并节省芯片面积。 一般而言， 同一器件的漏区 12俯视图形与 外围如槽栅结构 8和半导体埋层 4的俯视图形相匹配， 如漏区 12为正六 边形， 半导体埋层 4、 体区 9、 源区 l la、 体接触区 10、 源区 l ib和槽栅 结构 8也为正六边形环带。 图 7是表示本发明的具有面对称结构的一个 SOI横向 MOSFET器件 元胞版图布局的示意图。 如图 7所示， 该图为 xz平面图， 其中 ΑΑ' 沿 X 方向， ΒΒ' 沿 ζ方向， 垂直于纸面的纵向即为 y方向。 该器件的对称面 为过 ΒΒ' 的 yz平面。 该图包含半导体埋层 4和槽栅结构 8的版图， 还具 有如下的金属电极的版图： 槽栅电极0、 平面栅电极 G'、 栅电极 G〃 （槽 栅电极 G和平面栅电极 G'电气连接， 由同一电极 G〃 引出连在一起构成 ) 源电极 S和漏电极0。在该版图布局上， 电学上起作用的源区 l la、 l ib (图 6、 图 7为俯视图， 源区 l la、 1 lb和体接触区 10被遮挡， 因此 未显示出， 但其与其他部件的相对位置例如可参见图 4 ( a ) ) 、 漏区 12、 槽栅结构 8、 半导体埋层 4等俯视图形均为条形， 图中漏区 12位于器件 中心， 漏电极 D两边结构左右对称， 平分漏区 12且不穿过槽栅结构 8的 平面为其对称面， 从漏区 12向外依次为半导体埋层 4、 平面栅电极 G'、 源电极 S、 槽栅结构 8 , 槽栅结构 8位于器件最外侧以便将来自漏区 12 的高电位（对于 N沟道器件而言）终止于槽栅结构 8以内， 从而实现集 成电路中高、 低压单元的隔离。 平面栅结构 8'中由平面栅电极 G'引出， 槽 栅结构 8中的导电材料 5 由槽栅电极 G引出， 它们的共同引出端为器件 的栅电极0〃 。 图中栅电极 G〃 和源电极 S采用了叉指状结构。 此外， 也 可以是图 7所示之外的其他的面对称结构。 For the axisymmetric structure, in the layout design, the top view of the drain region 12 may be a circular or regular polygon other than an equilateral triangle, matching the semiconductor ii layer 4, the source region la, the body contact region 10, the source The top view of the region l ib and the trench gate structure 8 is a circular annulus or a regular polygonal annulus other than the equilateral triangular annulus. For a drain region 12 having a circular shape in plan view, and the semiconductor buried layer 4, the body region 9, the source region l la, the body contact region 10, the source region 1 ib, and the trench gate structure 8 are circular ring-shaped devices. The structure, which has the best symmetry type, and reduces the curvature effect, thus the highest withstand voltage and saves chip area. In general, the top view pattern of the drain region 12 of the same device matches the top view of the periphery such as the trench gate structure 8 and the semiconductor buried layer 4, such as the drain region 12 being a regular hexagon, the semiconductor buried layer 4, the body region 9, and the source region The la, body contact region 10, source region l ib and trench gate structure 8 are also regular hexagonal annulus. Figure 7 is a diagram showing the cell layout layout of an SOI lateral MOSFET device having a plane symmetrical structure of the present invention. As shown in Fig. 7, the figure is an xz plan view, in which ΑΑ' is in the X direction, ΒΒ' is in the ζ direction, and perpendicular to the longitudinal direction of the paper is the y direction. The symmetry plane of the device is the yz plane of the ΒΒ'. The figure includes a layout of the semiconductor buried layer 4 and the trench gate structure 8, and also has a layout of metal electrodes: a trench gate electrode 0, a planar gate electrode G', a gate electrode G? (a trench gate electrode G and a planar gate electrode G' The electrical connection is made up of the same electrode G〃 connected to each other) source electrode S and drain electrode 0. In the layout of the layout, the electrically active source regions l la, l ib (Fig. 6, Fig. 7 are top views, the source regions l la, 1 lb and the body contact region 10 are occluded, and thus are not shown, but For the relative positions of other components, for example, see FIG. 4( a )), the drain region 12, the trench gate structure 8, and the semiconductor buried layer 4, and the like, the top view pattern is strip-shaped. In the figure, the drain region 12 is located at the center of the device, and the drain electrode D is structured on both sides. The left and right symmetry, the drain region 12 is evenly divided and the plane of the trench gate structure 8 is not symmetrical, and the semiconductor buried layer 4, the planar gate electrode G', the source electrode S, and the trench gate structure 8 are sequentially arranged from the drain region 12, The trench gate structure 8 is located on the outermost side of the device to terminate the high potential (for N-channel devices) from the drain region 12 within the trench gate structure 8, thereby achieving isolation of the high and low voltage cells in the integrated circuit. The planar gate structure 8' is led out by the planar gate electrode G', and the conductive material 5 in the trench gate structure 8 is taken out by the trench gate electrode G, and their common terminals are the gate electrodes of the device. In the figure, the gate electrode G 〃 and the source electrode S have an interdigitated structure. Further, other plane symmetrical structures than those shown in FIG. 7 may be used.
<其他实施例〉  <Other Embodiments>
本发明的 SOI横向器件可用于 MOS控制的横向功率器件， 最适合用 于集成电路的有源器件，特别是适合用于功率集成电路或射频功率集成电 路。  The SOI lateral device of the present invention can be used for MOS controlled lateral power devices, and is most suitable for active devices for integrated circuits, particularly for power integrated circuits or RF power integrated circuits.
本发明的上述各实施例描述的器件， 可以采用 Si、 SiC、 SiGe、 GaAs 或 GaN等作为有源层 3的材料制作器件或集成电路， 这些材料技术成熟， 取材方便， 可以满足不同器件或电路性能要求。  The device described in the above embodiments of the present invention can be made of Si, SiC, SiGe, GaAs or GaN as the material of the active layer 3, and the materials are mature and convenient, and can satisfy different devices or circuits. Performance requirements.
如果有源层 3是材料采用 Si, 则优选导电材料 5和 5'为多晶硅。  If the active layer 3 is made of Si, the conductive materials 5 and 5' are preferably polycrystalline silicon.
槽栅介质 6和平面栅介质 6'的选择， 也可以采用 Si02,或介电系数高 于 Si02且临界击穿电场与 Si02相当或更高的介质: 如 Si3N4、 A1N、 A1203 或 Hf〇2等。 槽栅介质 6采用较高的介电系数， 可以增强栅电压对栅电荷 的控制能力， 增大跨导。 或者， 在相同的栅结构 MIS ( Metal-Insulator- Semiconductor,栅电极 -栅介质-栅介质下的半导体形成 MIS结构）电容下， 可以将槽栅介质 6做得更厚， 减小隧道电流， 避免隧穿效应， 增强器件或 芯片的稳定性与可靠性。 Trench gate and planar gate dielectric medium 6 selected 6 'may be employed Si0 2, or Si0 2 is higher than the dielectric constant and the dielectric breakdown field threshold equal to or higher Si0 2: The Si 3 N 4, A1N, A1 2 0 3 or Hf〇 2, etc. The trench gate dielectric 6 adopts a higher dielectric constant, which can enhance the gate voltage control capability of the gate charge and increase the transconductance. Alternatively, under the same gate structure MIS (Metal-Insulator-Semiconductor), the trench gate dielectric 6 can be made thicker to reduce the tunnel current and avoid Tunneling effect, enhancement device or Chip stability and reliability.
对于介质埋层 2的材料， 可以是 Si02, 或采用介电系数低于 Si02且 临界击穿电场高于 Si临界击穿电场的 3倍的介质， 如 SiOF或 SiCOF等。 采用介电系数较 ^的介质， 可以增强介质埋层 2的电场， 有利于器件耐压 的提高。 For the material of the dielectric buried layer 2, it may be Si0 2 , or a medium having a dielectric constant lower than Si0 2 and a critical breakdown electric field higher than three times the critical breakdown electric field of Si, such as SiOF or SiCOF. The dielectric of the dielectric buried layer 2 can be enhanced by using a medium having a higher dielectric constant, which is advantageous for improving the withstand voltage of the device.
本发明的技术方案对衬底材料几乎没有要求，可以是 n型或 p型半导 体材料， 甚至可以是绝缘介质材料， 或与介质埋层 2为同一种介质材料。  The technical solution of the present invention has almost no requirement for the substrate material, and may be an n-type or p-type semiconductor material, or even an insulating dielectric material, or the same dielectric material as the dielectric buried layer 2.
<实施例与现有技术的效果评价〉  <Evaluation of effects of the prior art and the prior art>
图 8是表示 3种 N沟道 SOI LDMOS的击穿电压对半导体 P埋层位 置依赖关系的示意图。图中，横坐标 Dp为 P埋层距槽栅介质的内边界（以 漏区为器件中心） 的距离； 对比的 3种器件包括： 具有 P埋层的平面栅 SOI LDMOS; 具有 P埋层的槽栅 SOI LDMOS, 如图 3所示。 这 2类 SOI LDMOS均为单栅结构； 双栅 SOI LDMOS为本发明的具有 P半导体埋层 和双栅结构的 SOI LDMOS, 如图 4 ( a )所示。 从图中可以看出， 具有 P 埋层的平面栅 SOI LDMOS的耐压对半导体埋层位置艮敏感， 这对器件的 可靠性来说是不利的； 具有半导体 P埋层的槽栅 SOI LDMOS结构解决了 耐压对半导体埋层敏感性的问题， 半导体埋层的位置在很大范围内变化， 器件的耐压基本没有变化； 本发明中的具有半导体埋层的双栅 SOI LDMOS结构， 从图中可以看出， 解决了耐压对半导体埋层位置的敏感性 的问题。 Fig. 8 is a view showing the dependence of the breakdown voltage of three kinds of N-channel SOI LDMOS on the buried position of the semiconductor P. In the figure, the abscissa D p is the distance of the P buried layer from the inner boundary of the trench gate dielectric (the drain region is the center of the device); the three devices compared include: a planar gate SOI LDMOS with a buried layer; a buried layer P The trench gate SOI LDMOS is shown in Figure 3. These two types of SOI LDMOS are single-gate structures; the dual-gate SOI LDMOS is the SOI LDMOS with P-semiconductor and double-gate structure of the present invention, as shown in Fig. 4(a). It can be seen from the figure that the withstand voltage of the planar gate SOI LDMOS with P buried layer is sensitive to the buried position of the semiconductor, which is disadvantageous for the reliability of the device; the trench gate SOI LDMOS structure with the buried layer of the semiconductor P The problem of the withstand voltage sensitivity to the buried layer of the semiconductor is solved, the position of the buried layer of the semiconductor is varied within a wide range, and the withstand voltage of the device is substantially unchanged; the double-gate SOI LDMOS structure having the semiconductor buried layer in the present invention, from the figure It can be seen that the problem of the sensitivity of the withstand voltage to the buried position of the semiconductor is solved.
图 9是表示几种结构的 N沟道 SOI LDMOS正向电流-电压特性曲线 的示意图。 图中， 具有 P埋层的槽栅 SOI LDMOS结构如图 3所示； 单 RESURF平面栅 SOI LDMOS是常规的 N沟道平面栅 SOI LDMOS; 具有 P埋层的双栅 SOI LDMOS是本发明的具有 P埋层的 N 沟道双栅 SOI LDMOS, 如图 4 ( a )所示； 双 RESURF平面栅 SOI LDMOS结构如图 2 所示。 从图中可以知道在一定的电流密度下， 本发明的具有半导体埋层的 双栅结构具有最下的正向压降， 具有半导体埋层的单槽栅 SOI LDMOS次  Fig. 9 is a view showing a forward current-voltage characteristic curve of an N-channel SOI LDMOS of several structures. In the figure, a trench gate SOI LDMOS structure having a P buried layer is shown in FIG. 3; a single RESURF planar gate SOI LDMOS is a conventional N-channel planar gate SOI LDMOS; a double-gate SOI LDMOS having a P buried layer is the present invention having The P-buried N-channel double-gate SOI LDMOS is shown in Figure 4 (a); the double RESURF planar gate SOI LDMOS structure is shown in Figure 2. It can be seen from the figure that the double-gate structure with semiconductor buried layer of the present invention has the lowest forward voltage drop at a certain current density, and the single-slot gate SOI LDMOS with semiconductor buried layer
SOI LDMOS结构降低了 49.3%, 比单 RESURF SOI LDMOS结构降低了 64.2%, 比半导体埋层单槽栅 SOI LDMOS (由于半导体埋层常规平面栅 SOI LDMOS耐压特性太差， 这里不做比较） 下降了 38.2%。 本发明的具 有半导体埋层的双栅结构的比导通电阻能有这么大的下降，一是由于 P埋 层的存在使得漂移区的优化浓度有很大的提高； 二是由于采用了双栅结 构， 使电流路径比较短， 且拓展了有源层有效导电面积， 使电流分布比较 均匀， 因而， 降低了器件的比导通电阻。 The SOI LDMOS structure is reduced by 49.3%, which is 64.2% lower than that of the single RESURF SOI LDMOS structure. Compared with the semiconductor buried single-slot SOI LDMOS (because the semiconductor buried layer conventional planar gate SOI LDMOS has poor withstand voltage characteristics, it is not compared here) 38.2%. The specific on-resistance of the double gate structure of the semiconductor buried layer of the present invention can be greatly reduced, and the first is due to the buried of P The existence of the layer makes the optimized concentration of the drift region greatly improved. Secondly, due to the double gate structure, the current path is shorter, and the effective conductive area of the active layer is expanded, so that the current distribution is relatively uniform, thereby reducing the current. The specific on-resistance of the device.
图 10是表示二维电流线分布的比较的示意图 （半个元胞） ， 2根相 邻电流线的电流强度差为 4 χ 1(Τ7Α/ μ ιη。 其中图 10 ( a )表示单 RESURF 平面栅 SOI LDMOS, 图 10 ( b )表示双 RESURF平面栅 SOI LDMOS , 图 10 ( c )表示具有半导体埋层的单槽栅 SOI器件， 图 10 ( d )表示本发 明的具有半导体埋层的双栅 SOI器件。 由图中可知， 具有半导体埋层的双 栅 SOI器件的电流分布最为均匀， 且在相同正向压降下， 电流密度最大； 具有半导体埋层单槽栅 SOI器件次之， 且都优于其他两种结构。 由于电流 分布比较均匀， 所以正向导通的导通电阻小、 以及可以具有更好的温度特 性。 综上， 本发明一方面使器件耐压得到提高， 且解决了耐压对半导体埋 层位置的敏感性问题； 另一方面， 由于采用的双栅结构以及引入半导体埋 层， 所以使得器件具有更低的比导通电阻； 再者， 高压截止状态时， 纵向 延伸至介质埋层上表面的槽栅介质将来自于器件中心的漏区的高电位终 止于槽栅以内， 能够避免高电位对槽栅以外的低压电路的影响。 因此， 槽 栅同时也作为介质隔离槽， 这不仅节省了介质隔离槽的面积， 而且不需要 像常规 SOI高压集成电路那样， 采用专门工艺流程制作介质隔离槽， 简化 了功率集成电路工艺， 节约了成本。 Fig. 10 is a schematic diagram showing the comparison of the two-dimensional current line distribution (half cell), and the current intensity difference of two adjacent current lines is 4 χ 1 (Τ 7 Α / μ ηη. wherein Fig. 10 (a) indicates a single RESURF planar gate SOI LDMOS, Fig. 10(b) shows a double RESURF planar gate SOI LDMOS, Fig. 10(c) shows a single trench gate SOI device with a semiconductor buried layer, and Fig. 10(d) shows a semiconductor buried layer of the present invention Double-gate SOI device. As can be seen from the figure, the current distribution of the double-gate SOI device with semiconductor buried layer is the most uniform, and the current density is the highest under the same forward voltage drop; the semiconductor buried single-slot SOI device is the second. Both of them are superior to the other two structures. Since the current distribution is relatively uniform, the on-resistance of the forward conduction is small, and the temperature characteristics can be better. In summary, the present invention improves the withstand voltage of the device and solves the problem. The sensitivity of the withstand voltage to the buried position of the semiconductor; on the other hand, due to the double gate structure and the introduction of the semiconductor buried layer, the device has a lower specific on-resistance; When the trench gate medium extending longitudinally to the upper surface of the dielectric buried layer terminates the high potential of the drain region from the center of the device within the trench gate, the influence of the high potential on the low voltage circuit other than the trench gate can be avoided. Also used as a dielectric isolation trench, which not only saves the area of the dielectric isolation trench, but also does not require a special process flow to form a dielectric isolation trench like a conventional SOI high voltage integrated circuit, which simplifies the power integrated circuit process and saves costs.
<变形例 >  <Modification>
图 1 1是表示本发明用于集成电路中的情况下高压器件与低压电路的 隔离.的示意图。 从该图 1 1可以看出， 采用本发明， 高压器件与低压电路 之间不需要形成专门的隔离槽 （比如图 1 中的隔离槽 30 ) ， 本发明的槽 栅结构 8 , 配以围绕槽栅外边界接地的浅 P+区 13， 可以有效地避免栅极 的开关瞬态对低压电路区域的影响， 从而具有完善的隔离功能， 由此降低 了集成电路的制造成本和工艺难度。  Fig. 11 is a view showing the isolation of a high voltage device from a low voltage circuit in the case where the present invention is used in an integrated circuit. As can be seen from FIG. 11 , with the present invention, there is no need to form a special isolation trench (such as the isolation trench 30 in FIG. 1 ) between the high voltage device and the low voltage circuit, and the trench gate structure 8 of the present invention is provided with the surrounding trench The shallow P+ region 13 grounded to the outer boundary of the gate can effectively avoid the influence of the switching transient of the gate on the low voltage circuit region, thereby having a perfect isolation function, thereby reducing the manufacturing cost and process difficulty of the integrated circuit.
以上通过示例性实施例描述了本发明， 然而， 这并不意图限制本 发明的保护范围。 本领域技术人员可以想到的上述实施例的任何修改 或变型都落入由所附权利要求限定的本发明的范围内。 例如， 还可以 对各实施例或实施例中的要素进行任意组合使用。  The invention has been described above by way of exemplary embodiments, however, this is not intended to limit the scope of the invention. Any modification or variation of the above-described embodiments that can be conceived by those skilled in the art is intended to fall within the scope of the invention as defined by the appended claims. For example, the elements in the respective embodiments or examples may be used in any combination.

Claims

权 利 要 求 Rights request
1. 一种 SOI横向 MOSFET器件， 其自下而上依次层叠有衬底层、 介质埋层和有源层， 其特征在于， An SOI lateral MOSFET device in which a substrate layer, a dielectric buried layer, and an active layer are laminated in this order from bottom to top, wherein
所述有源层包括：  The active layer includes:
分别位于所述有源层的表面并且相互分离的体区和漏区， 以及 位于所述体区的表面并且从靠近所述漏区的一侧起按顺序设置的 平面栅沟道区、 第一源区、 体接触区和第二源区；  Body and drain regions respectively located on the surface of the active layer and separated from each other, and a planar gate channel region located in the surface of the body region and disposed in order from a side close to the drain region, first a source region, a body contact region, and a second source region;
位于所述体区和所述漏区之间的所述有源层为漂移区， 所述漂移 区和所述体区的导电类型相反；  The active layer between the body region and the drain region is a drift region, and the drift region and the body region have opposite conductivity types;
所述有源层在其表面以下设置有半导体埋层， 所述半导体埋层和 所述体区的导电类型相同；  The active layer is provided with a semiconductor buried layer below the surface thereof, and the semiconductor buried layer and the body region have the same conductivity type;
所述器件具有槽栅结构和平面栅结构， 所述槽栅结构与所述体区 栅结构形成于所述体 '区的上方， 所 槽栅结构由槽栅介质及其包围的 导电材料构成， 所述平面栅结构由平面栅介质及其上面的导电材料构 成。.  The device has a trench gate structure and a planar gate structure formed above the body region, and the trench gate structure is composed of a trench gate dielectric and a conductive material surrounded by the same. The planar gate structure is composed of a planar gate dielectric and a conductive material thereon. .
2. 根据权利要求 1 所述的器件， 其特征在于， 所述半导体埋层与 所述体区接触、 或所述半导体埋层与所述体区不接触， 所述半导体埋 层与所述槽栅结构接触、 或所述半导体埋层与所述槽栅结构不接触。  2. The device according to claim 1, wherein the semiconductor buried layer is in contact with the body region, or the semiconductor buried layer is not in contact with the body region, the semiconductor buried layer and the trench The gate structure contacts, or the semiconductor buried layer does not contact the trench gate structure.
3. 根据权利要求 1或 2所述的器件， 其特征在于， 所述器件的俯 视图为对称结构， 所述漏区位于所述器件的中心， 由所述漏区向外依 次是所述半导体埋层、 所述体区、 所述第一源区、 所述体接触区、 所 述第二源区和所述槽栅结构， 所述槽栅结构位于所述器件的外围。  The device according to claim 1 or 2, wherein the top view of the device is a symmetrical structure, the drain region is located at a center of the device, and the semiconductor region is buried by the drain region. a layer, the body region, the first source region, the body contact region, the second source region, and the trench gate structure, the trench gate structure being located at a periphery of the device.
4. 根据权利要求 3所述的器件， 其特征在于， 所述器件为轴对称 结构， 所述漏区的中心轴线为所述器件的对称轴。  4. The device according to claim 3, wherein the device is an axisymmetric structure, and a central axis of the drain region is an axis of symmetry of the device.
5. 根据权利要求 4所述的器件， 其特征在于， 所述器件在俯视时， 所述漏区为圆形， 所述半导体埋层、 所述体区、 所述第一源区、 所述 体接触区、 所述第二源区和所述槽栅结构为圆形环带状。  The device according to claim 4, wherein the device has a circular shape in a plan view, the semiconductor buried layer, the body region, the first source region, and the The body contact region, the second source region, and the trench gate structure are in the shape of a circular ring.
6. 根据权利要求 3所述的器件， 其特征在于， 所述器件为面对称 结构， 平分所述漏区且不穿过所述槽栅结构的平面为所述器件的对称 面。 6. The device according to claim 3, wherein the device is a plane symmetrical structure, and a plane that bisects the drain region and does not pass through the trench gate structure is a symmetry plane of the device.
7. 根据权利要求 1或 2所述的器件， 其特征在于, 所述器件用于 MOS控制的半导体器件。 7. A device according to claim 1 or 2, characterized in that the device is used in a MOS controlled semiconductor device.
8. 根据权利要求 1或 2所述的器件， 其特征在于， 所述有源层的 材料包括 Si、 SiC、 SiGe、 GaAs或 GaN。  The device according to claim 1 or 2, wherein the material of the active layer comprises Si, SiC, SiGe, GaAs or GaN.
9. 根据权利要求 1或 2所述的器件， 其特征在于， 所述介质埋层 的材料为 Si02 , 或者为包括 SiOF或 SiCOF的介电系数低于 Si02且临 界击穿电场高于 Si临界击穿电场的 3倍的介质。 The device according to claim 1 or 2, wherein the dielectric buried material is Si0 2 or the dielectric constant including SiOF or SiCOF is lower than Si0 2 and the critical breakdown electric field is higher than Si A dielectric that is 3 times the critical breakdown electric field.
10. 根据权利要求 1或 2所述的器件， 其特征在于， 所述槽栅介质 为 Si02 , 或者为包括 Si3N4、 A1203、 A1N或 Hf02的介电系数高于 Si02 且临界击穿电场与 Si02相当或更高的介质。 The device according to claim 1 or 2, wherein the trench gate dielectric is Si0 2 or a dielectric coefficient including Si 3 N 4 , A1 2 0 3 , A1N or Hf0 2 is higher than Si0 2 and a medium with a critical breakdown electric field equal to or higher than Si0 2 .
1 1. 根据权利要求 1或 2所述的器件， 其特征在于， 在所述器件用 作高压器件并与低压电路隔离时， 直接将槽栅结构作为隔离高压区域 与低压区域间的隔离槽， 或者利用与制作槽栅结构相同的工艺同时形 成隔离才曹。  1 . The device according to claim 1 or 2, wherein when the device is used as a high voltage device and is isolated from the low voltage circuit, the trench gate structure is directly used as an isolation trench between the isolated high voltage region and the low voltage region. Or use the same process as the trench gate structure to form the isolation.
12. 一种集成电路， 其特征在于， 作为所述集成电路的有源器件， 包括根据权利要求 1至 1 1的任一项所述的器件。  An integrated circuit, characterized in that the active device of the integrated circuit comprises the device according to any one of claims 1 to 11.
13. 根据权利要求 12所迷的集成电路， 其特征在于， 所述集成电 路为功率集成电路或射频功率集成电路。  13. An integrated circuit as claimed in claim 12, wherein the integrated circuit is a power integrated circuit or a radio frequency power integrated circuit.
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