CN109698196B - Power semiconductor device - Google Patents
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- CN109698196B CN109698196B CN201811621100.0A CN201811621100A CN109698196B CN 109698196 B CN109698196 B CN 109698196B CN 201811621100 A CN201811621100 A CN 201811621100A CN 109698196 B CN109698196 B CN 109698196B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 210000000746 body region Anatomy 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052710 silicon Inorganic materials 0.000 claims description 34
- 239000010703 silicon Substances 0.000 claims description 34
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 235000012431 wafers Nutrition 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
Abstract
The invention provides a power semiconductor device, which comprises a second conduction type substrate, a first conduction type lower drift region, a first conduction type drain contact region, a drain metal electrode, a second conduction type lower body region, a first conduction type lower source region, a second conduction type lower body contact region, a lower source electrode, a lower gate dielectric layer, a lower gate electrode, a buried oxide layer, a first conduction type upper drift region, a second conduction type upper body region, a first conduction type upper source region, a second conduction type upper body contact region, an upper source electrode, a first conduction type upper drain contact region, an upper gate dielectric layer and an upper gate electrode, wherein the conduction resistance of the LDMOS device is reduced, the off-state breakdown voltage characteristic of the device is not influenced, and on the basis of maintaining the breakdown voltage unchanged, the double-layer LDMOS device structure provided by the invention is adopted, compared with the traditional LDMOS device, the conduction resistance is reduced by more than 50%, therefore, the on-state power consumption of the device is effectively reduced.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to an SOI power semiconductor device with low on-resistance.
Background
With the development of miniaturization and integration of electronic equipment and electric power systems, power high-voltage integrated circuits have wider market and application space, power high-voltage integrated technologies are subject to more and more research and attention, and the power high-voltage integrated technologies aim at realizing monolithic integration of high-voltage devices and low-voltage devices and lay a foundation for the development of the power high-voltage integrated circuits. The power high-voltage device is the core of the power high-voltage integrated power circuit, and the LDMOS (Laterally diffused MOSFET) is one of the most important high-voltage integrated power devices, has the characteristics of easy integration, high switching speed, voltage control, good temperature stability and the like, and is widely applied to power high-voltage integrated circuits such as a power supply circuit, an analog switch circuit, a high-voltage driving circuit and the like.
Conventional LDMOS devices are shown in FIG. 1, and the circuitry requires a high-voltage power LDMOS having a low on-resistance (R)on,sp) And parasitic capacitance to reduce device conduction loss and switching loss, and high off-state Breakdown Voltage (BV), and there is a contradiction between on-resistance and off-state withstand voltage, Ron,sp∝BV2.5As the device breakdown voltage increases, the on-resistance rises rapidly. In order to solve the pair of contradictions, various device structures represented by Resurf technology are proposed, a Super Junction (Super Junction) structure is proposed by chen assist academy of electronics science and technology university in U.S. patent No.5216275, a novel power MOS device CoolMOS based on the Super Junction structure is proposed, the device greatly reduces on-resistance while keeping device voltage resistance, so that the contradiction between on-resistance and voltage resistance is relieved, and multiple universities and companies at home and abroad develop a Super Junction LDMOS device based on the Super Junction principle, as shown in fig. 2. However, with the continuous development of circuit integration, the demand for low power consumption of devices is increasing, and the search for new structures of low on-resistance devices is promoted.
In the SOI (Silicon-On-Insulator) technology, an insulating layer is introduced into a Silicon layer to isolate the Silicon layer On the surface from a substrate, so that the parasitic latch-up effect of a bulk Silicon device is eliminated, the substrate leakage of the device is greatly reduced, the reliability of the device is improved, and the conventional SOI LDMOS device has a structure as shown in fig. 3. Meanwhile, an integrated circuit adopting the SOI technology has the advantages of small parasitic capacitance, high integration density, high speed, simple process and the like, and SOI devices occupy an increasingly important position in power integrated circuits. Therefore, the research of developing the SOI high-voltage LDMOS device with low on-resistance based on the SOI technology has important significance.
Disclosure of Invention
In order to further reduce the on-resistance of the SOI high-voltage LDMOS device and reduce the on-loss of the device on the basis of the prior art, the invention provides a power semiconductor device and a possible process implementation mode thereof. The device provided by the invention adopts a double-layer device structure, the device structure is formed below the SOI layer of the traditional SOI LDMOS device, the space of the device is fully utilized, the on-resistance of the device can be effectively reduced under the condition of not influencing the off-state voltage resistance of the device, and the purpose of reducing the power consumption of the device is achieved.
In order to realize the purpose, the technical scheme is as follows:
a power semiconductor device includes a second conductive type substrate 9, a first conductive type lower drift region 11 is arranged on the second conductive type substrate 9; a first conductive type drain contact region 12 with high doping concentration is arranged on the right side of the first conductive type lower drift region 11, and the first conductive type drain contact region 12 is connected with the device top drain metal electrode 10; a second conductive type lower body region 13 is arranged on the left side of the first conductive type lower drift region 11; a first-conductivity-type lower source region 14 and a second-conductivity-type lower body contact region 15 above the first-conductivity-type lower source region 14 are arranged on the left side in the second-conductivity-type lower body region 13, a lower source electrode 18 short-circuits the first-conductivity-type lower source region 14 and the second-conductivity-type lower body contact region 15, and the lower source electrode 18 penetrates through the device and is led out from the surface; a lower gate dielectric layer 16 is arranged on the surface of the second conductive type lower body region 13, and a lower gate electrode 17 is arranged on the surface of the lower gate dielectric layer 16; a buried oxide layer 8 is arranged on the first conduction type lower drift region 11, and a first conduction type upper drift region 21 is arranged on the buried oxide layer 8; a second conductive type upper body region 23 is arranged on the left side of the first conductive type upper drift region 21; a first conductive type upper source region 24 and a second conductive type upper body contact region 25 are arranged above the second conductive type upper body region 23, an upper source electrode 28 is arranged on the surface of the device, and the upper source region 24 and the second conductive type upper body contact region 25 are in short circuit; the first conduction type upper drain contact region 22 is positioned in the first conduction type upper drift region 21 and is in contact with the drain metal electrode 10, the upper surface of the second conduction type upper body region 23 is provided with an upper gate dielectric layer 26, and the upper surface of the upper gate dielectric layer 26 is provided with an upper gate electrode 27.
Preferably, there is an STI structure 7 in the upper portion of the drift region 21 on the first conductivity type. The STI structure optimizes the electric field distribution on the surface of the device and improves the voltage endurance capability of the device.
Preferably, the second conductivity type lower auxiliary depletion region 6 is arranged below the buried oxide layer 8 in the first conductivity type lower drift region 11, and the auxiliary depletion region can assist the first conductivity type upper drift region 21 and the first conductivity type lower drift region 11, so that the doping concentrations of the two regions are increased, and the on-resistance of the device is reduced.
Preferably, the lower gate dielectric layer 16 is disposed on the left side surface of the second conductivity type lower body region 13, and the lower gate electrode 17 is disposed on the surface of the lower gate dielectric layer 16.
Preferably, a lower gate dielectric layer 16 is arranged on the upper surface of the second conductivity type lower body region 13, which is in contact with the buried oxide layer 8, and a lower gate electrode 17 is arranged on the surface of the lower gate dielectric layer 16.
The invention also provides a preparation method of the power semiconductor device, which comprises the following steps:
the first step is as follows: manufacturing LDMOS basic device structures comprising a drift region, a body region, a drain contact region and a source region on the surfaces of two silicon wafers respectively;
the second step is that: forming a first oxide layer 8a and a second oxide layer 8b on the surfaces of the two silicon wafers in a deposition or thermal growth mode;
the third step: bonding the oxide layers on the surfaces of the two silicon wafers by a bonding technology to form a buried oxide layer 8;
the fourth step: thinning the silicon layer of the upper device by a CMP technology;
the fifth step: and manufacturing a gate structure of the upper-layer device, forming each metal electrode and finally forming the double-layer SOI device.
The invention also provides a preparation method of the power semiconductor device, which comprises the following steps:
the first step is as follows: manufacturing LDMOS basic device structures comprising a drift region, a body region, a drain contact region and a source region on the surfaces of two silicon wafers;
the second step is that: forming a buried oxide layer 8 on the surface of the device by deposition or thermal growth;
the third step: forming a via in the buried oxide layer 8 by etching techniques to contact the underlying silicon layer;
the fourth step: depositing or thermally growing silicon in the via and to the upper surface of the buried oxide layer 8;
the fifth step: growing an epitaxial silicon layer on the surface of the buried oxide layer 8 on the basis of the silicon grown from the through hole;
and a sixth step: and manufacturing a device structure of the upper LDMOS in the epitaxial silicon layer to finally form the double-layer SOI device.
The invention has the beneficial effects that: the invention reduces the on-resistance of the LDMOS device and does not influence the off-state breakdown voltage characteristic of the device. On the basis of maintaining the breakdown voltage unchanged, compared with the traditional LDMOS device, the double-layer LDMOS device structure provided by the invention has the advantage that the on-resistance is reduced by over 50%, so that the on-power consumption of the device is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional LDMOS device;
FIG. 2 is a schematic diagram of an LDMOS device using super junction technology in the prior art;
FIG. 3 is a schematic diagram of an LDMOS device using SOI technology in the prior art;
fig. 4 is a schematic structural diagram of an LDMOS device according to embodiment 1 of the present invention;
fig. 5 is a schematic structural view of a device proposed in embodiment 2 of the present invention;
fig. 6 is a schematic structural view of a device proposed in embodiment 3 of the present invention;
FIGS. 7A-7E are schematic diagrams of a device process flow proposed in example 5 of the present invention;
FIGS. 8A-8F are schematic diagrams of a device process flow set forth in example 6 of the present invention;
6 is a second conductive type lower auxiliary depletion region, 7 is an STI structure, 8 is a buried oxide layer, 8a is a first oxide layer, 8b is a second oxide layer, 9 is a second conductive type substrate, 10 is a drain metal electrode, 11 is a first conductive type lower drift region, 12 is a first conductive type drain contact region, 13 is a second conductive type lower body region, 14 is a first conductive type lower source region, 15 is a second conductive type lower body contact region, 16 is a lower gate dielectric layer, 17 is a lower gate electrode, 18 is a lower source electrode, 21 is a first conductive type upper drift region, 21a is a first conductive type drift region, 21b is a second conductive type auxiliary depletion region, 22 is a first conductive type upper drain contact region, 23 is a second conductive type upper body region, 24 is a first conductive type upper source region, 25 is a second conductive type upper body contact region, 26 is an upper gate dielectric layer, reference numeral 27 denotes an upper gate electrode, and 28 denotes an upper source electrode.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 4, a power semiconductor device includes: a second conductive type substrate 9, wherein the second conductive type substrate 9 is provided with a first conductive type lower drift region 11; a first conductive type drain contact region 12 with high doping concentration is arranged on the right side of the first conductive type lower drift region 11, and the first conductive type drain contact region 12 is connected with the device top drain metal electrode 10; a second conductive type lower body region 13 is arranged on the left side of the first conductive type lower drift region 11; a first-conductivity-type lower source region 14 and a second-conductivity-type lower body contact region 15 above the first-conductivity-type lower source region 14 are arranged on the left side in the second-conductivity-type lower body region 13, a lower source electrode 18 short-circuits the first-conductivity-type lower source region 14 and the second-conductivity-type lower body contact region 15, and the lower source electrode 18 penetrates through the device and is led out from the surface; a lower gate dielectric layer 16 is arranged on the left side surface of the second conductive type lower body region 13, and a lower gate electrode 17 is arranged on the surface of the lower gate dielectric layer 16; a buried oxide layer 8 is arranged on the first conduction type lower drift region 11, and a first conduction type upper drift region 21 is arranged on the buried oxide layer 8; a second conductive type upper body region 23 is arranged on the left side of the first conductive type upper drift region 21; a first conductive type upper source region 24 and a second conductive type upper body contact region 25 are arranged above the second conductive type upper body region 23, an upper source electrode 28 is arranged on the surface of the device, and the upper source region 24 and the second conductive type upper body contact region 25 are in short circuit; the first conduction type upper drain contact region 22 is positioned in the first conduction type upper drift region 21 and is in contact with the drain metal electrode 10, the upper surface of the second conduction type upper body region 23 is provided with an upper gate dielectric layer 26, and the upper surface of the upper gate dielectric layer 26 is provided with an upper gate electrode 27.
The STI structure 7 is arranged on the upper portion in the first conduction type upper drift region 21, electric field distribution on the surface of the device is optimized through the STI structure, and voltage resistance of the device is improved.
Example 2
As shown in fig. 5, the present embodiment is different from embodiment 1 in that: the upper surface of the second conductive type lower body region 13, which is in contact with the buried oxide layer 8, is provided with a lower gate dielectric layer 16, and the surface of the lower gate dielectric layer 16 is provided with a lower gate electrode 17. The lead-out mode of the gate electrode is changed.
Example 3
As shown in fig. 6, the present embodiment is different from embodiment 1 in that: and a second conductive type lower auxiliary depletion region 6 is arranged below the buried oxide layer 8 in the first conductive type lower drift region 11, and can assist the first conductive type upper drift region 21 and the first conductive type lower drift region 11, so that the doping concentrations of the first conductive type upper drift region and the first conductive type lower drift region are improved, and the on-resistance of the device is reduced.
Example 4
This example differs from example 1 in that: the STI structure 7 is not located in the upper portion of the first conductive upper drift region 21.
Example 5
A manufacturing method of an LDMOS device comprises the following steps:
the first step is as follows: manufacturing an LDMOS basic device structure comprising a drift region, a well region electrode, a drain region and a source region on the surface of a silicon wafer a, and forming a first oxide layer 8a on the surface of the silicon wafer a in a deposition or thermal growth mode;
the second step is that: an upper drift region 21 of the first conductivity type is formed on the substrate of the silicon wafer b, and an upper body region 23 of the second conductivity type, an upper drain contact region 22 of the first conductivity type, and an upper body contact region 25 of the second conductivity type and an upper source region 24 of the first conductivity type are formed in the epitaxial layer. Forming a second oxide layer 8b on the surface of the silicon wafer b by deposition or thermal growth;
the third step: bonding the oxide layers on the surfaces of the two silicon wafers by a bonding technology to form a buried oxide layer 8;
the fourth step: thinning the silicon layer of the upper-layer device to the position of the buried layer first-conductivity-type upper drain contact region 22 by using a CMP technology to form an upper-layer LDMOS basic device structure;
the fifth step: and adding the upper-layer device into the STI structure, manufacturing the gate structure of each layer of device, forming each metal electrode and finally forming the device.
Example 6
A manufacturing method of an LDMOS device comprises the following steps:
the first step is as follows: the second conductive type silicon wafer is used as a second conductive type substrate 9, and first conductive type impurities are lightly doped on the surface of the second conductive type silicon wafer to form a first conductive type lower drift region 11;
the second step is that: photoetching a window of the lower body region 13 of the second conductivity type, and performing ion implantation on the lower body region 13 of the second conductivity type;
the third step: photoetching a window of the first conductive type lower source region 14, the first conductive type drain contact region 12 and a window of the second conductive type lower body contact region 15, and carrying out high-dose implantation to form an LDMOS basic device structure;
the fourth step: forming a buried oxide layer 8 on the surface of the device by deposition or thermal growth;
the fifth step: forming a via in the buried oxide layer 8 by etching techniques to contact the underlying silicon layer;
and a sixth step: depositing or thermally growing silicon in the via hole and up to the upper surface of the buried oxide layer 8, and growing an upper drift region 21 of the first conductivity type on the surface of the buried oxide layer 8 on the basis of the silicon grown from the via hole;
the seventh step: manufacturing a second conductive type upper body region 23, a second conductive type upper body contact region 25, a first conductive type upper source region 24, a first conductive type upper drain contact region 22 and the STI structure 7 in the first conductive type upper drift region 21 to form an upper LDMOS device structure;
eighth step: and manufacturing a grid electrode, and forming each metal electrode to form a final device structure.
Claims (7)
1. A power semiconductor device, characterized by: the device comprises a second conductive type substrate (9), wherein a first conductive type lower drift region (11) is arranged on the second conductive type substrate (9); the right side of the first conduction type lower drift region (11) is provided with a first conduction type drain contact region (12) with high doping concentration, and the first conduction type drain contact region (12) is connected with a device top drain metal electrode (10); a second conductive type lower body region (13) is arranged on the left side of the first conductive type lower drift region (11); a first conduction type lower source region (14) and a second conduction type lower body contact region (15) above the first conduction type lower source region (14) are arranged on the left side in the second conduction type lower body region (13), a lower source electrode (18) is used for short-circuiting the first conduction type lower source region (14) and the second conduction type lower body contact region (15), and the lower source electrode (18) penetrates through the device and is led out from the surface; a lower gate dielectric layer (16) is arranged on the surface of the second conductive type lower body region (13), and a lower gate electrode (17) is arranged on the surface of the lower gate dielectric layer (16); a buried oxide layer (8) is arranged on the first conduction type lower drift region (11), and a first conduction type upper drift region (21) is arranged on the buried oxide layer (8); a second conductive type upper body region (23) is arranged on the left side of the first conductive type upper drift region (21); a first conductive type upper source region (24) and a second conductive type upper body contact region (25) are arranged above the second conductive type upper body region (23), an upper source electrode (28) is arranged on the surface of the device, and the upper source region (24) and the second conductive type upper body contact region (25) are in short circuit; the first conduction type upper drain contact region (22) is positioned in the first conduction type upper drift region (21) and is in contact with the drain metal electrode (10), the upper surface of the second conduction type upper body region (23) is provided with an upper gate dielectric layer (26), and the upper surface of the upper gate dielectric layer (26) is provided with an upper gate electrode (27).
2. The power semiconductor device of claim 1, wherein: the first conduction type upper drift region (21) is internally and upwardly provided with an STI structure (7).
3. The power semiconductor device of claim 1, wherein: and a second conductive type lower auxiliary depletion region (6) is arranged below the buried oxide layer (8) in the first conductive type lower drift region (11).
4. The power semiconductor device of claim 1, wherein: and a lower gate dielectric layer (16) is arranged on the left side surface of the second conductive type lower body region (13), and a lower gate electrode (17) is arranged on the surface of the lower gate dielectric layer (16).
5. The power semiconductor device of claim 1, wherein: and a lower gate dielectric layer (16) is arranged on the upper surface of the second conductive type lower body region (13) which is in contact with the buried oxide layer (8), and a lower gate electrode (17) is arranged on the surface of the lower gate dielectric layer (16).
6. A method for manufacturing a power semiconductor device according to any one of claims 1 to 5, characterized by comprising the steps of:
the first step is as follows: manufacturing LDMOS basic device structures comprising a drift region, a body region, a drain contact region and a source region on the surfaces of two silicon wafers respectively;
the second step is that: forming a first oxide layer (8a) and a second oxide layer (8b) on the surfaces of the two silicon wafers in a deposition or thermal growth mode;
the third step: bonding the oxide layers on the surfaces of the two silicon wafers by a bonding technology to form a buried oxide layer (8);
the fourth step: thinning the silicon layer of the upper device by a CMP technology;
the fifth step: and manufacturing a gate structure of the upper-layer device, forming each metal electrode and finally forming the double-layer SOI device.
7. A method for manufacturing a power semiconductor device according to any one of claims 1 to 5, characterized by comprising the steps of:
the first step is as follows: manufacturing LDMOS basic device structures comprising a drift region, a body region, a drain contact region and a source region on the surfaces of two silicon wafers;
the second step is that: forming a buried oxide layer (8) on the surface of the device by deposition or thermal growth;
the third step: forming a via in the buried oxide layer (8) by means of an etching technique in contact with the underlying silicon layer;
the fourth step: depositing or thermally growing silicon in the via and to the upper surface of the buried oxide layer (8);
the fifth step: growing an epitaxial silicon layer on the surface of the buried oxide layer (8) on the basis of the silicon grown from the through hole;
and a sixth step: and manufacturing a device structure of the upper LDMOS in the epitaxial silicon layer to finally form the double-layer SOI device.
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| CN113921610B (en) * | 2021-09-22 | 2023-06-30 | 杭州芯迈半导体技术有限公司 | LDMOS device structure and manufacturing method thereof |
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| US9231083B2 (en) * | 2012-06-29 | 2016-01-05 | Freescal Semiconductor Inc. | High breakdown voltage LDMOS device |
| US9698024B2 (en) * | 2012-12-06 | 2017-07-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Partial SOI on power device for breakdown voltage improvement |
| CN105097923A (en) * | 2014-05-22 | 2015-11-25 | 上海北京大学微电子研究院 | Double-buried layer SOI high-voltage device |
| CN105304693B (en) * | 2015-07-13 | 2018-07-10 | 电子科技大学 | A kind of manufacturing method of LDMOS device |
| US20170207177A1 (en) * | 2016-01-18 | 2017-07-20 | Silanna Asia Pte Ltd. | Quasi-Lateral Diffusion Transistor with Diagonal Current Flow Direction |
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2018
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