CN103745996A - Lateral power device with partially insulated buried layer and manufacturing method - Google Patents
Lateral power device with partially insulated buried layer and manufacturing method Download PDFInfo
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- CN103745996A CN103745996A CN201310744626.9A CN201310744626A CN103745996A CN 103745996 A CN103745996 A CN 103745996A CN 201310744626 A CN201310744626 A CN 201310744626A CN 103745996 A CN103745996 A CN 103745996A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a lateral power device with a partially insulated buried layer. The lateral power device with the partially insulated buried layer comprises a supporting substrate, an insulated buried layer which is arranged on the surface of the supporting substrate and an active layer which is arranged on the surface of the insulated buried layer. The insulated buried layer comprises a doped window. The supporting substrate comprises a first doped buried layer and a second doped buried layer, wherein the first doped buried layer is arranged below a drain region, the second doped buried layer is arranged below a source region and the distance from the second doped buried layer to the insulated buried layer is larger than the distance from the first doped buried layer to the insulated buried layer. In order to realize the lateral power device with the partially insulated buried layer, the invention additionally provides a manufacturing method, which is characterized in that a dual buried layer is formed in the supporting substrate through two times of ion implantation and the surface of the supporting substrate is etched to form the doped window. The lateral power device with the partially insulated buried layer and the manufacturing method have the advantages that the breakdown voltage of the device is improved, the produced heat can be dissipated from the substrate through the doped window, the heat dissipation is accelerated and the reliability of the device is improved.
Description
Technical field
The present invention relates to a kind of lateral power with SI semi-insulation buried regions and manufacture method, particularly a kind of transverse diffusion metal oxide semiconductor device with SI semi-insulation buried regions and manufacture method, belong to microelectronics and solid electronics technical field.
Background technology
Power integrated circuit also claims high voltage integrated circuit sometimes, it is the important branch that hyundai electronics is learned, can be various power conversions and energy processing unit provides the new-type circuit of high speed, high integration, low-power consumption and anti-irradiation, is widely used in many key areas such as the current consumption fields such as electric control system, automotive electronics, display device driving, communication and illumination and national defence, space flight.The rapid expansion of its range of application, also has higher requirement to the high tension apparatus of its core.
Because power integrated circuit usually combines high-voltage power transistor, controls the functions such as transducer and single logic function, so high tension apparatus and Low-Voltage Logic Devices must be integrated on chip piece.Silicon-on-insulator is as a kind of desirable medium isolated material, can effectively realize high and low power model, and the isolation between high-low voltage device, thoroughly eliminate electrical interference, simplify the structural design of device, and silicon-on-insulator isolated area area to tie isolation little, greatly saved die area, reduced parasitic capacitance, easily integrated different circuit and device.Therefore, soi process is applied to high tension apparatus and power integrated circuit and has obvious advantage and have wide practical use.
The IC product of the above silicon-on-insulator high voltage power device of integrated 600V is widely used in fluorescent lamp, the fields such as Switching Power Supply control.Compare with body silicon high-voltage device, conventional silicon-on-insulator high tension apparatus, due to the existence of its dielectric buried layer, has stoped depletion layer to be expanded to substrate, and its longitudinal puncture voltage is lower.Conventionally the design of 200V and following silicon-on-insulator high tension apparatus thereof is relatively easy, and the design difficulty of the above product of 600V is larger.The puncture voltage of device is by laterally withstand voltage and longitudinal withstand voltage common decision, horizontal withstand voltage can acquisition by increase drift region length.The longitudinal withstand voltage thickness that is proportional to oxygen buried layer and top layer silicon of device, increases top layer silicon and can cause isolation difficulty, increases oxygen buried layer thickness and can cause heat dissipation problem.Also there is another major issue in silicon-on-insulator power device, the thermal conductivity that is exactly silicon dioxide only has one of percentage of body silicon, power device relates to high-voltage large current, so during ON state, body silicon device can scatter heat by substrate, and silicon-on-insulator substrate is due to the existence of oxygen buried layer, make the very slow of heat dissipation, because heat accumulates in tagma, easily cause a lot of integrity problems, even can cause metal melting, thoroughly destroy device.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of transverse diffusion metal oxide semiconductor device with SI semi-insulation buried regions and manufacture method, electric field can be introduced to substrate, avoid electric field to concentrate, improve the puncture voltage of device, and can the heat of generation be shed from substrate by doping window, accelerate heat dissipation, improve the reliability of device.
In order to address the above problem, the invention provides a kind of lateral power with SI semi-insulation buried regions, comprise have the first conduction type support substrates, be positioned at the insulating buried layer on described support substrates surface and be positioned at the active layer on described insulating buried layer surface; Described active layer comprises grid region, lays respectively at source region and the drain region of both sides, described grid region, and described source region and described drain region have the second conduction type; Described insulating buried layer comprises doping window, and described doping window is positioned at below, described drain region, and described doping window is filled with the semi-conducting material with the first conduction type; Described support substrates comprises the first buried dopant layer and the second buried dopant layer, described the first buried dopant layer is positioned at the below in described drain region, described the second buried dopant layer is positioned at below, described source region, described the second buried dopant layer is greater than described the first buried dopant layer to the distance of described insulating buried layer to the distance of described insulating buried layer, and described the first buried dopant layer and described the second buried dopant layer all have the second conduction type.
Alternatively, described active layer also comprises well region and drift region, and described well region is positioned under described grid region, and described well region has the first conduction type, and described drift region is between described well region and described drain region, and described drift region has the second conduction type.
Alternatively, described the first conduction type is N-type, and described the second conduction type is P type.
Alternatively, described the first conduction type is P type, and described the second conduction type is N-type.
The present invention also provides a kind of manufacture method of the lateral power with SI semi-insulation buried regions, comprises the steps: to provide a support substrates with the first conduction type; On described support substrates surface, carry out Implantation for the first time, at the region opposite position of intending formation drain region, form first buried dopant layer with the second conduction type; On described support substrates surface, carry out Implantation for the second time, at the region opposite position of intending formation source region, form second buried dopant layer with the second conduction type, the Implantation degree of depth is greater than the Implantation degree of depth for the first time for the second time; Support substrates surface opposite position above described the second buried dopant layer carries out etching; In described etch areas, deposit and form insulating buried layer; Described support substrates and a device substrate bonding; Described in attenuate, device substrate forms active layer.
Alternatively, the manufacture method of the described lateral power with SI semi-insulation buried regions, is also included in for the second time and anneals after Implantation.
The invention has the advantages that, this device, has increased by 2 layers of buried dopant layer and in insulating buried layer, has formed doping window on the basis with the transverse diffusion metal oxide semiconductor device of insulating buried layer in traditional part in support substrates.In the 2 layers of buried dopant layer adding and insulating buried layer, form the PN junction that doping window has formed 3 transoids in support substrates, in order to bear a part of longitudinal electric field, and modulate drift region electric field, surface potential is introduced to support substrates, can reduce surface field, avoid puncturing in advance, improving the puncture voltage of device, and, can the heat of generation be shed from support substrates by doping window, accelerate heat dissipation, improve the reliability of device.
Accompanying drawing explanation
Accompanying drawing 1 illustrates according to the schematic diagram of the lateral power with SI semi-insulation buried regions of embodiment.
Accompanying drawing 2 to accompanying drawing 13 illustrates according to the process chart of the manufacture method of the lateral power with SI semi-insulation buried regions of embodiment.
Embodiment
Below in conjunction with accompanying drawing, to provided by the invention, with the lateral power of SI semi-insulation buried regions and the embodiment of manufacture method, elaborate.
With reference to being according to the schematic diagram of the lateral power with SI semi-insulation buried regions of this embodiment shown in accompanying drawing 1, comprising P type support substrates 15, be positioned at the insulating buried layer on described P type support substrates 15 surfaces and be positioned at the active layer 18 on described insulating buried layer surface; Described active layer 18 comprises grid region 3, lays respectively at source region 2 and the drain region 7 of both sides, described grid region, and described source region 2 is N-type doping with described drain region 7; Described insulating buried layer comprises buried oxide region 12 and P type window 11, and described P type window 11 is positioned at 7 belows, described drain region; Described P type support substrates comprises: the first n type buried layer 14 and the second n type buried layer 13, described the first n type buried layer 14 is positioned at the below in described drain region 7, described the second n type buried layer 13 is positioned at 2 belows, described source region, and described the second n type buried layer 13 is greater than described the first n type buried layer 14 to the distance of described insulating buried layer to the distance of described insulating buried layer.
Wherein, described active layer 18 also comprises: field oxide 4, P trap 10, N-type drift region 8, source metal 1, drain metal 6 and gate metal 5, and described P trap 10 is positioned under described grid region 3, and described N-type drift region 8 is between described P trap 10 and described drain region 7.
Wherein, should also comprise P type body contact zone 9 with the lateral power of SI semi-insulation buried regions, it is other that described P type body contact zone 9 is positioned at described source region 2, contacts with described P trap 10, and the unnecessary electric charge of assembling for drawing P trap 10, avoids floater effect.
The operation principle of the lateral power with SI semi-insulation buried regions provided by the invention is as follows: when source electrode and grid short circuit, when drain terminal adds voltage, horizontal direction at device, voltage concentrates on the P trap 10 of source and the reverse PN junction of N-type drift region 8 formation, electric field concentrates on the reverse PN junction of P type window 11 formation in the vertical, voltage increase along with drain terminal, P type support substrates will all exhaust near drain terminal place, electromotive force drops on the first n type buried layer 14, and the equipotential forming by the first n type buried layer 14 is introduced electromotive force the P type support substrates 15 of source electrode below, along with drain voltage further increases, P type support substrates 15 can exhaust gradually, electromotive force is fallen on N-type the second buried regions 13, electromotive force further can be introduced to support substrates.When leaking pressure increase, 2 layers of P resilient coating and 2 layers of n type buried layer are realized and entirely being exhausted.When drift region exhausts entirely, device withstand voltage reaches maximum.
Lateral power with SI semi-insulation buried regions provided by the invention is introduced support substrates by surface potential, can reduce surface field, avoid puncturing in advance, improving the puncture voltage of device, and, can the heat of generation be shed from support substrates by doping window, accelerate heat dissipation, improve the reliability with the lateral power of SI semi-insulation buried regions.This device high-pressure section can bear more than 800V withstand voltage under 60 microns of drift region length, and possesses the ON resistance lower than traditional devices, better heat radiation.
Below describe in detail accompanying drawing 2 to shown in accompanying drawing 13 according to the manufacture method of the lateral power with SI semi-insulation buried regions of this specific embodiment.The manufacture method of the lateral power with SI semi-insulation buried regions of the present invention at least comprises the following steps:
Shown in accompanying drawing 2, provide a P type support substrates 15.In this embodiment.Described semiconductor is monocrystalline silicon.In other execution mode, described semiconductor can be also germanium silicon, strained silicon and other compound semiconductors, as gallium nitride or GaAs etc.Also can be the MULTILAYER COMPOSITE substrat structure that semi-conducting material above-mentioned and that other are common forms.
Shown in accompanying drawing 3, on the surface of described P type support substrates 15, form patterned the first mask layer 16, form the first Implantation window 19; Take described the first mask layer 16 as mask carries out Implantation for the first time, adopt phosphonium ion to inject and form the first n type buried layer 14.
Wherein, ROM mask programmable read-only memory Implantation is whole silicon chip to be carried out to blanket type equably inject, and the masking film of Implantation can be SiO
2film can be also other films such as photoresist.Mask mode is that production efficiency is high for the advantage of adulterating, and equipment is relatively simple, control easily, so application is relatively early, and technique comparative maturity.
Shown in accompanying drawing 4, remove the first mask layer 16; On the surface of described P support substrates 15, form patterned the second mask layer 17, form the second Implantation window 20; Described the second mask layer 17 of take carries out Implantation for the second time as mask, and the Implantation degree of depth is greater than the Implantation degree of depth for the first time for the second time, adopts phosphonium ion to inject and forms the second n type buried layer 13.
Shown in accompanying drawing 5, remove the second mask layer 17, and anneal, thereby form the two buried regions of substrate.Because the silicon chip that adopts ion implantation technique to adulterate can produce lattice damage, so it is annealed and is conducive to improve device performance, make the impurity injecting proceed to displacement position to realize electricity activation.
Shown in accompanying drawing 6, above described P type support substrates 15 surfaces, the second n type buried layer 13, opposite position carries out surface etch, forms P type window 11.
Shown in accompanying drawing 7, the etching place deposition of silica on described P type support substrates 15 surfaces, forms oxygen buried layer 12, and oxygen buried layer is discontinuous insulation buried regions, contacts with P type window 11.
Shown in accompanying drawing 8, described P type support substrates 15 and a wafer bonding, silicon chip forms active layer 18 described in attenuate.
Shown in accompanying drawing 9, on described active layer 18 surfaces and be positioned at above the first n type buried layer 14, carry out shallow Doping Phosphorus injection, form N-type drift region 8.Utilize repeatedly Implantation mode to the described active layer 18 part ion B Implanteds of surface except N-type drift region 8, form P trap 10.
Shown in accompanying drawing 10, at described active layer 18 superficial growth field oxides 4, and on gate oxidation material, depositing polysilicon, doping form polysilicon gate material, on P trap 10, near one end of N-type drift region 8, produce grid region 3.
Shown in accompanying drawing 11, above described the second n type buried layer 13, by Implantation organizator contact zone 9 and source region 2 on P trap 10.
Shown in accompanying drawing 12, above described the first n type buried layer 14, by Implantation formation drain region, one end 7 away from grid region on N-type drift region 8, thereby complete the making of active layer 18.
Wherein, make P trap 10, grid region 3, source region 2, body contact zone 9 and drain region 7 and adopt the conventional semiconductor technologies such as Implantation, etching, the present embodiment is only a kind of preferred step method, while specifically making, also can have other variation.
Shown in accompanying drawing 13, at active layer 18 upper surfaces, cover field oxide.On described field oxide, etch window, and carve the contact hole in source region 2, drain region 7 and grid region 3, then depositing metal carry out etching, form source metal 1, drain metal 6 and the gate metal 5 of LDMOS transistor, finally, deposit silicon nitride, generates passivation layer.
In sum, the present invention has overcome the problems such as the electric field of traditional transverse diffusion metal oxide semiconductor device with SI semi-insulation buried regions is concentrated, heat dissipation is slow, on the basis of traditional devices, in support substrates, increased by 2 layers of buried dopant layer and in insulating buried layer, formed doping window.In the 2 layers of buried dopant layer adding and insulating buried layer, form the PN junction that doping window has formed 3 transoids in support substrates, in order to bear a part of longitudinal electric field, and modulate drift region electric field, surface potential is introduced to support substrates, can reduce surface field, avoid puncturing in advance, improving the puncture voltage of device, and, can the heat of generation be shed from support substrates by doping window, accelerate heat dissipation, improve the reliability with the lateral power of SI semi-insulation buried regions.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. with a lateral power for SI semi-insulation buried regions, comprise have the first conduction type support substrates, be positioned at the insulating buried layer on described support substrates surface and be positioned at the active layer on described insulating buried layer surface;
Described active layer comprises grid region, lays respectively at source region and the drain region of both sides, described grid region, and described source region and described drain region have the second conduction type;
It is characterized in that, described insulating buried layer comprises doping window, and described doping window is positioned at below, described drain region, and described doping window is filled with the semi-conducting material with the first conduction type;
Described support substrates comprises the first buried dopant layer and the second buried dopant layer, described the first buried dopant layer is positioned at the below in described drain region, described the second buried dopant layer is positioned at below, described source region, described the second buried dopant layer is greater than described the first buried dopant layer to the distance of described insulating buried layer to the distance of described insulating buried layer, and described the first buried dopant layer and described the second buried dopant layer all have the second conduction type.
2. the lateral power with SI semi-insulation buried regions according to claim 1, is characterized in that, described active layer also comprises well region and drift region; Described well region is positioned under described grid region, and described well region has the first conduction type; Described drift region is between described well region and described drain region, and described drift region has the second conduction type.
3. the lateral power with SI semi-insulation buried regions according to claim 1, is characterized in that, described the first conduction type is N-type, and described the second conduction type is P type.
4. the lateral power with SI semi-insulation buried regions according to claim 1, is characterized in that, described the first conduction type is P type, and described the second conduction type is N-type.
5. with a manufacture method for the lateral power of SI semi-insulation buried regions, it is characterized in that, comprise the steps:
One support substrates with the first conduction type is provided;
On described support substrates surface, carry out Implantation for the first time, at the region opposite position of intending formation drain region, form first buried dopant layer with the second conduction type;
On described support substrates surface, carry out Implantation for the second time, at the region opposite position of intending formation source region, form second buried dopant layer with the second conduction type, the Implantation degree of depth is greater than the Implantation degree of depth for the first time for the second time;
Support substrates surface opposite position above described the second buried dopant layer carries out etching;
In etch areas, deposit and form insulating buried layer;
Described support substrates and a device substrate bonding;
Described device substrate attenuate forms active layer.
6. the manufacture method of the lateral power with SI semi-insulation buried regions according to claim 5, is characterized in that, is also included in for the second time and anneals after Implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310744626.9A CN103745996B (en) | 2013-12-31 | 2013-12-31 | With lateral power and the making method of part insulation buried regions |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310744626.9A CN103745996B (en) | 2013-12-31 | 2013-12-31 | With lateral power and the making method of part insulation buried regions |
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| Publication Number | Publication Date |
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| CN103745996A true CN103745996A (en) | 2014-04-23 |
| CN103745996B CN103745996B (en) | 2016-06-01 |
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