CN103441131A - Partially-depleted silicon-on-insulator device structure - Google Patents
Partially-depleted silicon-on-insulator device structure Download PDFInfo
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- CN103441131A CN103441131A CN2013103858931A CN201310385893A CN103441131A CN 103441131 A CN103441131 A CN 103441131A CN 2013103858931 A CN2013103858931 A CN 2013103858931A CN 201310385893 A CN201310385893 A CN 201310385893A CN 103441131 A CN103441131 A CN 103441131A
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Abstract
The invention provides a partially-depleted silicon-on-insulator device structure. The partially-depleted silicon-on-insulator device structure comprises a semiconductor substrate, a device active area, a grid and a body contact active area. The semiconductor substrate comprises a bottom layer substrate, an insulation area buried layer and an upper layer substrate, wherein the bottom layer substrate, the insulation area buried layer and the upper layer substrate are sequentially stacked from bottom to top. The device active area is placed in the upper layer substrate and comprises a body region, a source region and a drain region. The grid stretches cross the device active area, the body region is placed below the grid, and the source region and the drain region are placed on the two sides of the grid respectively. The body contact active area is placed in the portion, on one side of the device active area in the width direction, of the upper layer substrate, the body contact active area is isolated from the drain region or the source region through a shallow insulation area, the shallow insulation area does not make contact with the insulation area buried layer, and the grid is electrically connected with the body contact active area. According to the partially-depleted silicon-on-insulator device structure, the evenness of starting of a partially-depleted silicon-on-insulator dynamic threshold transistor can be improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of part depletion SOI device structure.
Background technology
Silicon-on-insulator (silicon on insulator, abbreviation SOI) in technology, device only is manufactured in the very thin silicon fiml in top layer, between at the bottom of device and back lining, by the insulation layer buried regions of monoxide, isolated, the parasitic capacitance of this structure is little, makes the SOI device have the characteristics of high-speed and low-power consumption.Because the Fully dielectric isolation of SOI cmos device has thoroughly been eliminated the parasitic latch-up of bulk-Si CMOS device, the SOI Fully dielectric isolation makes that the integration density of SOI technology is high, radiation resistance good, so the SOI technology is widely used in the fields such as radio frequency, high pressure and anti-irradiation.
Whether SOI MOS device exhausts and is divided into partial depletion SOI (PDSOI) and full-exhaustion SOI (FDSOI) according to tagma.Wherein, the tagma of partial depletion SOI MOS does not exhaust fully, makes tagma in vacant state, and the electric charge that ionization by collision produces can't be removed rapidly, and this can cause the distinctive floater effect of SOI MOS.The electron-hole pair produced in the drain terminal ionization by collision for SOI NMOS channel electrons, hole flows to tagma, SOI MOS floater effect causes hole to accumulate in tagma, thereby raise body potential, make the threshold voltage of SOINMOS reduce leakage current increase then, cause the output characteristic curve of device that warping phenomenon is arranged, this phenomenon is called the Kink effect.The Kink effect produces many adverse influences to device and circuit performance and reliability, when device designs, should avoid as far as possible.To SOI PMOS, because the ionization rate in hole is lower, the electron-hole pair that ionization by collision produces is far below SOI NMOS, and therefore, the Kink effect in SOI PMOS is not obvious.
The problem existed in order to solve partial depletion SOI NMOS, prior art adopts the method for body contact (body contact) that " body " connect to fixed potential (source ground connection) usually.Fig. 1 is the vertical view of part depletion SOI device structure of the prior art, the profile that Fig. 2 is AA' along the line in Fig. 1.Part depletion SOI device structure 100 of the prior art comprises Semiconductor substrate 101, device active region 139 (zone shown in the dotted line frame in Fig. 1), grid 140, body contact active area 150.Wherein, described Semiconductor substrate 101 comprises at the bottom of the back lining stacked gradually from bottom to top successively 110, insulation layer buried regions 120 and upper strata substrate 130, described device active region 139 is arranged in described upper strata substrate 130, described device active region 139 has tagma 131, 132He drain region, source region 133, described grid 140 is across on described device active region 139, described tagma 131 is positioned at described grid 140 belows, 132He drain region, described source region 133 lays respectively at the both sides of described grid 140, described body contact active area 150 is arranged in the described upper strata substrate 130 of Width W mono-side of described device active region 132.Described grid 140 contacts active area 150 by the first through hole contact 141 and is communicated with described body, thereby make described grid 140 connect together with described tagma 131, thereby form dynamic threshold MOSFET (Metal Oxide Semiconductor Field Effect Transistor, metal-oxide half field effect transistor).In PDSOI MOSFET, because the thickness of described grid 140 is limited, it is inhomogeneous that the dead resistance 190 in described tagma 131 can make dynamic threshold MOSFET open, thereby affect the performance of device.
Summary of the invention
The object of the present invention is to provide a kind of part depletion SOI device structure, can improve the uniformity of dynamic threshold transistor cut-in voltage in the part depletion SOI device.
For solving the problems of the technologies described above, the invention provides a kind of part depletion SOI device structure, comprising:
Semiconductor substrate, at the bottom of comprising the back lining stacked gradually from bottom to top successively, insulation layer buried regions and upper strata substrate;
Device active region, be arranged in described upper strata substrate, and described device active region has tagma, source region and drain region;
Grid, on described device active region, described tagma is positioned at described grid below, and described source region and drain region lay respectively at the both sides of described grid;
Body contacts active area, is arranged in the described upper strata substrate of Width one side of described device active region, and described body contact active area and described drain region or described source region are isolated by a shallow isolated area, and described shallow isolated area does not contact with described insulating buried layer;
Wherein, described grid contacts the active area electrical connection with described body.
Further, have the first through hole contact in described grid, have at least one the second through hole contact on described body contact active area, described the first through hole contact is connected by interconnection layer with described the second through hole contact.
Further, the length of described grid is greater than the length of described device active region, and described the first through hole contact is arranged in the described grid beyond described device active region.
Further, described interconnection layer is the first metal interconnecting layer.
Further, described shallow isolated area is shallow-trench isolation.
Further, the material of described shallow isolated area is silica.
Further, described tagma contacts active area with body be the doping of P type, and described source region and drain region are the N-type doping, and the doping content in described tagma is lower than the doping content of described body contact active area; Or contact active area with body be N-type doping in described tagma, described source region and drain region are the doping of P type, and the doping content in described tagma is lower than the doping content of described body contact active area.
Further, the dopant dose in described tagma is 1E14cm
-2～1E16cm
-2, the dopant dose of described body contact active area is 1E18cm
-2～1E20cm
-2.
Compared with prior art, part depletion SOI device structure provided by the invention has the following advantages:
In part depletion SOI device structure provided by the invention, described body contact active area is arranged in the described upper strata substrate of Width one side of described device active region, described body contact active area and described drain region or described source region are isolated by a shallow isolated area, described shallow isolated area does not contact with described insulating buried layer, described grid contacts the active area electrical connection with described body, compared with prior art, adopt described shallow isolated area to realize being connected of described grid and described tagma, with at described grid, described body contact active area and described tagma form dynamic threshold transistor, because the dead resistance in described tagma is uniformly distributed, thereby can improve the uniformity that part depletion silicon-on-insulator dynamic threshold transistor is opened.
The accompanying drawing explanation
Fig. 1 is the vertical view of part depletion SOI device structure of the prior art;
The profile that Fig. 2 is AA' along the line in Fig. 1;
Fig. 3 is the vertical view of the part depletion SOI device structure of one embodiment of the invention;
The profile that Fig. 4 is BB' along the line in Fig. 3;
The profile that Fig. 5 is CC' along the line in Fig. 3;
Fig. 6 is the vertical view of the part depletion SOI device structure of another embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, part depletion SOI device structure of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been meaned, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
With way of example, the present invention is more specifically described with reference to accompanying drawing in the following passage.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is to provide a kind of part depletion SOI device structure, comprising: Semiconductor substrate, at the bottom of comprising the back lining stacked gradually from bottom to top successively, insulation layer buried regions and upper strata substrate; Device active region, be arranged in described upper strata substrate, and described device active region has tagma, source region and drain region; Grid, on described device active region, described tagma is positioned at described grid below, and described source region and drain region lay respectively at the both sides of described grid; Body contacts active area, is arranged in the described upper strata substrate of Width one side of described device active region, and described body contact active area and described drain region or described source region are isolated by a shallow isolated area, and described shallow isolated area does not contact with described insulating buried layer; Wherein, described grid contacts the active area electrical connection with described body.Adopt described shallow isolated area to realize being connected of described grid and described tagma, in described grid, described body contact active area and described tagma, to form dynamic threshold transistor, because the dead resistance in described tagma is uniformly distributed, thereby can improve the uniformity that part depletion silicon-on-insulator dynamic threshold transistor is opened.
Illustrate the part depletion SOI device structure of the present embodiment below in conjunction with Fig. 3-Fig. 5, wherein, Fig. 3 is the vertical view of the part depletion SOI device structure of one embodiment of the invention, the profile that Fig. 4 is BB' along the line in Fig. 3, the profile that Fig. 5 is CC' along the line in Fig. 3.
As shown in Figure 3, in the present embodiment, part depletion SOI device structure 200 comprises Semiconductor substrate 201, device active region 239 (zone as shown in Fig. 3 dotted line frame), grid 240 and body contact active area 250.
Described Semiconductor substrate 201 comprises at the bottom of the back lining stacked gradually from bottom to top successively 210, insulation layer buried regions 220 and upper strata substrate 230, described device active region 239 is arranged in described upper strata substrate 230, described device active region 239 has tagma 231, 232He drain region, source region 233, described grid 240 is across on described device active region 239, described tagma 231 is positioned at described grid 240 belows, 232He drain region, described source region 233 lays respectively at the both sides of described grid 240, described body contact active area 250 is arranged in the described upper strata substrate 230 of Width (W direction) side of described device active region 239, described body contact active area 250 is isolated by a shallow isolated area 260 with described drain region 233, described shallow isolated area 260 does not contact with described insulating buried layer 220, wherein, described grid 240 contacts active area 250 electrical connections with described body.As shown in Figure 4, in the present embodiment, the degree of depth of described shallow isolated area 260 is shallower than described drain region 233 and contacts active area 250 with described body, but, the degree of depth of described shallow isolated area 260 can also be deeper than described drain region 233 and contact active area 250 with described body, as long as described shallow isolated area 260 does not contact with described insulating buried layer 220, also within thought range of the present invention.Preferably, described Semiconductor substrate 201 also comprises necessary structure such as isolated area 234 grades, and this common practise that is this area, do not do and repeat at this.
Adopt described shallow isolated area 260 to realize being connected of described grid 240 and described tagma 231, in described grid 240, described body contact active area 250 and described tagma 231, to form dynamic threshold transistors; And, because described body contacts the described upper strata substrate 230 that active area 250 is arranged in Width W mono-side of described device active region 239, so, the dead resistance 290 in described tagma 231 is arranged side by side in a side in the close described drain region 233 of Width (W direction) of described device active region 239, as shown in Figure 3, the described dead resistance 290 be arranged side by side is uniformly distributed, thereby improves the uniformity of the dynamic threshold transistor unlatching formed in part depletion SOI device structure 200.
In the present embodiment, there is the first through hole contact 241 in described grid 240, there is at least one the second through hole contact 251 on described body contact active area 250, described the first through hole contact 241 is connected by interconnection layer with described the second through hole contact 251, thereby guarantees that described grid 240 contacts active area 250 electrical connections with described body.Preferably, the length of described grid 240 is greater than the length of described device active region 239, and described the first through hole contact 241 is arranged in the described grid 240 beyond described device active region 239.But the shape of described grid 240 is not limited to the shape shown in Fig. 3, the shape of described grid 240 can also be the shape such as T-shaped.
In the present embodiment, described interconnection layer is the first metal interconnecting layer 270, but, it is the first metal interconnecting layer 270 that described interconnection layer is not limited to, it can also be second metal interconnecting layer etc., as long as can realize that described grid 240 contacts active area 250 electrical connections with described body, also within thought range of the present invention.
Preferably, described shallow isolated area 260 is shallow-trench isolation, can realize undersized effective isolation, but described shallow isolated area 260 is carrying out local oxide isolation, also within thought range of the present invention.In the present embodiment, the material of described shallow isolated area 260 is silica, but so long as can realize that the material of electrical isolation all can.
In the present embodiment, described part depletion SOI device structure 200 is the NMOS pipe, described tagma 231 contacts active area 250 for the doping of P type with body, 232He drain region 233, described source region is the N-type doping, the doping content in described tagma 231 is lower than the doping content of described body contact active area 250, but described part depletion SOI device structure 200 can also be managed for PMOS, described tagma 231 contacts active area 250 for the doping of P type with body, 232He drain region 233, described source region is for the N-type doping, also within thought range of the present invention.Preferably, the dopant dose in described tagma 231 is 1E14cm
-2～1E16cm
-2, preferred 1E15cm
-2, the dopant dose of described body contact active area 250 is 1E18cm
-2～1E20cm
-2, preferred 1E19cm
-2.
The present invention is not limited to above embodiment, and wherein, described body contact active area 250 is not limited to be arranged in the described upper strata substrate 230 of the Width (W direction) of described device active region 239 near a side in described drain region 233.Described body contact active area 250 can also be arranged in the described upper strata substrate 230 of the Width (W direction) of described device active region 239 near a side in described source region 232, described body contact active area 250 is isolated by a shallow isolated area 260 with described source region 232, can also realize that the dead resistance 290 in described tagma 231 is arranged side by side in a side in the close described source region 232 of Width (W direction) of described device active region 239, the described dead resistance 290 be arranged side by side is uniformly distributed, thereby improve the uniformity of the unlatching of the dynamic threshold transistor formed in part depletion SOI device structure 200.In addition, the Width (W direction) that described body contact active area 250 can also lay respectively at described device active region 239 is near in the side in described source region 232 and the described upper strata substrate 230 near the side in described drain region 233, as shown in Figure 6.Fig. 6 is the vertical view of the part depletion SOI device structure of another embodiment of the present invention, and in Fig. 6, reference number means the parts that the statement identical with Fig. 3 is identical with one embodiment of the invention.As shown in Figure 6, the Width (W direction) that described body contact active area 250 lays respectively at described device active region 239 is near in the side in described source region 232 and the described upper strata substrate 230 near the side in described drain region 233, described body contact active area 250 is isolated by a shallow isolated area 260 with described source region 232, described body contact active area 250 also is isolated by a shallow isolated area 260 with described drain region 233, can also realize that the dead resistance 290 in described tagma 231 is arranged side by side near a side in described source region 232 and a side in close described drain region 233 at the Width (W direction) of described device active region 239, the described dead resistance 290 be arranged side by side is uniformly distributed, thereby improve the uniformity of the unlatching of the dynamic threshold transistor formed in part depletion SOI device structure 200.
In sum, the invention provides a kind of part depletion SOI device structure, in part depletion SOI device structure provided by the invention, described body contact active area is arranged in the described upper strata substrate of Width one side of described device active region, described body contact active area and described drain region or described source region are isolated by a shallow isolated area, described shallow isolated area does not contact with described insulating buried layer, and described grid contacts the active area electrical connection with described body.Compared with prior art, part depletion SOI device structure provided by the invention has the following advantages:
Adopt described shallow isolated area to realize being connected of described grid and described tagma, in described grid, described body contact active area and described tagma, to form dynamic threshold transistor, because the dead resistance in described tagma is uniformly distributed, thereby can improve the uniformity that part depletion silicon-on-insulator dynamic threshold transistor is opened.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. a part depletion SOI device structure comprises:
Semiconductor substrate, at the bottom of comprising the back lining stacked gradually from bottom to top successively, insulation layer buried regions and upper strata substrate;
Device active region, be arranged in described upper strata substrate, and described device active region has tagma, source region and drain region;
Grid, on described device active region, described tagma is positioned at described grid below, and described source region and drain region lay respectively at the both sides of described grid;
Body contacts active area, is arranged in the described upper strata substrate of Width one side of described device active region, and described body contact active area and described drain region or described source region are isolated by a shallow isolated area, and described shallow isolated area does not contact with described insulating buried layer;
Wherein, described grid contacts the active area electrical connection with described body.
2. part depletion SOI device structure as claimed in claim 1, it is characterized in that, have the first through hole contact in described grid, have at least one the second through hole contact on described body contact active area, described the first through hole contact is connected by interconnection layer with described the second through hole contact.
3. part depletion SOI device structure as claimed in claim 2, is characterized in that, the length of described grid is greater than the length of described device active region, and described the first through hole contact is arranged in the described grid beyond described device active region.
4. part depletion SOI device structure as claimed in claim 2, is characterized in that, described interconnection layer is the first metal interconnecting layer.
5. part depletion SOI device structure as claimed in claim 1, is characterized in that, described shallow isolated area is shallow-trench isolation.
6. part depletion SOI device structure as claimed in claim 5, is characterized in that, the material of described shallow isolated area is silica.
7. part depletion SOI device structure as claimed in claim 1, it is characterized in that, described tagma contacts active area with body be the doping of P type, and described source region and drain region are the N-type doping, and the doping content in described tagma is lower than the doping content of described body contact active area; Or contact active area with body be N-type doping in described tagma, described source region and drain region are the doping of P type, and the doping content in described tagma is lower than the doping content of described body contact active area.
8. part depletion SOI device structure as claimed in claim 7, is characterized in that, the dopant dose in described tagma is 1E14cm
-2～1E16cm
-2, the dopant dose of described body contact active area is 1E18cm
-2～1E20cm
-2.
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Cited By (6)
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| CN104752429A (en) * | 2015-04-17 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Insulator-on-silicon (SOI) radio-frequency device structure |
| CN105047720A (en) * | 2015-08-11 | 2015-11-11 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switch device structure |
| CN105280715A (en) * | 2015-11-30 | 2016-01-27 | 上海华虹宏力半导体制造有限公司 | SOI body contact device structure |
| CN106935634A (en) * | 2015-12-30 | 2017-07-07 | 意法半导体(克洛尔2)公司 | Low noise MOS transistor and related circuit |
| CN112054025A (en) * | 2020-08-31 | 2020-12-08 | 中国科学院微电子研究所 | Serial SOI MOSFET device structure and preparation method thereof |
| CN114068686A (en) * | 2020-08-06 | 2022-02-18 | 格芯(美国)集成电路科技有限公司 | Device with staggered body contacts |
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| CN102208449A (en) * | 2011-05-24 | 2011-10-05 | 上海宏力半导体制造有限公司 | Silicon-on-insulator (SOI) body contact metal oxide semiconductor (MOS) transistor and forming method thereof |
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| CN106935634A (en) * | 2015-12-30 | 2017-07-07 | 意法半导体(克洛尔2)公司 | Low noise MOS transistor and related circuit |
| CN114068686A (en) * | 2020-08-06 | 2022-02-18 | 格芯(美国)集成电路科技有限公司 | Device with staggered body contacts |
| CN112054025A (en) * | 2020-08-31 | 2020-12-08 | 中国科学院微电子研究所 | Serial SOI MOSFET device structure and preparation method thereof |
| CN112054025B (en) * | 2020-08-31 | 2023-11-14 | 中国科学院微电子研究所 | Series SOI MOSFET device structure and preparation method thereof |
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Effective date of registration: 20140504 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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Application publication date: 20131211 |
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