CN112054061B - Body contact structure of partially depleted silicon on insulator and manufacturing method thereof - Google Patents
Body contact structure of partially depleted silicon on insulator and manufacturing method thereof Download PDFInfo
- Publication number
- CN112054061B CN112054061B CN202010867363.0A CN202010867363A CN112054061B CN 112054061 B CN112054061 B CN 112054061B CN 202010867363 A CN202010867363 A CN 202010867363A CN 112054061 B CN112054061 B CN 112054061B
- Authority
- CN
- China
- Prior art keywords
- region
- trench isolation
- shallow trench
- body contact
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 40
- 239000010703 silicon Substances 0.000 title claims abstract description 40
- 239000012212 insulator Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 210000000746 body region Anatomy 0.000 claims abstract description 70
- 238000002955 isolation Methods 0.000 claims abstract description 62
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 10
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000008901 benefit Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
Abstract
The invention relates to the technical field of semiconductors, in particular to a body contact structure of partially depleted silicon on insulator and a manufacturing method, wherein the body contact structure of partially depleted silicon on insulator comprises the following components: the semiconductor device comprises a bottom silicon layer, an oxygen-buried layer positioned on the bottom silicon layer, a body region above the oxygen-buried layer, a source region, a drain region, a P+ body contact region and two first shallow trench isolation regions; the body region is positioned in the middle of the upper part of the oxygen burying layer; the source region and the drain region are respectively positioned at two opposite ends of the body region, the two first shallow trench isolation regions are respectively embedded into the other opposite ends of the body region, and the depth of the two first shallow trench isolation regions is smaller than that of the body region; the P+ body contact region is located outside the source region and above the buried oxide layer, so that the body region is connected with the P+ body contact region, holes accumulated in the body region can leak to the P+ body contact region, the potential of the body region can be better clamped, the threshold voltage can not be greatly reduced, the parasitic bipolar transistor is not easy to trigger and conduct, and the floating body effect can be well restrained.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a body contact structure of partially depleted silicon on insulator.
Background
Silicon-on-insulator (SOI) refers to a material structure in which a single crystal silicon film is formed over an insulating substrate or separated from a supporting silicon substrate by an insulating layer.
The difference between an SOI device and a bulk silicon device is mainly caused by the introduction of a buried oxide layer (BOX), and is characterized as follows: 1, a buried oxide layer isolates an active region of a device from a substrate; 2, the buried oxide layer replaces the direct contact between the substrate and the source and the drain; 3, the active area is changed into a thin silicon film from the whole substrate, so that compared with the bulk silicon technology, the SOI CMOS technology has the advantages of no latch, high speed, low power consumption, miniaturization, radiation resistance and the like.
The SOI device is classified into a fully depleted device and a partially depleted device, the threshold voltage is very sensitive to the thickness of the silicon film because the silicon film is fully depleted during operation, so the threshold voltage is not easy to control, and the electrical characteristics of the fully depleted SOI device may be affected by the non-uniformity of the silicon film because the silicon film is very thin. Therefore, the partially depleted SOI device is more suitable for mass production application, but a floating body effect can be generated when the partially depleted SOI device works, and the floating body effect can cause a king phenomenon, BJT amplification, drain breakdown voltage reduction, GIDL current increase and the like, so that the performance of the device is seriously affected, and even the device is disabled.
Therefore, how to reduce the floating body effect is a technical problem to be solved.
Disclosure of Invention
The present invention has been made in view of the above problems, and has been made to provide a partially depleted silicon-on-insulator body contact structure and a method of making the same, which overcomes or at least partially solves the above problems.
In one aspect, the invention provides a partially depleted silicon-on-insulator body contact structure comprising:
the semiconductor device comprises a bottom silicon layer, an oxygen-buried layer positioned on the bottom silicon layer, a body region above the oxygen-buried layer, a source region, a drain region, a P+ body contact region and two first shallow trench isolation regions;
the body region is positioned in the middle of the upper part of the oxygen burying layer;
the source region and the drain region are respectively positioned at two opposite ends of the body region, the two first shallow trench isolation regions are respectively embedded into the other opposite ends of the body region, and the depth of the two first shallow trench isolation regions is smaller than that of the body region;
the P+ body contact region is positioned outside the source region and above the oxygen-buried layer and is in contact with the body region.
Further, the depth of the source region and the depth of the drain region are equal to the depth of the body region; or alternatively
The depth of the source region and the depth of the drain region are both smaller than the depth of the body region.
Further, the method further comprises the following steps:
and the grid region is positioned above the middle part of the body region and positioned between the source region and the drain region.
Further, the method further comprises the following steps:
and the metal silicide layer is positioned above the source region and the P+ body contact region and is used for electrically connecting the source region and the P+ body contact region.
Further, the method further comprises the following steps:
and annular second shallow trench isolation regions located above the oxygen-buried layer and outside the two first shallow trench isolation regions, outside the drain region and outside the P+ body contact region, wherein the depth of the second shallow trench isolation region is greater than that of the first shallow trench isolation region, and the depth of the second shallow trench isolation region 109 reaches the oxygen-buried layer.
Further, the source region is an N-type source region, and the drain region is an N-type drain region.
Further, the gate region comprises a gate dielectric layer and a gate electrode positioned on the gate dielectric layer.
Further, the grid electrode is made of polycrystalline silicon material.
In a second aspect, the present invention also provides a method for fabricating a partially depleted silicon-on-insulator body contact structure, comprising:
defining an active region on an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top;
forming first shallow trench isolation regions on two opposite sides of the active region, wherein the depth of the first shallow trench isolation regions is smaller than that of the top silicon layer;
and forming a drain region, a source region and a P+ body contact region in the active region along the length direction of the first shallow trench isolation region, so that a body region is formed between the drain region and the source region, wherein the source region is contacted with the P+ body contact region, and the P+ body contact region is contacted with the body region.
Further, after forming the first shallow trench isolation region on opposite sides of the active region, the method further comprises:
and forming annular second shallow trench isolation regions surrounding the outer sides of the first shallow trench isolation regions, the outer sides of the drain regions and the outer sides of the P+ body contact regions on the SOI substrate, wherein the depth of the second shallow trench isolation regions is larger than that of the first shallow trench isolation regions and reaches the oxygen-buried layer.
One or more technical solutions in the embodiments of the present invention at least have the following technical effects or advantages:
the invention provides a body contact structure of partially depleted silicon on insulator, which comprises a bottom silicon layer, an oxygen-buried layer positioned on the bottom silicon layer, a body region, a source region, a drain region, a P+ body contact region and two first shallow trench isolation regions, wherein the body region is positioned in the middle of the upper part of the oxygen-buried layer; the source region and the drain region are respectively positioned at two opposite ends of the body region, the two first shallow trench isolation regions are respectively embedded into the other opposite ends of the body region, and the depth of the two first shallow trench isolation regions is smaller than that of the body region; the P+ body contact region is located outside the source region and above the buried oxide layer, so that the body region is connected with the P+ body contact region, holes accumulated in the body region can leak to the P+ body contact region, the potential of the body region can be better clamped, the threshold voltage can not be greatly reduced, the parasitic bipolar transistor is not easy to trigger and conduct, and the floating body effect can be well restrained.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also throughout the drawings, like reference numerals are used to designate like parts. In the drawings:
FIG. 1 illustrates a schematic top view of a partially depleted silicon-on-insulator body contact structure in accordance with an embodiment of the present invention;
figure 2 illustrates a portion of a partially depleted silicon-on-insulator body contact structure along B-B in accordance with an embodiment of the present invention ’ A directional cross-sectional view;
figure 3 illustrates a partially depleted silicon-on-insulator body contact structure along A-A in accordance with an embodiment of the present invention ’ A directional cross-sectional view;
fig. 4 is a schematic flow chart showing the steps of a method for manufacturing a body contact structure partially depleted of silicon on insulator in a second embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example 1
An embodiment of the present invention provides a body contact structure partially depleted of silicon on insulator, as shown in fig. 1, 2 and 3, comprising:
a bottom silicon layer 101, a buried oxide layer 102 on the bottom silicon layer 101, a body region 103 above the buried oxide layer 102, a source region 104, a drain region 105, a p+ body contact region 106, and two first shallow trench isolation regions 107.
The body region 103 is positioned in the middle of the upper part of the buried oxide layer 102; the source region 104 and the drain region 105 are respectively located at two opposite ends of the body region 103, two first shallow trench isolation regions 107 are embedded into the other opposite ends of the body region 103, and the depth of the two first shallow trench isolation regions is smaller than that of the body region 103; the p+ body contact region 106 is located outside the source region 104 and above the buried oxide layer 102, and contacts the body region 103.
In a specific embodiment, the source region 104 and the drain region 105 in the body contact structure are formed by ion implantation, which may be shallow implantation or deep implantation, specifically, when the source region 104 and the drain region 105 are both shallow implantation, the depth of the source region 104 and the depth of the drain region 105 are both smaller than the depth of the body region 103, and when the source region 104 and the drain region 105 are both deep implantation, the depth of the source region 104 and the depth of the drain region 105 are both equal to the depth of the body region 103.
The source region 104 is an N-type source region, and the drain region 105 is an N-type drain region. The specific doping ions are arsenic and phosphorus.
A gate region 108 over the middle of the body region 103 and between the source region 104 and the drain region 105.
As shown in fig. 2, the gate region 108 includes a gate dielectric layer 1081 and a gate 1082 on the gate dielectric layer 1081.
Wherein the gate 1082 is a polysilicon material.
The gate dielectric layer 1081 is silicon dioxide or a high-k dielectric (e.g., hfO 2 ) A material.
As shown in fig. 1 and 2, when the depth of the source region 104 and the depth of the drain region 105 are smaller than the depth of the body region 103, since the body region 103 is in contact with the p+ body contact region 106, holes accumulated in the body region 103 leak to the p+ body contact region, specifically, holes in the body region 103 under the gate 1072 are released to the p+ body contact region 106 through a portion under the source region 104 according to the nearby principle, and thus, the potential of the body region 103 can be clamped, the threshold voltage is not greatly reduced, and the parasitic bipolar transistor is not easily triggered to be turned on, thereby suppressing the floating body effect.
As shown in fig. 1 and 3, when the depth of the source region 104 and the depth of the drain region 105 are equal to the depth of the body region 103, holes accumulated in the body region 103 leak to the p+ body contact region 107, specifically, holes in the body region 103 under the gate 1072 are communicated with the p+ body contact region through a portion under the first shallow trench isolation region 107, so that the holes are released to the p+ body contact region 106, the potential of the body region 103 is clamped, the threshold voltage is not greatly reduced, and the parasitic bipolar transistor is not easily triggered to turn on, thereby suppressing the floating body effect.
The channel width between the source region 104 and the drain region 105 is unchanged, and current crowding can be effectively avoided.
In an alternative embodiment, the body contact structure further comprises: the metal silicide located above the source region 104 and the p+ body contact region 106 is used to electrically connect the source region 104 and the p+ body contact region 106, when the source region 104 is grounded, the p+ body contact region 106 is also grounded, and holes are released, so that the condition of providing grounding for the contact region is not needed to be provided additionally, and the electrode of the contact region is omitted, thereby greatly saving the area cost of the device.
In an alternative embodiment, the body contact structure further comprises: and annular second shallow trench isolation regions 109 located above the buried oxide layer 102 and outside the two first shallow trench isolation regions 107, outside the drain region 105 and outside the p+ body contact region 107, the depth of the second shallow trench isolation regions 109 being greater than the depth of the first shallow trench isolation regions 107, and the depth of the second shallow trench isolation regions 109 reaching the buried oxide layer 102.
The second shallow trench isolation region 109 is used to isolate the adjacent devices, and ensure the stability of the devices. The device can effectively save the area.
One or more technical solutions in the embodiments of the present invention at least have the following technical effects or advantages:
the invention provides a body contact structure of partially depleted silicon on insulator, which comprises a bottom silicon layer, an oxygen-buried layer positioned on the bottom silicon layer, a body region, a source region, a drain region, a P+ body contact region and two first shallow trench isolation regions, wherein the body region is positioned in the middle of the upper part of the oxygen-buried layer; the source region and the drain region are respectively positioned at two opposite ends of the body region, the two first shallow trench isolation regions are respectively embedded into the other opposite ends of the body region, and the depth of the two first shallow trench isolation regions is smaller than that of the body region; the P+ body contact region is located outside the source region and above the buried oxide layer, so that the body region is connected with the P+ body contact region, holes accumulated in the body region can leak to the P+ body contact region, the potential of the body region can be better clamped, the threshold voltage can not be greatly reduced, the parasitic bipolar transistor is not easy to trigger and conduct, and the floating body effect can be well restrained.
Example two
Based on the same inventive concept, the present invention also provides a method for manufacturing a body contact structure of partially depleted silicon on insulator, as shown in fig. 4, comprising:
s401, defining an active region on an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top;
s402, forming first shallow trench isolation regions on two opposite sides of the active region, wherein the depth of the first isolation regions is smaller than that of the top silicon layer;
s403, forming a drain region, a source region and a P+ body contact region in the active region along the length direction of the first shallow trench isolation region, so that a body region is formed between the drain region and the source region, wherein the source region is contacted with the P+ body contact region, and the P+ body contact region is contacted with the body region.
In forming the first shallow trench isolation region, the isolation oxide may be filled after etching on the top silicon layer.
And forming a drain region, a source region and a P+ body contact region, wherein the body region is formed between the drain region and the source region, arsenic and phosphorus are injected into the drain region and the source region, an N-type source region and an N-type drain region are formed, boron (B) ions are injected into the body region between the drain region and the source region, and the P+ body contact region is boron ions with deeper injection concentration.
In an alternative embodiment, after S402, the method further includes:
and forming annular second shallow trench isolation regions surrounding the outer sides of the first shallow trench isolation regions, the outer sides of the drain regions and the outer sides of the P+ body contact regions on the SOI substrate, wherein the depth of the second shallow trench isolation regions is larger than that of the first shallow trench isolation regions and reaches the oxygen-buried layer. The second shallow trench isolation region is formed by the same process as the first shallow trench isolation region.
In an alternative embodiment, the depth of the source region and the depth of the drain region are both equal to the depth of the body region; or alternatively
The depth of the source region and the depth of the drain region are both smaller than the depth of the body region.
In an alternative embodiment, before S403, the method further includes:
and forming a gate region in the active region.
In an alternative embodiment, after S403, the method further includes:
a metal silicide layer is formed over the source region and the p+ body contact region for electrically connecting the source region and the p+ body contact region.
In an alternative embodiment, the source region is an N-type source region and the drain region is an N-type drain region.
In an alternative embodiment, the gate region includes a gate dielectric layer and a gate electrode on the gate dielectric layer.
In an alternative embodiment, the gate is a polysilicon material.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A partially depleted silicon-on-insulator body contact structure comprising:
the semiconductor device comprises a bottom silicon layer, an oxygen-buried layer positioned on the bottom silicon layer, a body region above the oxygen-buried layer, a source region, a drain region, a P+ body contact region and two first shallow trench isolation regions;
the body region is positioned in the middle of the upper part of the oxygen burying layer;
the source region and the drain region are respectively positioned at two opposite ends of the body region, the two first shallow trench isolation regions are respectively embedded into the other opposite ends of the body region, and the depth of the two first shallow trench isolation regions is smaller than that of the body region;
the P+ body contact region is positioned outside the source region and above the oxygen-buried layer and is in contact with the body region;
further comprises:
the annular second shallow trench isolation region is arranged above the oxygen burying layer and is arranged outside the two first shallow trench isolation regions, outside the drain region and outside the P+ body contact region, the depth of the second shallow trench isolation region is larger than that of the first shallow trench isolation region, and the depth of the second shallow trench isolation region reaches the oxygen burying layer.
2. The body contact structure of claim 1, wherein a depth of the source region and a depth of the drain region are both equal to a depth of the body region; or alternatively
The depth of the source region and the depth of the drain region are both smaller than the depth of the body region.
3. The body contact structure of claim 1, further comprising:
and the grid region is positioned above the middle part of the body region and positioned between the source region and the drain region.
4. The body contact structure of claim 1, further comprising:
and the metal silicide layer is positioned above the source region and the P+ body contact region and is used for electrically connecting the source region and the P+ body contact region.
5. The body contact structure of claim 1, wherein the source region is an N-type source region and the drain region is an N-type drain region.
6. The body contact structure of claim 3, wherein the gate region comprises a gate dielectric layer and a gate electrode on the gate dielectric layer.
7. The body contact structure of claim 6, wherein the gate is a polysilicon material.
8. A method of forming a partially depleted silicon-on-insulator body contact structure, comprising:
defining an active region on an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer from bottom to top;
forming first shallow trench isolation regions on two opposite sides of the active region, wherein the depth of the first shallow trench isolation regions is smaller than that of the top silicon layer;
forming a drain region, a source region and a P+ body contact region in the active region along the length direction of the first shallow trench isolation region, so that a body region is formed between the drain region and the source region, wherein the source region is contacted with the P+ body contact region, and the P+ body contact region is contacted with the body region;
after forming the first shallow trench isolation region on opposite sides of the active region, the method further comprises:
and forming annular second shallow trench isolation regions surrounding the outer sides of the first shallow trench isolation regions, the outer sides of the drain regions and the outer sides of the P+ body contact regions on the SOI substrate, wherein the depth of the second shallow trench isolation regions is larger than that of the first shallow trench isolation regions and reaches the oxygen-buried layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010867363.0A CN112054061B (en) | 2020-08-25 | 2020-08-25 | Body contact structure of partially depleted silicon on insulator and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010867363.0A CN112054061B (en) | 2020-08-25 | 2020-08-25 | Body contact structure of partially depleted silicon on insulator and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112054061A CN112054061A (en) | 2020-12-08 |
| CN112054061B true CN112054061B (en) | 2024-04-05 |
Family
ID=73600239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010867363.0A Active CN112054061B (en) | 2020-08-25 | 2020-08-25 | Body contact structure of partially depleted silicon on insulator and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112054061B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020013700A (en) * | 2000-08-11 | 2002-02-21 | 윤종용 | A SOI MOSFET including a body contact for removing floating body effect and a method for the SOI MOSFET |
| CN101621009A (en) * | 2008-07-02 | 2010-01-06 | 中国科学院微电子研究所 | Method for manufacturing body-contact structure of partially depleted SOI MOSFET |
| CN102254949A (en) * | 2011-08-01 | 2011-11-23 | 上海宏力半导体制造有限公司 | Silicon-on-insulator MOS (metal-oxide-semiconductor) transistor structure |
| CN102598273A (en) * | 2009-10-06 | 2012-07-18 | 国际商业机器公司 | Split level shallow trench isolation for area efficient body contacts in SOI MOSFET |
| CN109742085A (en) * | 2018-11-30 | 2019-05-10 | 中国科学院微电子研究所 | SOI device and preparation method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9230990B2 (en) * | 2014-04-15 | 2016-01-05 | Globalfoundries Singapore Pte. Ltd. | Silicon-on-insulator integrated circuit devices with body contact structures |
| US9685364B2 (en) * | 2014-09-05 | 2017-06-20 | Globalfoundries Singapore Pte. Ltd. | Silicon-on-insulator integrated circuit devices with body contact structures and methods for fabricating the same |
| US10573639B2 (en) * | 2016-02-29 | 2020-02-25 | Globalfoundries Singapore Pte. Ltd. | Silicon controlled rectifier (SCR) based ESD protection device |
-
2020
- 2020-08-25 CN CN202010867363.0A patent/CN112054061B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020013700A (en) * | 2000-08-11 | 2002-02-21 | 윤종용 | A SOI MOSFET including a body contact for removing floating body effect and a method for the SOI MOSFET |
| CN101621009A (en) * | 2008-07-02 | 2010-01-06 | 中国科学院微电子研究所 | Method for manufacturing body-contact structure of partially depleted SOI MOSFET |
| CN102598273A (en) * | 2009-10-06 | 2012-07-18 | 国际商业机器公司 | Split level shallow trench isolation for area efficient body contacts in SOI MOSFET |
| CN102254949A (en) * | 2011-08-01 | 2011-11-23 | 上海宏力半导体制造有限公司 | Silicon-on-insulator MOS (metal-oxide-semiconductor) transistor structure |
| CN109742085A (en) * | 2018-11-30 | 2019-05-10 | 中国科学院微电子研究所 | SOI device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112054061A (en) | 2020-12-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101055710B1 (en) | High Performance Capacitors with Planar Rear Gate CMS | |
| US5554546A (en) | Method of fabricating a high voltage transistor | |
| US20110198726A1 (en) | Semiconductor device and manufacturing method thereof | |
| KR100790257B1 (en) | Semiconductor device and method for the same | |
| US20080258214A1 (en) | Semiconductor Device and Method of Fabricating the Same | |
| EP1083607A2 (en) | High voltage SOI semiconductor device | |
| KR101531882B1 (en) | Semiconductor device and method for manufacturing the same | |
| KR100930150B1 (en) | Semiconductor device and manufacturing method thereof | |
| US9443943B2 (en) | Semiconductor device and fabrication method thereof | |
| KR100529455B1 (en) | Pdsoi type mos transistor and manufacturing method the same | |
| US10217828B1 (en) | Transistors with field plates on fully depleted silicon-on-insulator platform and method of making the same | |
| US10256340B2 (en) | High-voltage semiconductor device and method for manufacturing the same | |
| US8723256B1 (en) | Semiconductor device and fabricating method thereof | |
| US9231081B2 (en) | Method of manufacturing a semiconductor device | |
| KR100593733B1 (en) | DRAM cell adopting asymmetric buried insulating film and method of manufacturing the same | |
| TWI525817B (en) | Semiconductor device and method for manufacturing semiconductor device | |
| KR100947941B1 (en) | Semiconductor device and method for fabricating the same | |
| CN112054061B (en) | Body contact structure of partially depleted silicon on insulator and manufacturing method thereof | |
| US20210296161A1 (en) | Semiconductor Device and Method for Manufacturing Same | |
| KR100482950B1 (en) | Semiconductor device and manufacturing method thereof | |
| JP2008205031A (en) | Method for manufacturing semiconductor device | |
| CN116314002A (en) | Implementation mode of PDSOI body contact structure | |
| CN112054060B (en) | Body contact SOI MOS device structure and forming method | |
| KR20050063315A (en) | High voltage transistor and method for manufacturing the same | |
| KR20010094722A (en) | method for manufacturing high voltage device and the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |