CN112054025A - Serial SOI MOSFET device structure and preparation method thereof - Google Patents

Serial SOI MOSFET device structure and preparation method thereof Download PDF

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Publication number
CN112054025A
CN112054025A CN202010894212.4A CN202010894212A CN112054025A CN 112054025 A CN112054025 A CN 112054025A CN 202010894212 A CN202010894212 A CN 202010894212A CN 112054025 A CN112054025 A CN 112054025A
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region
body contact
semiconductor material
material layer
layer
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CN112054025B (en
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李多力
王家佳
曾传滨
罗家俊
韩郑生
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract

The invention discloses a serial SOI MOSFET device structure and a preparation method thereof, wherein the serial SOI MOSFET device structure comprises the following steps: the semiconductor material layer and the grid electrode are positioned on the buried oxide layer, and the partial isolation region is arranged at the edge where the active region of the series device is intersected with the grid electrode and extends to two sides along the width direction of the grid electrode; the shallow groove isolation region is arranged on the outermost side of the series device; the semiconductor device comprises a body contact area arranged at the non-intersected edge of an active area and a grid of the series device, and a conducting layer arranged on the surface of a semiconductor material layer, wherein the conducting layer covers and is short-circuited with the body contact area and an adjacent source area, so that the body contact area and the adjacent source area share a conducting contact hole. The device structure and the method provided by the invention are used for solving the technical problems of large chip area overhead and complex wiring of the serial SOI MOSFET device in the prior art. The technical effects of reducing the area occupation and the wiring complexity are achieved.

Description

Serial SOI MOSFET device structure and preparation method thereof
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly to a series SOI MOSFET device structure and a method for fabricating the same.
Background
In the modern CMOS process, the difference based on substrate materials is mainly divided into bulk silicon and SOI two process technical schemes, wherein the SOI technology has the advantages of eliminating parasitic latch-up effect, high speed, low noise, heat resistance, radiation resistance and the like compared with the bulk silicon technology due to the full-medium isolation structure characteristics of devices of the SOI technology, so that the SOI technology is widely adopted and becomes an important component part of the CMOS process.
The SOI technology can be divided into two technical branches of full depletion and partial depletion according to the depletion condition of the whole body region below a channel under the working state of an MOS device. The fully depleted SOI eliminates the body effect of the device due to the fact that the body region is fully depleted, and therefore the device design does not need to lead the body region out, namely, the body contact structure design is not needed. And for the partially depleted SOI device, without a Body contact structure, Body injection charges (NMOS is holes and PMOS is electrons) generated by reverse bias of a drain-Body junction and impact ionization of channel carriers near the drain-Body junction are accumulated in a Body region, so that a Floating Body Effect (Floating Body Effect) of the partially depleted SOI device is caused. The floating body effect can bias the device source-body junction forward, resulting in increased device sub-threshold leakage. And as the absolute value of the body region potential increases, the source-body-drain parasitic bipolar tube is finally opened, the warping (Kink effect) of an output characteristic curve occurs in the on state of the device, and the source-drain breakdown is reduced in the off state.
In order to avoid or relieve the negative influence of the floating body effect on the characteristics of the partially depleted SOI device, the structure and the layout of the device need to be specially designed, and the body region is led out, so that the charges injected into the body region can be quickly and effectively led out without accumulation. T-type, H-type and BTS-type are the most common types of partially depleted SOI devices with body contact structures. However, this also results in significant chip area overhead and wiring complexity due to the need to ensure that each individual SOI device has its own body contact design.
Disclosure of Invention
The present disclosure is directed, at least in part, to solving the technical problem of the prior art in which the body contact of the series SOI MOSFET device structure results in large chip area overhead and complicated wiring.
The embodiment of the disclosure provides the following technical scheme:
in a first aspect, a series SOI MOSFET device structure is provided, comprising:
the semiconductor material layer and the grid electrode are positioned on the buried oxide layer, the semiconductor material layer comprises an active region of a series device, and a source region and a drain region of the series device are arranged in the active region;
the partial isolation region is arranged at the edge of the serial device where the active region and the grid electrode are intersected, extends towards two sides along the width direction of the grid electrode, and is partially spaced from the buried oxide layer by the active region;
the shallow groove isolation region is arranged on the outermost side of the series device; the partial isolation region is connected with the shallow trench isolation region;
the body contact region is arranged at the edge where the active region of the series device does not intersect with the grid electrode, and extends to be connected with the buried oxide layer and the source region; the body contact region and the active region are the same in doping type, and the source region and the drain region are different from the active region in doping type;
and the conducting layer is arranged on the surface of the semiconductor material layer, and covers the body contact region and the adjacent source region in a short circuit mode, so that the body contact region and the adjacent source region share the conducting contact hole.
Optionally, the doping concentration of the body contact region is greater than the doping concentration of the active region.
Optionally, the thickness of the active region reserved between the partial isolation region and the buried oxide layer is greater than or equal to 50 nm.
Optionally, the doping concentration of the body contact region is greater than 1e19/cm3The doping concentration of the active region and the channel region of the device is more than 1e17/cm3。
Optionally, the active region adjacent to the body contact region is a ground terminal or a power terminal.
In a second aspect, a method for fabricating a serial SOI MOSFET device structure is provided, comprising:
providing a substrate, wherein a buried oxide layer is arranged on the substrate, and a semiconductor material layer is arranged on the buried oxide layer;
forming a shallow trench isolation region on the outermost side of the series device and partial isolation regions extending towards two sides along the width direction of a gate of the series device on the semiconductor material layer, wherein the shallow trench isolation region extends downwards to be connected with the buried oxide layer, a part of the semiconductor material layer is arranged between the partial isolation region and the buried oxide layer at intervals, and the partial isolation regions are connected with the shallow trench isolation region;
forming a source region, a drain region and a body contact region of a series device on the semiconductor material layer, wherein the body contact region is formed at the edge of the active region of the series device, which does not intersect with the gate electrode, and the body contact region extends to be connected with the buried oxide layer and the source region; the body contact region and the active region are the same in doping type, and the source region and the drain region are different from the active region in doping type;
and preparing a grid electrode on the surface of a channel region between the source region and the drain region, and preparing a conducting layer which is short-circuited with the body contact region and the adjacent source region on the surface of the semiconductor material layer so that the body contact region and the adjacent source region share a conducting contact hole.
Optionally, before forming the shallow trench isolation region and the partial isolation region, the method further includes: performing ion implantation on the semiconductor material layer to enable the doping concentration to be larger than 1e17/cm3。
Optionally, forming a shallow trench isolation region on the outermost side of the series device and a partial isolation region extending to both sides along the width direction of the gate of the series device on the semiconductor material layer includes: etching the semiconductor material layer to the buried oxide layer in the region where the shallow trench isolation region needs to be formed; etching the semiconductor material layer in the region where the partial isolation region needs to be formed until the distance between the semiconductor material layer and the buried oxide layer is more than or equal to 50 nm; and filling an isolation oxide in the etching area to form the shallow trench isolation area and the partial isolation area.
Optionally, forming a source region, a drain region and a body contact region of a series device on the semiconductor material layer includes: preparing an injection window on the semiconductor material layer, wherein the injection window is positioned on one side of an active region of the series device connected to a ground terminal or a power terminal and is connected with the partial isolation region; and carrying out ion implantation on the implantation window to form the body contact region, wherein the doping concentration of the body contact region is greater than that of the active region.
Optionally, forming a source region, a drain region and a body contact region of a series device on the semiconductor material layer includes: the doping concentration is formed to be more than 1e19/cm3The body contact region of (a).
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
the serial SOI MOSFET device structure and the manufacturing method thereof provided by the embodiment of the application are combined with a partial isolation region which is arranged at the intersected edge of the active region and the grid of the serial device and extends to two sides along the width direction of the grid, and a body contact region which is arranged at the intersected edge of the active region and the grid of the serial device. The active region below the channel of the series device is contacted with the body contact regions with the same type heavy doping below the partial isolation of the two ends of the active region, and then contacted with the source end of the device and the contact hole leading-out region, and the conductive channel has lower resistance, so that a novel complete body contact structure of the series device is formed. The structure body contact region is positioned at the edge of the source region, the layout width and length of the source region and the drain region are not increased, and the area overhead brought by the traditional body contact region can be effectively reduced. The loss of the effective width of the device caused by the BTS structure is avoided, and the extra gate capacitance caused by the overlapped region of the gate and the active region at the connecting position of the T-shaped or H-shaped body contact region is eliminated. And a contact hole is not required to be specially prepared for the body contact area for metal wiring, the source area contact hole is shared, and the wiring complexity of the rear section is simplified.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only examples of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a block diagram of a series SOI MOSFET device in accordance with one or more embodiments of the present disclosure;
FIG. 2 is a cross-sectional view taken along dashed line aa' of FIG. 1;
FIG. 3 is a cross-sectional view taken along the dashed line bb' in FIG. 1;
FIG. 4 is a cross-sectional view taken along the dashed line cc' in FIG. 1;
FIG. 5 is a cross-sectional view taken along the dotted line dd' in FIG. 1;
FIG. 6 is a logic diagram of a 2-input NAND gate;
fig. 7 is a flow chart of a method of fabricating a series SOI MOSFET device in accordance with one or more embodiments of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In the context of the present disclosure, similar or identical components may be referred to by the same or similar reference numerals.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to specific embodiments, and it should be understood that the specific features in the examples and examples of the present disclosure are detailed descriptions of the technical solutions of the present application, but not limitations of the technical solutions of the present application, and the technical features in the examples and examples of the present application may be combined with each other without conflict.
In accordance with one aspect of the present disclosure, there is provided a series SOI MOSFET device structure, as shown in fig. 1-5, comprising:
the semiconductor material layer 2 and the grid electrode 3 are positioned on the buried oxide layer 1, the semiconductor material layer 2 comprises an active region 4 of a series device, and a source region 41 and a drain region of the series device are arranged in the active region 4;
the partial isolation region 5 is arranged at the edge of the serial device where the active region 4 and the gate 3 intersect, and extends towards two sides along the width direction of the gate 3, and a part of the active region 4 is arranged between the partial isolation region 5 and the buried oxide layer 1;
a Shallow Trench Isolation (STI)6 arranged at the outermost side of the series device; the partial isolation region 5 is connected with the shallow trench isolation region 6;
the body contact region 7 is arranged at the edge of the active region 4 of the series device, which does not intersect with the grid electrode 3, and the body contact region 7 extends to be connected with the buried oxide layer 1 and the source region 41; the doping types of the body contact region 7 and the active region 4 are the same, and the doping types of the source region 41 and the drain region are different from the doping type of the active region 4;
and the conducting layer 8 is arranged on the surface of the semiconductor material layer 1, and the conducting layer 8 covers and shorts the body contact region 7 and the adjacent source region 41 so that the body contact region 7 and the adjacent source region 41 share the conducting contact hole 9.
It should be noted that fig. 2 is a cross-sectional view at a broken line aa 'in fig. 1, fig. 3 is a cross-sectional view at a broken line bb' in fig. 1, fig. 4 is a cross-sectional view at a broken line cc 'in fig. 1, and fig. 5 is a cross-sectional view at a broken line dd' in fig. 1.
Specifically, the serial devices may be 2 or more SOI NMOS devices connected in series, or may be 2 or more SOI PMOS devices connected in series. For example, the series devices may be 2 series SOI NMOS in 2-input nand logic with the source terminal Grounded (GND) as shown in fig. 6, where a, B, and Y in fig. 6 correspond to a, B, and Y in fig. 1. The serial device may also be a serial SOI PMOS with the device source terminal connected to the power supply (VDD) terminal, which is not limited herein. Generally, the number of bars of the series device is the same as the number of MOS devices in series, for example, there are 2 gates 3 as shown in fig. 1, which is two MOS devices in series.
When the serial device is arranged as an SOI NMOS device, the active region 4 is doped in a P type, the body contact region 7 is doped in a P + type, and the source region 41 and the drain region are doped in an N + type. When the series device is laid out as an SOI PMOS device, the active region 4 is doped N + type, the body contact region 7 is doped N + type, and the source region 41 and the drain region are doped P + type.
In a specific implementation, the doping concentration of the body contact region 7 is greater than the doping concentration of the active region 4. The active region 4 includes a channel region of the device and a region of the semiconductor material layer under the source and drain regions.
Preferably, the thickness of the active region 4 remained between the partial isolation region 5 and the buried oxide layer 1 is greater than or equal to 50 nm. The doping concentration of the body contact region 7 is more than 1e19/cm3The doping concentration of the active region 4 and the channel region of the device is more than 1e17/cm3。
Further, the source region 41 adjacent to the body contact region 7 is a ground terminal or a power terminal.
The following description will be made by taking the device as an SOI NMOS and the semiconductor material layer as a silicon layer as an example:
the silicon layer impurity under the partial isolation region 5 of the SOI NMOS serial device is P-type as the channel region(ii) a Correspondingly, the silicon layer impurity under the partial isolation region 5 for the SOI PMOS series device is N-type. In order to ensure that the silicon layer between the partial isolation region 5 and the buried oxide layer 1 has a stable and low series resistance, the thickness of the residual silicon layer should be at least 50nm, and the doping concentration is more than 1e17/cm3. The plan layout of the partial isolation region 5 is shown in fig. 1, the cross section of the partial isolation region connected with the body region below the device channel is shown in fig. 2, and the cross section of the partial isolation structure connected with the width direction of 2 series devices is shown in fig. 3.
For body contact region 7, SOI NMOS is P type, SOI PMOS is N type, and doping concentration is 1e19/cm3The above. The body contact region 7 and the series device source terminal 41 form ohmic contact through the conducting layer 8 and are short-circuited together, and then are commonly led out through the source terminal contact hole 9. The conducting layer 8 is a conductive layer, preferably a low-resistance silicide such as titanium silicide, nickel silicide or cobalt silicide, so that the process difficulty can be reduced by forming the conducting layer 8 through doping. The planar layout of the body contact region 7 is shown in fig. 1, the cross section of the body contact region 7 connected with a part of the isolation region 5 is shown in fig. 4, and the cross section of the conductive layer 8 shorting the body contact region 7 and the N + source region 41 together in the horizontal direction is shown in fig. 5. It can be seen that the body contact region 7 is connected to the active region 4 under part of the isolation region 5. And the body contact region 7 is arranged at one side which is not intersected with the grid electrode 3, so that the extra grid capacitance brought by the overlapping region of the grid electrode 3 and the active region 4 at the connecting position of the T-shaped or H-shaped body contact structure is eliminated. And the body contact region 7 can avoid the loss of the effective width of the device caused by the BTS structure, and the contact hole 9 is shared with the source region 41 without specially routing metal for the body contact region 7, thereby simplifying the wiring complexity of the rear section.
The above description has taken the device as an SOI NMOS as an example, and if the device is a PMOS, the involved doping types (N/P) need only be interchanged, and the solution still applies.
Based on the same inventive concept, the present application further provides a method for manufacturing the aforementioned serial SOI MOSFET device structure, as shown in fig. 7, including:
step S701, providing a substrate, wherein a buried oxide layer 1 is arranged on the substrate, and a semiconductor material layer 2 is arranged on the buried oxide layer 1;
step S702, forming a shallow trench isolation region 6 at the outermost side of the series device and a partial isolation region 5 extending to both sides along the width direction of the gate 3 of the series device on the semiconductor material layer 2, wherein the shallow trench isolation region 6 extends downward to be connected with the buried oxide layer 1, a part of the semiconductor material layer 2 is spaced between the partial isolation region 5 and the buried oxide layer 1, and the partial isolation region 5 is connected with the shallow trench isolation region 6;
step S703 of forming a source region 41, a drain region and a body contact region 7 of a tandem device on the semiconductor material layer 2, wherein the body contact region 7 is formed at an edge of the active region 41 of the tandem device not intersecting the gate 3, and the body contact region 7 extends to be connected with the buried oxide layer 1 and the source region 41; the doping types of the body contact region 7 and the active region 4 are the same, and the doping types of the source region 41 and the drain region are different from the doping type of the active region 4;
step S704, preparing a gate 3 on the surface of the channel region between the source region 41 and the drain region, and preparing a conducting layer 8 on the surface of the semiconductor material layer 2 to short the body contact region 7 and the adjacent source region 41, so that the body contact region 7 and the adjacent source region 41 share the conducting contact hole 9.
It should be noted that the semiconductor material layer 2 may be a silicon layer, a silicon germanium layer, or the like, and is not limited herein.
After providing the substrate with the buried oxide layer 1 and the semiconductor material layer 2 sequentially arranged upwards, the semiconductor material layer 2 can be subjected to ion implantation to enable the doping concentration to be more than 1e17/cm3And is used as an active region 4 below a channel region and a source/drain region of the device. Of course, the semiconductor material layer 2 may be implanted after the shallow trench isolation region 6 and the partial isolation region 5 are formed, which is not limited herein.
Then, shallow trench isolation regions 6 at the outermost sides of the series device and partial isolation regions 5 extending to both sides in the width direction of the gate 3 of the series device are formed on the semiconductor material layer 2. Specifically, the semiconductor material layer 2 is etched to the buried oxide layer 1 in the region where the shallow trench isolation region 6 needs to be formed; and etching the semiconductor material layer 2 in the region where the partial isolation region 5 needs to be formed until the distance between the semiconductor material layer 2 and the buried oxide layer 1 is greater than or equal to 50 nm. And filling an isolation oxide in the etching area to form the shallow trench isolation region 6 and the partial isolation region 5.
Specifically, a 1-layer mask can be added in the etching step of the original shallow trench isolation region 6 of the device, and the edge of the active region 4 in the width direction of the device gate extends outwards for a certain width to define the SOI partial isolation region 5. The shallow trench isolation region is etched to the buried oxide layer 1. And then, by additional 1-time partial silicon etching, a strip-shaped groove which is only etched to the middle part of the upper semiconductor material layer of the buried oxide layer 1 of the SOI is formed in a partial isolation region, and the strip-shaped groove and other grooves which are completely etched to the buried oxide layer 1 are filled with isolation oxide, so that a fully isolated shallow groove isolation region 6 and a partial isolation region 5 which are connected are formed simultaneously.
For example, the device is an SOI NMOS device, and the semiconductor material layer under the partial isolation region 5 is P-type as the channel region. Correspondingly, for an SOI PMOS device, the layer of semiconductor material under the partial isolation region 5 is N-type. In order to ensure a stable low series resistance of the semiconductor material layer between the partial isolation region 5 and the buried oxide layer 1, the thickness of the remaining semiconductor material layer should be kept at least 50 nm.
Source regions 41, drain regions and body contact regions 7 of the series devices are then formed on the layer 2 of semiconductor material. Specifically, an implantation window is first prepared on the semiconductor material layer 2, the implantation window being located on the side of the active region 4 where the series device is connected to a ground terminal or a power terminal, and both ends of the implantation window being connected to the partial isolation region 5. And then carrying out ion implantation on the implantation window to form the body contact region 7, wherein the doping concentration of the body contact region 7 is greater than that of the active region 4. For example, in the step of forming source and drain region doping, a body contact region 7 may be defined on the field isolation side of the active region at one end of the SOI MOS device connected to Ground (GND) or power (VDD) through a mask for source and drain region implantation, and connected to the two end isolation regions 5 in the device width direction, and impurities of the same type as the device channel may be implanted to form a doping concentration greater than 1e19/cm3The body contact region 7.
Preparing a grid 3 on the surface of a channel region between the source region 41 and the drain region, and preparing a conducting layer 8 on the surface of the semiconductor material layer 2 for short-circuiting the body contact region 7 and the adjacent source region 41, so that the body contact region 7 and the adjacent source region 41 share a conducting contact hole 9. And then preparing structures such as contact holes, metal leads and the like to finally form the series device.
Since the method provided in this embodiment is a method for manufacturing the tandem device provided in the foregoing embodiment, the specific structure of the tandem device has been described in detail and will not be described again.
Specifically, the serial SOI MOSFET device structure and the method for manufacturing the same provided by the embodiments of the present application combine a partial isolation region disposed at an edge where an active region of the serial device intersects with the gate and extending to both sides along a width direction of the gate, and a body contact region disposed at an edge where the active region of the serial device does not intersect with the gate. The active region below the channel of the series device is contacted with the body contact regions with the same type heavy doping below the partial isolation of the two ends of the active region, and then contacted with the source end of the device and the contact hole leading-out region, and the conductive channel has lower resistance, so that a novel complete body contact structure of the series device is formed. The structure body contact region is positioned at the edge of the source region, the layout width and length of the source region and the drain region are not increased, and the area overhead brought by the traditional body contact region can be effectively reduced. The loss of the effective width of the device caused by the BTS structure is avoided, and the extra gate capacitance caused by the overlapped region of the gate and the active region at the connecting position of the T-shaped or H-shaped body contact region is eliminated. And a contact hole is not required to be specially prepared for the body contact area for metal wiring, the source area contact hole is shared, and the wiring complexity of the rear section is simplified.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims (10)

1. A series SOI MOSFET device structure, comprising:
the semiconductor material layer and the grid electrode are positioned on the buried oxide layer, the semiconductor material layer comprises an active region of a series device, and a source region and a drain region of the series device are arranged in the active region;
the partial isolation region is arranged at the edge of the serial device where the active region and the grid electrode are intersected, extends towards two sides along the width direction of the grid electrode, and is partially spaced from the buried oxide layer by the active region;
the shallow groove isolation region is arranged on the outermost side of the series device; the partial isolation region is connected with the shallow trench isolation region;
the body contact region is arranged at the edge where the active region of the series device does not intersect with the grid electrode, and extends to be connected with the buried oxide layer and the source region; the body contact region and the active region are the same in doping type, and the source region and the drain region are different from the active region in doping type;
and the conducting layer is arranged on the surface of the semiconductor material layer, and covers the body contact region and the adjacent source region in a short circuit mode, so that the body contact region and the adjacent source region share the conducting contact hole.
2. The device of claim 1, wherein:
the body contact region has a doping concentration greater than a doping concentration of the active region.
3. The device of claim 1, wherein:
the thickness of the active region reserved between the partial isolation region and the buried oxide layer is greater than or equal to 50 nm.
4. The device of claim 1, wherein:
the body contact region has a doping concentration greater than 1e19/cm3The doping concentration of the active region and the channel region of the device is more than 1e17/cm3。
5. The device of claim 1, wherein:
the active region adjacent to the body contact region is a ground terminal or a power terminal.
6. A method for manufacturing a series SOI MOSFET device structure is characterized by comprising the following steps:
providing a substrate, wherein a buried oxide layer is arranged on the substrate, and a semiconductor material layer is arranged on the buried oxide layer;
forming a shallow trench isolation region on the outermost side of the series device and partial isolation regions extending towards two sides along the width direction of a gate of the series device on the semiconductor material layer, wherein the shallow trench isolation region extends downwards to be connected with the buried oxide layer, a part of the semiconductor material layer is arranged between the partial isolation region and the buried oxide layer at intervals, and the partial isolation regions are connected with the shallow trench isolation region;
forming a source region, a drain region and a body contact region of a series device on the semiconductor material layer, wherein the body contact region is formed at the edge of the active region of the series device, which does not intersect with the gate electrode, and the body contact region extends to be connected with the buried oxide layer and the source region; the body contact region and the active region are the same in doping type, and the source region and the drain region are different from the active region in doping type;
and preparing a grid electrode on the surface of a channel region between the source region and the drain region, and preparing a conducting layer which is short-circuited with the body contact region and the adjacent source region on the surface of the semiconductor material layer so that the body contact region and the adjacent source region share a conducting contact hole.
7. The method of claim 6, wherein prior to forming said shallow trench isolation region and said partial isolation region, further comprising:
performing ion implantation on the semiconductor material layer to enable the doping concentration to be larger than 1e17/cm3。
8. The method of claim 6, wherein forming an outermost shallow trench isolation region of the series device and partial isolation regions extending to both sides in a width direction of a gate of the series device on the layer of semiconductor material comprises:
etching the semiconductor material layer to the buried oxide layer in the region where the shallow trench isolation region needs to be formed; etching the semiconductor material layer in the region where the partial isolation region needs to be formed until the distance between the semiconductor material layer and the buried oxide layer is more than or equal to 50 nm;
and filling an isolation oxide in the etching area to form the shallow trench isolation area and the partial isolation area.
9. The method of claim 6, wherein forming source, drain and body contact regions of a tandem device on the layer of semiconductor material comprises:
preparing an injection window on the semiconductor material layer, wherein the injection window is positioned on one side of an active region of the series device connected to a ground terminal or a power terminal and is connected with the partial isolation region;
and carrying out ion implantation on the implantation window to form the body contact region, wherein the doping concentration of the body contact region is greater than that of the active region.
10. The method of claim 6, wherein forming source, drain and body contact regions of a tandem device on the layer of semiconductor material comprises:
the doping concentration is formed to be more than 1e19/cm3The body contact region of (a).
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CN103441131A (en) * 2013-08-29 2013-12-11 上海宏力半导体制造有限公司 Partially-depleted silicon-on-insulator device structure
CN105280715A (en) * 2015-11-30 2016-01-27 上海华虹宏力半导体制造有限公司 SOI body contact device structure
CN105845733A (en) * 2016-04-15 2016-08-10 中国科学院上海微系统与信息技术研究所 P-type dynamic threshold transistor, preparation method and method for increasing operating voltage
CN106847749A (en) * 2017-01-19 2017-06-13 上海宝芯源功率半导体有限公司 A kind of switching device for lithium electric protection and preparation method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103441131A (en) * 2013-08-29 2013-12-11 上海宏力半导体制造有限公司 Partially-depleted silicon-on-insulator device structure
CN105280715A (en) * 2015-11-30 2016-01-27 上海华虹宏力半导体制造有限公司 SOI body contact device structure
CN105845733A (en) * 2016-04-15 2016-08-10 中国科学院上海微系统与信息技术研究所 P-type dynamic threshold transistor, preparation method and method for increasing operating voltage
CN106847749A (en) * 2017-01-19 2017-06-13 上海宝芯源功率半导体有限公司 A kind of switching device for lithium electric protection and preparation method thereof

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