JP3456913B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MISFE formed on a semiconductor layer on an insulating substrate.
T, so-called SOI-MISFET (Silicon on insul
ator-Metal Insulator Semiconductor Field Effect Tra
nsistor).

[0002]

2. Description of the Related Art SOI-MISFET, that is, MISFE formed on a semiconductor layer formed on an insulating substrate.
T is a MISFET formed on a bulk semiconductor substrate
In comparison with, the junction capacitance between the source / drain region and the substrate can be reduced, so that it is expected as a low power consumption and high speed device.

Particularly, in a so-called fully depleted SOI-MISFET in which the thickness of the SOI layer is equal to or less than the thickness of the depletion layer in the channel region during operation, a so-called portion in which the SOI layer is larger than the depletion layer thickness in the channel region during operation Depleted SOI
-It is possible to eliminate or suppress unfavorable phenomena such as a kink characteristic and a current overshoot effect which are problems in a MISFET.

Further, a fully depleted SOI-MISFET
Suppresses short channel effect, improves punch-through breakdown voltage,
It offers a wide range of benefits, including improved subthreshold coefficients and increased channel mobility.

[0005]

FIG. 21 shows MISFET transistors Q _n1 and Q _n2 formed on an SOI substrate.
FIG. 7 is a cross-sectional view of a conventional semiconductor device in which the gate array structure is formed. In the support substrate 5 facing the SOI layer region in which the gate array is formed, an n-type bar serving as a back gate electrode is formed.
The lock gate region 1 is formed. As an example of the method of forming the back gate region 1, p facing the transistor region is used.
An n-type silicon region is formed by ion-implanting an n-type impurity such as phosphorus, arsenic or antimony into the support substrate 5 made of type silicon. Then, by forming the voltage node 18 to the back gate region 1, it becomes possible to apply a voltage to the back gate region . Therefore, with the structure of FIG. 21, it is possible to apply a back gate voltage equal to that of the MISFET transistors Q _n1 and Q _n2 .

However, the back gate region 1 shown in FIG.
The above structure has a problem that the parasitic capacitance CD with the drain electrode 15 is large. Also, independent back gate voltages cannot be applied to the MISFET transistors Q _n1 and Q _n2 . Therefore, it is impossible to individually control the back gate voltage of the transistors.

Next, a problem that occurs in the circuit of the semiconductor device shown in FIG. 21 will be described. FIG. 22 is a circuit diagram showing a NAND circuit. In FIG. 22, Q _n1 , Q
_n2 is an n-type MISFET, and Q _p1 and Q _p2 are p-type MISFETs. A common back gate electrode is provided for each of Q _n1 , Q _n2 and Q _p1 , Q _p2 , and an n-type MISFET and a p-type MISF are provided.
The back gate voltages VB1 and VB2 can be applied to each ET.

In this circuit configuration, the source electrode of Q _n2 is connected in series with the drain electrode of Q _n1 . Therefore, in the state where the input voltages of Q _n1 and Q _n2 are conductive at VDD, the voltage of the source electrode of Q _n2 increases by, for example, Vs due to the series resistance of Q _n1 . On the other hand, Q
The voltage of the source electrode of _n1 is 0V because it is grounded. The source voltage of Q _n2 rises above the source voltage of Q _n1 .

Therefore, the gate voltage input to Q _n2 becomes Vgs2 = (VDD-Vs), which is smaller than Vgs1 = VDD which is the gate voltage of Q _n1 . Also, Q _n2
Similarly, the back gate voltage of VBS2 = (VB2-V
s), and the back gate voltage of Q _n1 is VBS1 = V
It becomes smaller than B1.

Therefore, even if this circuit is formed by transistors having the same threshold value for Q _n1 and Q _n2 , the same current driving capability or the same threshold value cannot be obtained.
Therefore, there arises a problem that the delay times of Q _n1 and Q _n2 are different, which becomes a problem in the timing design of the circuit.

The present invention is a semiconductor device using an SOI-MISFET having a back gate electrode which solves the above problems, and particularly SOI-MISFE in a gate array structure.
A semiconductor device using T is provided.

[0012]

The first aspect of the present invention is as follows.
An insulating film and a first conductive type first film formed on the insulating film;
Impurity region, a second conductivity type first channel region formed adjacent to the first impurity region, and a first conductivity type second region formed adjacent to the first channel region. Impurity region, a second conductivity type second channel region formed adjacent to the second impurity region, and a first conductivity type third channel formed adjacent to the second channel region. Impurity region, a first gate insulating film formed on the first channel region, a second gate insulating film formed on the second channel region, and the first gate insulating film A first gate electrode formed thereon, a second gate electrode formed on the second gate insulating film, and a first gate electrode formed directly below the first channel region with the insulating film interposed therebetween.
A first back gate region of a conductivity type, a second back gate region of a first conductivity type formed directly below the second channel region with the insulating film interposed, and a first back gate region; A first power supply for supplying a first potential;
And a second power supply for supplying a second potential different from the first potential to the back gate region.

The second conductive type first semiconductor region may be provided to cover the first and second back gate regions.

[0014]

A second aspect of the present invention is an insulating film,
A first impurity region of the first conductivity type formed on the insulating film, and a second impurity region formed adjacent to the first impurity region.
A conductivity type first channel region, a first conductivity type second impurity region formed adjacent to the first channel region, and a second impurity region formed adjacent to the second impurity region. A conductive type second channel region, a first conductive type third impurity region formed adjacent to the second channel region, and a first gate formed on the first channel region. An insulating film, a second gate insulating film formed on the second channel region, a first gate electrode formed on the first gate insulating film, and a second gate insulating film on the second gate insulating film. A second gate electrode formed on the second conductive layer, and a fourth conductive type fourth layer formed under the second impurity region via the insulating film.
First impurity region, a fifth impurity region of the second conductivity type that covers the fourth impurity region, and a first impurity region in the fourth impurity region.
And a second power source that supplies a second potential different from the first potential to the fifth impurity region.

A third aspect of the present invention is an insulating film,
A first impurity region of the first conductivity type formed on the insulating film, and a second impurity region formed adjacent to the first impurity region.
A conductivity type first channel region, a first conductivity type second impurity region formed adjacent to the first channel region, and a second impurity region formed adjacent to the second impurity region. A conductive type second channel region, a first conductive type third impurity region formed adjacent to the second channel region, and a first gate formed on the first channel region. An insulating film, a second gate insulating film formed on the second channel region, a first gate electrode formed on the first gate insulating film, and a second gate insulating film on the second gate insulating film. A second gate electrode formed on the second conductive layer, and a fourth conductive type fourth layer formed under the second impurity region via the insulating film.
Second impurity type fifth and sixth impurity regions facing each other with the fourth impurity region interposed therebetween, and a first potential supplying a first potential to the fifth impurity region. A power source and a second power source for supplying a second potential different from the first potential to the sixth impurity region are provided.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of a semiconductor device according to the first embodiment, FIG. 2 is a sectional view, FIG. 3 is a plan view, and FIG. 4 is a circuit diagram. 1 and 2 show sectional structures taken along lines AA 'and BB' in FIG. 3, respectively. FIG. 4 shows a circuit diagram including a NAND circuit. Further, in FIG. 2, a contact electrode (17) to a gate formed on an extension of the A-side of the BB ′ cross section,
And the contact electrode (18) to the back gate is not included in the cross section but is shown for illustration.

Next, reference symbols used in this embodiment will be described. 1 is an n-type back gate region, 2 is a p-type back gate region
Gate region, 3 is a gate sidewall insulating film, 4 is a channel region, 5 is a supporting substrate, 6 is a buried insulating film in SOI, 9
Is a gate insulating film, 10 is a gate electrode, 11 is a source / drain region, 12 is an interlayer insulating film, 13 is an element isolation insulating film, 14 is a contact, 15 is a source / drain region shared by transistors connected in series, 16 , 16 'are contacts to the Si film of SOI, 16''are contacts to the gate electrode 10, 17 are electrodes to the Si film of SOI, and 18 is an electrode to the support substrate 5.

A specific configuration example will be described below. Here, the configuration of the n-type MISFET will be described. For example, P, As, and Sb are 10 ¹⁵ to 10 ¹⁸ cm
^A buried insulating film 6 made of, for example, a silicon oxide film or a silicon nitride film is formed to have a thickness of 10 to 1000 nm on a support substrate 5 made of an n-type semiconductor made of ^-3 doped, for example, Si or SiGe. Then, on the buried insulating film 6, for example, boron or indium 10 ¹⁵
P-type silicon or p-type S added to 10 ¹⁸ cm ^-3
An iGe semiconductor is formed of a semiconductor layer having a thickness of 1 to 300 nm to form an SOI substrate. Then, on the semiconductor layer including the channel region 4, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film,
A gate insulating film 9 made of a tantalum oxide film, a titanium oxide film, or a strontium titanium oxide film and having a thickness of 1 to 200 nm, and, for example, phosphorus or boron 10
¹⁹ cm ⁻³ or more doped polycrystalline silicon film or T
The gate electrode 10 is formed by depositing iN, TaN, W, and Al to a thickness of 10 to 300 nm. Gate electrode 10
Are formed with a width of 0.01 to 1 μm, for example.
Then, for example, P, As, or Sb is added to the semiconductor layer in which the channel region 4 is formed, in the range of 10 ¹⁶ to 10 ²¹ cm ^−3.
Source / drain regions 11 and 1 of the added n-type region
1'and 15 are formed on both sides of the gate, and these gate electrode 10, channel region 4, and source / drain region 1 are formed.
1, 11 ′ and 15 form n-type MISFET transistors Q _n1 and Q _n2 . In order to improve the electrical isolation between the gate electrode 10 and the source / drain regions 11, 11 ′, 15 on the raised side surface of the gate region, an insulating film 3 made of, for example, a silicon oxide film or a nitride film is formed.
Are formed with a side surface thickness of 5 to 200 nm.

The drain region of Q _n1 and the source region of Q _n2 are composed of the same n-type impurity region 15 and form a gate array structure in which so-called two transistors are connected in series.

In the support substrate 5, for example, B or In
Of p-type backgam to which 10 ¹⁶ to 10 ¹⁸ cm ^{−3 was} added
DOO region 2 is formed. The p-type back gate region 2 is in contact with the buried insulating film 6. And p-type back game
In the region opposite to the channel regions of Q _n1 and Q _{n2 in} the _transistor region 2, for example, P, As or Sb is 10 ¹⁶ to 10 ^16.
Back gate made of n-type impurities added at ²¹ cm ⁻³
Regions 1, 1'are formed. This back gate area 1,
1'is formed in contact with the embedded insulating film 6,
It is possible to change the potentials of the channel regions 4 and 4'of the I layer by adjusting the potential of the back gate region . Then, the voltage node 18 of FIG. 2 is formed in the back gate regions 1 and 1 ′, and a voltage can be applied. The back gate regions 1 and 1 ′ are surrounded by the p-type back gate region 2 and do not contact the n-type support substrate 5. Therefore, a reverse bias is applied between the p-type back gate region 2 and the back gate region 1 and between the p-type back gate region 2 and the back gate region 1 ′ so that they are electrically separated. There is. Therefore, it becomes possible to apply different voltages to the back gate region 1 and the back gate region 1 '.

Furthermore, p-type back gate region 2, the pn junction formed between the n-type support substrate 5, by applying a reverse bias between them, the supporting substrate 5 and p-type bar
The electrical isolation between the gate gate region 2 can be performed. As a result, the voltage of the p-type back gate region 2 can be set independently of the support substrate 5, and the support substrate 5 can be made smaller so that the capacitance between the n-type back gate region 1 and the p-type back gate region 2 can be reduced. And the voltage can be set independently. Therefore, in this embodiment, the n-type back gate region is
It is important to prevent a forward bias condition between the region 1 or 1 ′ and the p-type back gate region 2, but even if these back gate voltages are biased positively and negatively with respect to the source voltage, The voltage of the back gate region 2
By making the voltage of the back gate regions 1 and 1 ′ more negative and adjusting it to be more negative than 0V, it is possible to prevent the forward bias condition while keeping the potential of the substrate 5 at 0V. Therefore, the capacitive coupling between the back gate and the substrate becomes weak, and the voltage change due to the capacitive coupling between the back gates and the latch-up effect due to the minority carrier injection can be reduced. Further, since it is not necessary to bias the support substrate 5 having a large capacitance with the package, it is possible to suppress the power consumption of the substrate bias circuit.

According to the structure of the semiconductor structure of this embodiment,
In the semiconductor device having the gate array structure, the back gate region 1 is provided on the supporting substrate 5 facing the channel region 4 of each transistor, and independent back gate voltages VB1 and VB2 can be applied to each. Therefore, the threshold value of each transistor can be controlled by the back gate voltage.
In addition, the back gate region is formed in the supporting substrate region facing the channel region, and the source / drain regions 11, 1 are formed.
Source / drain regions 11 and 1 facing 1 ′ and 15
A p-type battery having a conductivity type opposite to those of 1'and 15
The gate region 2 is formed. When a potential is applied to the source / drain regions 11, 11 'and 15 , p-type back
Gate region 2 and n-type source / drain regions 11, 1
Since the conductivity is different between 1'and 15 , a depletion layer is formed in the back gate region 2 having a low p-type impurity concentration. Therefore, the parasitic capacitance between the source / drain region 11 and the back gate can be made smaller than that of the structure including the back gate electrode shown in FIG. Also,
Since this parasitic capacitance can be reduced, the impedance of the signal of the drain electrode transmitted to the supporting substrate 5 and the back gate regions 1 and 1'can be reduced, and the crosstalk between devices can be further reduced.

Next, an example in which a circuit problem is solved by the back gate control in the semiconductor device of this embodiment will be described. FIG. 4 shows a circuit diagram of a so-called NAND circuit, in which two p-type MISFETs connected in parallel are provided.
It is composed of transistors Q _p1 and Q _p2 and two n-type MISFET transistors Q _n1 and Q _n2 connected in series. The back gate electrode described above is formed on the n-type MISFETs Q _n1 and Q _n2 , and Q
Back gate voltages of VB1 and VB2 can be applied to _n1 and _Qn2 , respectively.

[0025] In this circuit _{configuration,} the source voltage of _{Q n2,} in a state _{where Q n1} and _{Q n2} is conductive for the series resistance of _{Q n1,} rises from 0V only Vs. On the other hand, Q
The source voltage of _n1 is grounded and is 0V. Therefore, the source voltage of Q _n2 becomes higher than that of Q _n1 .

Therefore, for example, in the circuit configuration of FIG. 4, a back gate voltage equal to Q _n1 and Q _n2 (VB1 = V
When B2) is applied from a voltage source, the back gate potential measured from the source potential applied to each transistor of Q _n1 and Q _n2 is, although Q _n1 is VB1 (= VB2),
Q _n2 becomes (VB2-Vs), and the back gate voltage of Q _n2 becomes smaller than that of Q _n1 .

By the way, fully depleted SOI-MISFE
The threshold value of T is expressed by the following equation when the region of the channel region in contact with the buried oxide film (hereinafter referred to as the back surface) is in a depleted state.

Vth1, depl2 = Vth1, acc2-CSiCox2
(VG2-VG2, acc) / {Cox1 (CSi + Cox2)}
(1) where VG2, acc <VG2 <VG2, inv In equation (1), Vth1 and acc2 represent the threshold values of the transistor when the back surface is in an accumulation state, and CSi and C
ox1 and Cox2 are the capacitance of the SOI layer, the gate insulating film, and the buried insulating film, VG2 is the back gate voltage, and V
G2, acc and VG2, inv indicate the back gate voltage when the back surface is accumulated and is in an inverted state.

FIG. 7 is a graph showing the back gate voltage dependence of the threshold value in the fully depleted MISFET. The threshold value of the fully depleted MISFET is determined by applying a back gate voltage to the back surface of the SOI layer.
Can be changed in the range from accumulation to inversion.

Therefore, in the circuit configuration of FIG. 4, Q _n1 ,
Q _n2 is composed of transistors of equal threshold,
And the back gate voltage (VB1 = V
When B2) is input from the voltage source, the effective back gate voltage of Q _n2 becomes the potential difference between the source voltage Vs and the back gate voltage, that is, VG2 = (VB1-Vs), and Q2
The back gate voltage of _n1 becomes VB1. Therefore Q
_n2 threshold CSiCox2Vs than the threshold value of _{Q n1}
It becomes larger by / {Cox1 (CSi + Cox2)}, which causes a problem that the transistor operation is different between Q _n1 and Q _n2 .

In the structure of this embodiment, the back gate voltage can be independently applied to each transistor. Therefore, to solve the Kakaru problem with the structure of this embodiment, i.e. by controlling the back gate voltage of Q _n1, Q _n2, realizing the equalizing the threshold of Q _n1 and Q _n2.

Specifically, the back gate voltage VB2 applied to Q _n2 is compared with the back gate voltage VB1 applied to Q _n1 by: VB2 = VB1 + Vs (2) where VG2, acc <VB2 <VG2, inv and To do. Thus the potential difference between the source electrode and the back gate electrode of _{Q n2} is equal to that of _{Q n1,} threshold resulting _{Q n1} and _{Q n2} are equal. That is, Q
The transistor Q _n2 by adding _n2 source voltage increment of the back gate voltage can achieve the same threshold as Q _n1 also. Therefore, the amount of change in the threshold value with respect to the variation in the SOI film thickness can be set to the same condition for Q _n1 and Q _n2 , and a transistor integrated circuit with more uniform characteristics can be realized. FIG. 8 shows a back gate voltage VB that realizes no threshold variation with respect to a change in the source voltage Vs of Q _n2 .
It is a graph showing the relationship of 2. With respect to the source voltage Vs,
By inputting VB2 corresponding to the straight line of the graph to the back gate, the threshold values of Q _n1 and Q _n2 can be made equal. By inputting VB2 larger than this straight line to the back gate, the threshold value of Q _n2 becomes Q _n1.
Smaller than that.

Further, by providing a control circuit for controlling the back gate voltage as shown in FIG. 5, it becomes possible to suppress the threshold variation due to the change of the source voltage of Q _n2 . FIG. 5 is a circuit diagram of a semiconductor device having a voltage supply control circuit 8 that sets the back gate voltage to be applied by feedback controlling the source voltage Vs of Q _n2 .
The control circuit 8 monitors the source voltage Vs of Q _n2 , sets the back gate voltage VB2 that satisfies the equation (2), and inputs it to the back gate electrode of the transistor Q _n2 . This control circuit can suppress the threshold variation of Q _n2 by controlling the back gate voltage.

By the way, since the source voltage of Q _n2 is Vs, the effective gate voltage input to Q _n2 is also (V
DD-Vs), which is smaller than VDD of the gate voltage of Q _n1 . This causes a problem that the current driving capability of Q _n2 is lowered and the gate delay time is increased.

Drain current Idsat in the saturation region
Is represented by the formula shown below. Idsat = 1/2 · W / L · μeff · Cox · (Vgs-
Vth) 1.3 to 2 (3) In formula (3), W is the gate width, L is the gate length, and μef
f is the mobility, Cox is the capacitance of the gate insulating film, Vgs is the gate voltage with reference to the source potential, and Vth is the threshold value of the transistor.

As can be seen from the equation (3), the current driving capability of the transistor is represented by a function of the gate voltage, and the higher the gate voltage, the higher the current driving capability. Therefore, in the circuit configuration of FIG. 22, when Q _n1 and Q _n2 perform the same threshold operation, the gate voltage of Q _n2 is reduced by Vs as described above, so that the current driving capability is lower than that of Q _n1. .

The signal propagation delay time τ is expressed by the following equation. τ = Cload · VDD / Idsat (4) In the equation (4), Cload represents a load capacity.

The propagation delay time τ is the saturated drain current Ids
It is inversely proportional to at, and the delay time increases as the saturation drain current decreases. The circuit arrangement of FIG. 22 Thus, when a 4 in VB1 = VB2 In other _{words, Q n2}
Since the current drive capacity of Q _n2 is smaller than that of Q _n1 ,
The transition time before turning on becomes longer than that of Q _n1 . The difference in transition time caused by the difference in the input terminals causes a problem in the timing design of the circuit.

A back gate control method for solving this problem in this embodiment will be described below. As mentioned above
The current drive capability is proportional to (Vgs-Vth) 1.3-2. Therefore, in the circuit configuration of FIG. 4, Q _n1 and Q _n2
When equal threshold (Vth1 = _Vth2), the current driving capability of the _{Q n2} because the gate voltage is smaller by Vs compared to the _{Q n1,} the current driving capability of the _{Q n2} is smaller than that of _{Q n1.}

Therefore, in order to equalize the current driving capacities of Q _n1 and Q _n2 , the reduction Vs of the gate voltage input to Q _n2 is compensated by a threshold value. That is, the threshold V of Q _n2 is controlled by the back gate voltage control.
By reducing th2 to Vth2 '= Vth1-Vs,
_A current driving capability equal to _n1 is realized. This Vth2 '＝
The back gate voltage VB2 ′ required to realize Vth1−Vs satisfies the following equation.

VB2 '(Vs) = Vs / γ + VB1
(5) In the equation (5), γ is γ = CSiCox2 / {Cox1 (CSi
+ Cox2)}, which can be approximated as tox1 / tox2. tox1 and tox2 represent the film thickness of the gate insulating film and the embedded insulating film. Therefore, the back gate voltage VB2 ′ that makes the current driving capability constant is determined by the source voltage Vs and the film thickness ratio of the gate insulating film and the buried insulating film.

FIG. 9 is a graph showing the relationship between the source voltage Vs of Q _{n2 and} the back gate voltage VB2 'required to make the current driving capability equal to Q _n1 . Q
It is possible to make the current driving capacities almost equal by applying the back gate voltage VB2 ′ satisfying the expression (5) in the circuit formed by the thresholds with the same _n1 and Q _n2 . In other words, in FIG. 9, by applying the back gate voltage VB2 ′ corresponding to the straight line of the graph to Vs, it is possible to make the current driving capacities almost equal. However, transistor control is performed within the range where the back surface is depleted, that is, the back gate voltage VB.
2 ′ is possible within the range of VG2, acc <VB2 ′ <VG2, inv.

Further, it is also possible to use the control circuit 8 shown in FIG. 5 described above as a control circuit for keeping the current driving capability constant. That is, the source voltage Vs of Q _n2 is fed back, and the back gate voltage VB that satisfies FIG.
Set 2 ′ and apply to Q _n2 . As a result, it is possible to form a semiconductor device whose current driving capability does not change with respect to Vs fluctuation.

Here, it is understood that VB2 <VB1 should be satisfied in order to improve the effect of either equation (2) or equation (5), that is, to improve the current driving capability of Q _n2 as compared with the conventional example. Here, in order to control VB2, as shown in FIG. 4B, a transistor Q equivalent to Q _n1 and Q _n2 is used.
_The back gate voltage VB2 may be obtained from the source voltage obtained by the dummy circuit formed by connecting _n1 ′ and Q _n2 ′ in series, or VB2 may be commonly given to a plurality of NAND circuits.

According to the structure of this embodiment, the following effects can be obtained. (1) As shown in FIG. 1, in the present embodiment, a semiconductor device having a gate array structure is provided with a back gate region in a support substrate facing the channel region of each transistor, and is provided at a position facing the drain. Is designed to form a depletion layer on the support substrate. Therefore, the parasitic capacitance between the source / drain region and the supporting substrate is reduced, so that, for example, the operating power consumption is reduced and the S factor is reduced. Then, the signal propagation delay time can be reduced. Thus, it greatly contributes to low consumption and high speed.

[0046] (2) back gate region provided in each transistor, the back gate territory of adjacent transistors
Since it is formed to be electrically separated from the region, it is possible to individually apply a back gate voltage to control the transistor.

Further, according to the control example of the present embodiment, the following effects can be obtained. (3) As shown in FIG. 8, by controlling the back gate voltage of Q _n2, suppressing threshold increase due to the source voltage increase of Q _n2, it can be equal to the threshold value of Q _n1 is there. Therefore, for example, the delay time in the triode operation can be shortened, the margin of the operation time of the logic circuit in the triode operation can be reduced, and the high speed operation can be realized. Further, as shown in the circuit configuration of FIG. 5, by feeding back the change in the source voltage of Q _n2 and controlling the back gate voltage, it is possible to realize a semiconductor device with a small threshold variation.

[0048] (4) As shown in FIG. 9, by controlling the back gate voltage of Q _n2, it is possible to suppress the current driving capability decreases due to source voltage drop of Q _n2. Therefore, the propagation delay time of the signal is suppressed in the logic circuit, and high-speed operation is realized. Further, the difference between the maximum value and the minimum value of the switching time can be suppressed, and the operating speeds of the circuits can be made more uniform.

FIG. 10 shows a structural plan view of the second embodiment of the present invention. 10 is a top view in which the wiring layer and the contact layer are omitted, and FIGS. 11, 12 and 13 are cross-sectional views taken along arrows AA ′, BB ′ and CC ′ of FIG. 10, respectively. The same parts as those in the first embodiment are designated by the same reference numerals and detailed description thereof will be omitted. This embodiment differs from the first embodiment in the method of controlling the threshold value of the transistors connected in series and the back gate structure, and discloses a so-called gate array configuration method. In this embodiment, the supporting substrate 5 is formed in p-type semiconductor, n-type back gate region 1 and the n-type back gate in the supporting substrate 5
DOO region 1 'is formed. These are p-type back gate regions 2 ′ of FIG. 10 electrically connected to the support substrate 5.
Are electrically isolated from each other.

As shown in FIG. 11, a p-type back gate region 2 is formed so as to be surrounded by an n-type back gate region 1 . The p-type back gate region 2 is electrically separated from the supporting substrate 5 by the n-type back gate region 1 . These p-type back gate region 2 and n-type back
The gate region 1 acts as the back gate electrode of the p-type MISFET.

P-type acting as back gate electrode
For one semiconductor island region facing the back gate region 2 and the n-type back gate region 1 through the insulating film 6,
A plurality of p-type MISFETs are formed. In the present embodiment, an example in which two semiconductor island regions are formed is shown, but more semiconductor island regions may be formed. here,
Adjacent p-type MIS formed in one semiconductor island region
The FET has a source / drain region 15 made of a p-type semiconductor shared by transistors connected in series. Furthermore, the p-type source / drain
A region 1 made of a p-type semiconductor, facing the rain region 15.
1 is formed. These areas 15 and 11
Form the source region and the drain region or the drain region and the source region of the p-type MISFET. Further, an n-type region 10 or a region 4 of p-type impurity addition of 10 ¹⁶ cm ⁻³ or less is formed so as to sandwich the gate electrode 10 and the gate insulating film 9 and serves as a channel region of the p-type MISFET.

[0052] As shown in FIG. 12, is formed 'p-type back gate region 2 so as to be surrounded by the' n-type back gate territory <br/> zone 1. The p-type back gate region 2 ′ is electrically separated from the supporting substrate 5 by the n-type back gate region 1 ′. The p-type back gate region 2 ′ and the n-type back gate region 1 ′ act as the back gate electrode of the n-type MISFET.

P-type acting as back gate electrode
Back gate region 2 'and the n-type back gate region 1'
A plurality of n-type MISFETs are formed for one semiconductor island-shaped region facing each other with the insulating film 6 interposed therebetween. In the present embodiment, an example in which two semiconductor island regions are formed is shown, but more semiconductor island regions may be formed. Here, adjacent n-type Ms formed in one island-shaped semiconductor region
The ISFET has a source / drain region 15 'made of an n-type semiconductor shared by transistors connected in series. Furthermore, the n-type region 1 is sandwiched by the gate electrode 10 '.
A region 11 'made of an n-type semiconductor is formed so as to face 5'. These regions 15 'and 11' are
The source region and the drain region or the drain region and the source region of the n-type MISFET are formed. Furthermore, a p-type region or region 4'made of n-type impurity addition of 10 ¹⁶ cm ^-3 or less is formed with the gate electrode 10 ′ and the gate insulating film 9 sandwiched therebetween, and becomes a channel region of the n-type MISFET.

Here, as shown in FIG. 10, n-type MISFE
It is desirable that the T and p-type MISFETs are formed in an array so as to form a multi-stage logic circuit by connecting metal wires. In this case, by forming the structure of FIG. 10 in the form of an array on the left and right sides of the paper, the semiconductor regions 1, 1'2, 2'to be the back gates are continuously connected,
Even if the voltage application terminals are not formed on the back gates of the individual arrays, the voltage can be applied to the back gates of all the arrays formed successively by forming the voltage application terminals at the array ends, for example.

Here, the gate electrodes 10 and 10 'are
Semiconductors with different conductivity types may be used to control the threshold. Specifically, the gate electrode 10 is a polysilicon electrode added with 10 ¹⁹ cm ⁻³ or more of B, and the gate electrode 10 ′ is 10 ¹⁹ cm.
^Any polysilicon electrode having P or As added to ^-3 or more may be used.

On the side surfaces of the gate electrodes 10 and 10 ', an insulating film 3 is formed from, for example, a silicon oxide film or a silicon nitride film. This is the gate electrode 10 and the source / drain region 15 or the source / drain region 1.
The purpose is to maintain good electrical insulation from No. 1. Further, the element isolation insulating film 13 made of, for example, a silicon oxide film is formed between the semiconductor island regions. further,
An interlayer insulating film 12 made of, for example, a silicon oxide film is formed on the MISFET.

A feature of this embodiment is that in the p-type MISFET as shown in FIG. 11, the support substrate 5 facing the channel region 4 with the insulating film 6 interposed therebetween has a conductivity opposite to that of the source / drain region 11. N-type back gate region having
1 is formed, and the p-type back gate region 2 having the same conductivity as the source / drain region 11 is formed on the supporting substrate 5 facing the source / drain region 15 shared by the adjacent transistors with the insulating film 6 interposed therebetween. It is that.

Complementarily, as shown in FIG.
In the SFET, the source / drain region 11 ′ is formed on the support substrate 5 facing the channel region 4 ′ with the insulating film 6 interposed therebetween.
A support substrate 5 having a p-type back gate region 2'having a conductivity opposite to that of the source / drain region 15 'shared by adjacent transistors and having an insulating film 6 interposed therebetween.
In addition, the n-type back gate region 1'having the same conductivity as the source / drain region 11 'is formed.

By adopting such a structure, it is possible to form in series two transistors whose threshold values change depending on the direction of the current flowing through the source / drain. First, FIG. 14 is used to show that the threshold value changes depending on the present back gate structure. FIG. 14A shows
FIG. 9 is a cross-sectional view corresponding to the extraction of one n-type MISFET of the present embodiment, which is a source / drain region 11 ′.
a and 11'b have electrodes 17a and 17 respectively.
b is connected. Further, a p-type back gate region 2 ′ is formed below 11 ′ a and a channel region with an insulating film 6 interposed therebetween. Here, the p-type back gate region 2 ′ is formed through the high-concentration p-type back gate region 2 ″,
It is electrically connected to the electrode 18. Although not shown in the figure, the electrode 18 is connected to a voltage source, p-type back gate <br/> region 2 'is controlled to be constant voltage. Furthermore, under the layer 11′b, an n-type back-gate is provided through the insulating film 6.
Over preparative region 1 'is formed. Where n-type back
The gate region 1 ′ is electrically connected to the electrode 18 ′ through the high-concentration n-type back gate region 1 ″. Although not shown in the figure, the electrode 18 ′ is connected to the voltage source and the n-type barrier region 1 ′.
Kkugeto region 1 'is controlled to be a constant voltage. Here, in order to suppress the power consumption of the voltage source, p-type
The, n-type bar so that a large leakage current flows in the back gate region 2 'and the n-type back gate region 1'
Or positively biased to than 'a p-type back gate region 2' Kkugeto region 1, it is necessary to bias below the forward voltage. Therefore, under such a condition, the potential DD ′ on the surface of the back gate is as shown in FIG. 14B, and the conduction band Ec and the valence band Ev are the depletion layer including the boundary between the regions 1 ′ and 2 ′. By n-type back
Towards the gate region 1 'is the structure to bend down. Therefore,
D side, that is, the channel 4'and the insulating film 6 close to 11'a
The interface with the p-type layer is in the accumulation state, and the interface between the channel 4 ′ near the 11′b and the insulating film 6 is in the inversion state of the p-type layer. . Therefore, as shown in FIG. 14C, when the electrode 17b is used as the drain electrode and the electrode 17a is used as the source electrode, the pentode threshold is such that the maximum point of the potential of the channel portion that determines the threshold is the channel. Since it is formed on the side of 17a rather than the side of 17b in 4 ', it becomes difficult to form an inversion layer, and it becomes a high threshold value. On the other hand, as shown in FIG. 14 (d), when the electrode 17a is the drain electrode and the electrode 17b is the source electrode, the pentode threshold value is the maximum potential of the channel portion that determines the threshold value. Since it is formed on the side of 17b in 17 'rather than on the side of 17a, the inversion layer is easily formed and the threshold value becomes low. From the above, depending on the direction of the source / drain electrodes, a difference in the threshold value is formed even under the same condition of the voltage applied to the back gate. In particular, in the case where the transistor is a fully depleted transistor, the depletion layer extending from the back gate portion reaches the channel portion as well, so that the threshold value is largely changed by the back gate potential, which is a desirable form in this embodiment.

Hereinafter, under the condition that the threshold value becomes high when used as a source electrode, a black circle is attached to the source electrode side to indicate the direction. As is clear from the above description, the potential of the back gate electrode facing the channel 4 ′ may be asymmetrical with respect to the source / drain in order to form the difference in threshold value. Therefore, the boundary between the p-type back gate region 2 ′ and the n-type back gate region 1 ′ may be formed not at the position facing the source region but at the position facing the channel 4 ′. p
Similarly, in the type MISFET, the boundary between the p-type back gate region 2 and the n-type back gate region 1 is formed not at a position facing the source region but at a position facing the channel 4. Good.

Next, FIG. 15 shows an example of a logic circuit using the transistor of this embodiment. FIG. 15A is a circuit diagram for a static 2-input NAND, and FIG.
FIG. 3 is a circuit diagram for a static 2-input NOR. Further, FIG. 16A shows the layout of the wiring layer for the static two-input NAND corresponding to FIG. 15A, and the transistor arrangement of FIG. 10 is used. 16B shows the layout of the wiring layer for the static two-input NOR corresponding to FIG. 16A, and the transistor arrangement of FIG. 10 is used.

First, in FIGS. 15A and 16A, Q _n1 and Q _n2 are n-type MISFETs having different threshold values depending on the current direction, and Q _p1 and Q n are shown.
_p2 is a p-type MISFET having a threshold value that differs depending on the current direction. It is desirable that these are formed to face each other as shown in FIG. 16A in order to suppress wiring delay. In FIG. 16 (a), 17, 17 'and 1
7 "indicates a metal wiring made of W, Cu or Al,
17 'is connected to VDD, 17 "is connected to 0 V. In addition, 26 is a p-type source / drain electrode 1
Shows contact electrodes for 1 or 15 and 2
6'is an n-type source / drain electrode 11 'or source
A contact electrode for the drain electrode 15 'is shown, and 26''is the gate electrode 10 or 10', 10 ''.
Shows a contact electrode for.

Here, the drain electrode of the side of Q _n2 which is not the common electrode is connected to the output node. Also, Q _n2
The source electrode serving as the common electrode of Q _n1 is connected to the drain electrode of Q _n1 . Further, the source electrode of Q _n1 is G
It is connected to ND and the voltage node 17 ″ having 0V, which is indicated in FIG. The gate electrode of Q _n1 is connected to the gate electrode of Q _{p1 and} serves as a first voltage input terminal (IN1). Further, the gate electrode of Q _n2 is connected to the gate electrode of Q _{n1 and} serves as a second voltage input terminal (IN2). Further, the source electrodes of Q _p1 and Q _n1 are both connected to a voltage node having a voltage of VDD, for example, and the drain electrode is connected to the output node. In other words, this configuration has a 2-input NAN.
The logic circuit of D is shown, IN1, IN2, OUT
Operates to have voltages corresponding to two logic values, approximately 0V and approximately VDD. Further, in FIG. 15, voltages V1, V2, V3, and V4 are applied to the regions 2 ', 1', 2, 1 as back gates, respectively. Here, in order to prevent forward current from flowing between the back gates so that no current flows, the
When t-in voltage is Vi, V3> V4-Vi, and V1
It is necessary to satisfy the condition of> V2-Vi.

[0064] In this circuit _{configuration,} the source electrode of _{Q n2,} for the series resistance of _{Q n1,} in a state where the input voltage of _{Q n1} and _{Q n2} is conductive for VDD, Vs than 0V
Only rises. On the other hand, the source electrode of Q _n1 is connected to 0 V, and the source voltage of Q _n2 is higher than that of Q _n1 . Therefore, when a transistor having a threshold value equal to Q _n1 and Q _n2 is used, the current driving capability of Q _n2 is
Compared with the current driving capacity of Q _n1 , the gate voltage is (VDD−
Vs) is reduced, which is equivalent to reduction. Therefore, Q
The transition time when _n2 is turned on is longer than the transition time when Q _n1 is turned on, which causes a difference in transition time due to a difference in input terminals, which causes a problem in the timing design of the circuit.

Here, as described in the first embodiment, in order to suppress the current driving capability deterioration of Q _n2 with respect to Q _n1 due to the increase of the source voltage, the threshold Vth2 of Q _n2 is set to Q _n1. It is necessary to make the condition lower than the threshold value Vth1. Especially, if Vth2 = Vth1−Vs,
The current driving capacities of Q _n2 and Q _n1 are substantially equal, and the delay times can be approximately equal regardless of the input terminals.

Here, in this embodiment, the current direction of Q _{n2 is} the direction in which the threshold value is low, and the current direction of Q _{n1 is} the direction in which the threshold value is high, so the n-type MIS is performed.
This condition can be satisfied by adjusting the back gate voltages V1 and V2 of the FET. At this time, current flows in both the p-type MISFETs Q _p1 and Q _p2 in the direction of increasing the threshold value. Therefore, two p-type MIS
The transition times when the FETs are turned on are almost equal, and the difference in transition times caused by the difference in the input terminals does not change even if the back gate voltages V1 and V2 are changed. That is,
In order to reduce the difference in the delay time of the present two-input NAND circuit due to the input terminals, V1 and V2 may be controlled so that the transition time when Q _{n1 is} on is substantially equal to the transition time when Q _{n2 is} on.

On the other hand, in FIGS. 15 (b) and 16 (b), Q _n1 and Q _n2 are n-type MISFETs having different threshold values depending on the current direction, and Q _p1 and Q n
_p2 is a p-type MISFET having a threshold value that differs depending on the current direction. It is desirable that these are formed to face each other as shown in FIG. 16B in order to suppress wiring delay. In FIG. 16 (b), 17, 17 'and 1
7 "indicates a metal wiring made of W, Cu or Al,
17 ′ is connected to VDD and 17 ″ is connected to 0V. The drain electrode of Q _p2 is connected to the output node. Further, the source electrode of Q _p2 is connected to the drain electrode of Q _p1. Further, the source electrode of Q _p1 is connected to a voltage node having, for example, VDD, and the gate electrode of Q _p1 is connected to the gate electrode of Q _n1 and the first voltage input terminal ( In addition, the gate electrode of Q _p2 is connected to the gate electrode of Q _{n2 and} serves as a second voltage input terminal (IN2), and the source electrodes of Q _n1 and Q _n2 are ,
Both are connected to, for example, a voltage node 17 ″ having a voltage of 0 V, and a drain electrode is connected to an output node. That is, the present configuration shows a 2-input NOR logic circuit, IN1, IN2, OUT. Operates to have voltages corresponding to two logic values, approximately 0V and approximately VDD.

In FIG. 15, as the back gate, V1, V2 and V are provided in the regions 2 ', 1', 2 and 1, respectively.
A voltage of 3, V4 is applied. Here, in order to prevent a current from flowing due to forward bias between the back gates, the built-in voltage between the back gates is set to Vi, and V
It is necessary to satisfy the conditions of 3> V4-Vi and V1> V2-Vi.

[0069] In this circuit _{configuration,} the source electrode of _{Q p2,} due to the series resistance of _{Q p1,} in a state where the input voltage of _{Q p1} and _{Q p2} is conductive for 0V, than VDD Vs
Only drops. On the other hand, the source electrode of Q _p1 is connected to 0 V, and the source voltage of Q _p2 is lower than that of Q _p1 . Therefore, when a transistor having a threshold value equal to Q _p1 and Q _p2 is used, the current driving capability of Q _p2 is
Compared with the current driving capability of Q _p1 , it corresponds to the increase of the gate voltage by Vs and decreases. Therefore, the transition time when Q _p2 is turned on is longer than the transition time when Q _p1 is turned on, and the transition time _{varies due} to the difference in the input terminals, which is a problem in the timing design of the circuit.

Here, as described in the first embodiment, in order to suppress the current driving capability deterioration of Q _p2 with respect to Q _p1 due to the increase of the source voltage, the threshold value Vth3 of Q _p2 is set to Q _p1. It is necessary to make the condition lower than the threshold value Vth4. Especially, if Vth4 = Vth3-Vs, then Q
The current driving capacities of _p2 and Q _p1 are substantially equal, and the delay times can be approximately equal regardless of the input terminals.

Here, in this embodiment, the current direction of Q _{p2 is} the direction in which the threshold value is low, and the current direction of Q _{p1 is} the direction in which the threshold value is high, so that the p-type MIS is formed.
This condition can be satisfied by adjusting the back gate voltages V3 and V4 of the FET. At this time, current flows through both n-type MISFETs Q _n1 and Q _n2 in the direction of increasing the threshold value. Therefore, two n-type MISs
The transition times for turning on the FETs are almost equal, and the difference in transition time caused by the difference in the input terminals does not change even if the back gate voltages V3 and V4 are changed. That is, in order to reduce the difference between the delay times of the two-input NOR circuit depending on the input terminals, V3 and V4 may be controlled so that the transition time when Q _{p1 is} on is substantially equal to the transition time when Q _{p2 is} on. .

From the above, even if the NAND circuit and the NOR circuit of the present embodiment are formed on the same substrate and share the back gate terminal, the transition time difference caused by the difference of the input terminals is independently V1 and V2. , V3 and V4 can be minimized respectively. Therefore, in a logic circuit in which these and one-input inverters are combined, it is possible to minimize the shift in delay time due to the difference in input terminals.

FIG. 17 (b) is a circuit diagram for the clocked inverter, and FIG. 17 (a) shows the layout of the wiring layer for the clocked inverter corresponding to FIG. 17 (b). The arrangement is used. 17 (a) and 17 (b),
Q _n1 and Q _n2 are n-type MISFETs having different threshold values depending on the current direction, and Q _p1 and Q _p2 are p-type MISFE having different threshold values depending on the current direction.
T. It is desirable that these are formed to face each other as shown in FIG. 17A in order to suppress wiring delay. In FIG. 17A, 17, 17 'and 17 "are
A metal wire made of W, Cu, or Al is shown, 17 'is connected to VDD, and 17 "is connected to 0 V. Here, the drain electrode on the side other than the common electrode of Q _{n 2} serves as an output node. are connected. the common electrode to become the source electrode of Q _n2 is connected to the drain electrode of Q _n1. in addition, the source electrode of Q _n1 has a 0V that is denoted in GND and 15 Voltage node 1
7 '' is connected. Further, the drain electrode of the side of Q _p2 which is not the common electrode is connected to the output node.
In addition, the source electrode that serves as the common electrode of Q _p2 is connected to the drain electrode of Q _p1 . Further, the source electrode of Q _p1 is connected to GND and to the voltage node 17 ″ having 0 V, which is labeled in FIG.

The gate electrode of Q _n2 is connected to the gate electrode of Q _p2 , and the voltage input terminal (I
N). Further, the gate electrode of Q _n1 is connected to the clock input fai, and the gate electrode of Q _p1 is
It is connected to the inverted input / fai of the clock input.
That is, in this configuration, an inverted output of IN is obtained when fai is VDD and / fai is 0V, and when fai is 0V and / fai.
Shows a logic circuit of a clocked inverter whose output is in a high impedance state when is VDD, IN, fa
i, / fai, and OUT operate to have voltages corresponding to two logic values of approximately 0 V and approximately VDD.
Further, in FIG. 15, as the back gate, V1, V2, V3 are respectively provided in the regions 2 ', 1', 2, 1.
The voltage of V4 is applied. Here, in order to prevent forward current due to forward bias between the back gates,
V3> V where Vi is the built-in voltage between the back gates
It is necessary to satisfy the conditions of 4-Vi and V1> V2-Vi.

[0075] In this circuit _{configuration,} the source electrode of _{Q n2,} for the series resistance of _{Q n1,} in a state where the input voltage of _{Q n1} and _{Q n2} is conductive for VDD, Vs than 0V
Only rises. Therefore, the current driving capacity of Q _n2 is Q
Compared with the case where the source electrode of _n2 is grounded to 0V, the gate voltage is reduced by (VDD-Vs). On the other _hand, the source electrode of _{Q p2,} due to the series resistance of _{Q p1,} the input voltage of _{Q p1} and _{Q p2} is in a state where the conduction 0V, thereby lowering only the Vs than VDD. _Therefore, the current driving capability of the _{Q p2 is} the source electrode of _{Q p2} V
Compared to the case of connecting to DD, the gate voltage is increased by Vs, and is decreased. Therefore, compared with a normal inverter in which the source electrode of Q _p2 is connected to VDD and the source electrode of Q _n2 is connected to 0 V, the delay time of the present inverter increases even with the same transistor size. In addition, since the current driving capability of Q _p2 and Q _n2 is lowered, the delay time of the output signal with respect to the signal added to IN increases as compared with the input to the clock signals fai and / fai, which is a problem in the timing design of the circuit. .

Here, as described in the first embodiment, in order to suppress the current driving capability deterioration of Q _n2 with respect to Q _n1 due to the increase of the source voltage, the threshold Vth2 of Q _n2 is set to Q _n1. It is necessary to make the condition lower than the threshold value Vth1. Especially, if Vth2 = Vth1−Vs, then Q
The current driving capacities of _n2 and _Qn1 are made substantially equal, and the delay times can be made almost equal regardless of the input terminals. Further, in order to suppress the decrease in the current driving capability of Q _p2 with respect to Q _p1 due to the increase in the source voltage, the threshold value Vth3 of Q _p2 is set to Q.
_It is necessary to set the condition to be lower than the threshold value Vth4 of _p1 .
In particular, when almost Vth4 = _{Vth3-Vs, Q p2} and Q
The current drive capability of _p1 becomes almost equal, and the delay time can be made almost equal regardless of the input terminal.

Here, in the present embodiment, the current direction of Q _{n2 is} the direction in which the threshold value is low, and the current direction of Q _{n1 is} the direction in which the threshold value is high.
This condition can be satisfied by adjusting the back gate voltages V1 and V2 of the FET. Further, in the present embodiment, the current direction of Q _{p2 is} the direction in which the threshold value is low, and the current direction of Q _{p1 is} the direction in which the threshold value is high, so the back gate voltage V3 of the p-type MISFET This condition can be satisfied by adjusting V4 and V4.

From the above, the output delay time of the input IN can be made equal to or shorter than the output delay time with respect to the clock inputs fai and / fai, and an inverter switching at a higher speed can be formed.

The feature of suppressing the deterioration of the current drivability in the case of cascade-connecting the transistors whose thresholds differ depending on the direction of current flow is not limited to the static logic circuit described above, and is also applicable to more multi-inputs. It can also be used in a logic circuit or a dynamic circuit, and the difference in delay time depending on its input terminal can be shortened.

According to this embodiment, the following effects can be obtained. (1) Regions 1, 1 ′, 2, 2 ′ that act as back gate electrodes of transistors are electrically isolated from the support substrate 5. Therefore, the region to which the back gate is applied can be made smaller than the entire chip, and the region 1,
The capacity of 1 ', 2, 2'can be reduced. Therefore, as the substrate bias power source connected to the regions 1, 1 ', 2, 2', a power source having a smaller capacity can be used, and the circuit area and power consumption of the substrate bias power source can be reduced. Further, the influence of noise through the substrate is reduced, and a low-noise circuit can be stably realized.

[0081] (2) the voltage of the n-type back gate region 1 which acts as a back gate electrode 11 and p-type back gate
P-type MI by controlling the voltage of the gate region 2.
It is possible to control the threshold value of the SFET and the difference between the threshold values depending on the current directions of the source and the drain.
In addition, the n-type bar that functions as the back gate electrode in FIG.
The threshold voltage of the n-type MISFET and the difference between the threshold values of the source and drain depending on the current direction can be controlled independently by controlling the voltages of the gate gate region 1 ′ and the p-type back gate region 2 ′. . Therefore, for example, it is possible to optimize the delay time of the logic circuit by controlling the difference in threshold value by the external voltage input after the semiconductor element is formed up to the wiring layer and the actual operation state is achieved.

(3) The difference between the maximum delay and the minimum delay of the NOR or NAND circuit and the clocked inverter logic circuit can be shortened without changing the wiring layout pattern. Therefore, the time required for the synchronization margin of the logic circuit can be further reduced, and the logic circuit can be operated at a higher speed.

(4) Compared with the case where a back gate of the same conductivity type as the source / drain region is formed as the back gate of the MISFET on the entire lower surface of the source / drain layer and the channel layer, the source / drain region is opposite to that of the source / drain region. It is possible to reduce the capacitance of one of the source / drain layers in which the conductive type back gate is formed with respect to the back gate. In particular, when a back gate of the opposite conductivity type is formed in the drain region, when the drain voltage is high, the back gate region is depleted and the drain capacitance with respect to the back gate is reduced. It is possible to reduce the load capacitance of the circuit output and operate at high speed.

On the other hand, the depletion of the back gate region facing the channel is small as compared with the case where the back gate of the conductivity type opposite to that of the source / drain region is formed on the entire lower surface of the source / drain layer and the channel layer. As a result, the channel potential can be kept constant, and the threshold value is less likely to decrease even if the gate length becomes shorter.

(5) As shown in regions 1 and 2'of FIG. 10, a semiconductor region having one conductivity type and serving as a back gate can be shared by two transistors. Therefore, even if the gate length becomes smaller than the length along the gate length of the source / drain regions, the length of the regions 1 ′ and 2 ′ in the channel direction can be secured wider than the gate length. Therefore, the backgate design rule can be relaxed more than the gate design rule.
The back gate can be formed using an inexpensive lithographic apparatus with lower resolution. Further, since the widths of the regions 1'and 2'can be secured wide, the back gate resistance can be kept small, and a stable back gate voltage can be applied even if the channel width is increased.

FIG. 18 shows a structural plan view of the third embodiment of the present invention. 18 is a top view in which the wiring layer and the contact layer are omitted, and FIGS. 19A and 19B are cross-sectional views taken along arrows AA ′ and BB ′ of FIG. 10, respectively.
The same parts as those of the first and second embodiments are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment is partially different from the second embodiment in the method of controlling the threshold value of the transistors connected in series and the element isolation structure. In FIG. 19, two p-type MISFETs are connected in series and two n-type MISFETs are connected in series.
Is formed.

Adjacent p-type MISFETs formed in one semiconductor island region shown in FIG. 19A are provided with source / drain regions 15 made of p-type semiconductors shared by transistors connected in series. Further, the gate electrode 10 is sandwiched between the source / drain region 15 and p,
A region 11 made of a type semiconductor is formed. these,
The region 15 and the region 11 form the source region and the drain region or the drain region and the source region of the p-type MISFET. Furthermore, the region 4 formed by the addition of the n-type impurity under the gate electrode 10 and the gate insulating film 9 is p
Type MISFET. here,
An undepleted region under this channel region (see FIG. 19).
The dotted line portion) is referred to as a body region 20.

[0088] Further, on the lower or side of the junction between the p-type source and drain regions 11 and n-type body region 20, for example ¹⁰ 18 ^~10 20 ^{cm -3} P as an n-type impurity, A
a region 19 added with s or Sb is formed,
The tunnel leak current of the pn junction is set to increase. Here, the region 19 is the source / drain region 11
Are not formed in the source / drain region 15 and the dummy source / drain region 11 '''which are selectively formed in contact with the common source / drain region 15'''. Further, a dummy gate electrode 10 ″ for field shield isolation is formed on the side surface of the region 11 on the side where the gate electrode 10 is not formed. In this dummy gate, a dummy source / drain region 11 ″ ′ having the same conductivity type as the dummy 11 in a portion in contact with the side surface of the element isolation 13 made of, for example, an oxide film is electrically separated from the source / drain region 11. The gate is for reducing the influence of side leakage along the element isolation 13 between the dummy source / drain region 11 ′ ″ and the substrate 4, and is normally connected to VDD and is in a cutoff state. There is. Also, the dummy gate 1 in the center of the figure
0 ″ is for separating the source / drain regions 11 of the two p-type MISFETs from each other by the field shield, and is normally connected to VDD and is in a cutoff state. Figure 1
9 shows an example in which four p-type MISFETs used as circuit elements, that is, Q _p1 , Q _p2 , Q _p3 , and Q _p4 are formed in one semiconductor island region, but AA ′. A larger number may be formed by extending the semiconductor island region in the direction and forming the field shield gate.

On the other hand, the adjacent n-type MISFET formed in one semiconductor island region shown in FIG. 19B is provided with a source / drain region 15 'made of an n-type semiconductor shared by transistors connected in series. ing. Further, the n-type source / drain region 1 is sandwiched by the gate electrode 10 '.
A source / drain region 11 'made of an n-type semiconductor is formed so as to face 5'. The region 15 'and the region 11' form the source region and the drain region or the drain region and the source region of the n-type MISFET. Further, the region 4 ′ formed by adding the p-type impurity under the gate electrode 10 ′ and the gate insulating film 9 is the n-type MI.
It is the channel region of the SFET.

Further, the n-type source / drain region 11 '
Below or on the side surface of the junction between the p-type body region 20 'and
For example, a region 19 'in which B or In is added as 10 ¹⁸ to 10 ²⁰ cm ⁻³ n-type impurity is formed, and the tunnel leak current of the pn junction is set to increase. Here, the region 19 ′ is selectively formed in contact with the source / drain region 11 ′ and is shared, and the source / drain region 15 ′ and the dummy source / drain region 1 are shared.
It is not formed in 1 ''''. Further, a dummy gate electrode 10 ″ for field shield separation is formed on the side surface of 11 ′ on the side where the gate electrode 10 ′ is not formed. In this dummy gate electrode 10 ″, a dummy source / drain region 11 ″ ″ having the same conductivity type as the dummy 11 ′ in the side contact with the element isolation 13 made of, for example, an oxide film is formed as a source / drain region. 11 '
Is a gate for electrically isolating the dummy source / drain region 11 ″ ″ and the substrate 4 ′ to reduce the influence of side leakage along the element isolation 13 and is normally 0 V. Is connected to and is in the cutoff state.
Further, the dummy gate electrode 10 ″ in the center of the figure is for separating the source / drain regions 11 of the two n-type MISFETs from each other by the field shield, and is normally 0.
It is connected to V and is in a cutoff state. In FIG. 19, four n-type MISFETs used as circuit elements, that is, Q _n1 , Q _n2 , and Q, for one semiconductor island region.
_Although an example in which _n3 and _Qn4 are formed is shown, a _{larger number} may be formed by extending the semiconductor island region in the BB 'direction to form the field shield gate.

Here, as shown in FIG. 18, n-type MISFE is used.
It is desirable that the T and p-type MISFETs are formed in an array so as to form a multi-stage logic circuit by connecting metal wires. Here, the gate electrodes 10 and 10 '
May be semiconductors with different conductivity types to control the threshold. Specifically, the gate electrode 10 is a polysilicon electrode added with 10 ¹⁹ cm ⁻³ or more of B, and the gate electrode 10 ′ is 10 ¹⁹ c.
^Any polysilicon electrode having P or As added to m ⁻³ or more may be used.

On the side surfaces of the gate electrodes 10 and 10 ', an insulating film 3 is formed from, for example, a silicon oxide film or a silicon nitride film. This is the gate electrode 10 and the source / drain region 15 or the source / drain region 1.
The purpose is to maintain good electrical insulation from No. 1. Further, the element isolation insulating film 13 made of, for example, a silicon oxide film is formed between the semiconductor island regions. further,
An interlayer insulating film 12 made of, for example, a silicon oxide film is formed on the MISFET.

What is characteristic of this embodiment is that in FIG.
In (a), the same conductivity as that of the body region 20 is provided so that the p-type source / drain region 15 that is shared by the adjacent transistors is in contact with the lower portion or the side face of the p-type source / drain region 11 that faces the gate electrode 10. Have
In addition, the n-type semiconductor region 19 having a high impurity concentration is formed, and the resistance when the body region 20 and the source / drain region 11 are reverse biased is made smaller than the resistance between the body region 20 and the source / drain region 15. It is that you are.

Further, in FIG. 19B, the n-type source / drain region 1 shared by adjacent transistors is formed.
The p-type semiconductor region 1 having the same conductivity as that of the body region 20 'so as to be in contact with the lower portion or the side surface of the n-type source / drain region 11' that faces the 5'and the gate electrode 10.
9 ′ is formed, and the resistance when the body region 20 ′ and the source / drain region 11 ′ are reverse biased is the body region 2.
0 ′ and the resistance between the source / drain region 15 ′.

By doing so, the current driving capability can be made different depending on the direction of the source / drain. To explain this, for example, FIG.
In the n-type MISFET denoted by Q _n1 , in the case where 11 ′ is grounded to 0V to be a source region and 15 ′ is VDD to be a drain electrode, the region 11 ′ and the body region 2 are formed.
Since the resistance between the region 0'and the region 15 'is lower than the resistance between the region 15' and the body region 20 ', the resistance division brings the voltage of the body close to 0V. On the contrary, when 15 ′ is grounded to 0V to be a source region and 11 ′ is VDD to be a drain electrode, the resistance between the region 11 ′ and the body region 20 ′ is equal to that of the region 15 ′ and the body region 20 ′. Since the resistance is lower than the resistance between V and, the voltage of the body becomes close to VDD due to the resistance division. Here, in the n-type MISFET, when the body voltage decreases, the threshold value increases due to the substrate bias effect. Therefore, the threshold value becomes lower when 15 ′ is the source region than when 15 ′ is the drain region. . In particular,
When the transistor is a partially depleted transistor, an electrically neutral body region is formed, which is a desirable form in this embodiment.

From the above, it is apparent that a logic circuit similar to that described in the second embodiment can be formed by using a transistor whose threshold value changes depending on the direction of current flow. For example, FIG. 20B shows a circuit diagram for a static 2-input NAND, and FIG.
The layout of the wiring layer with respect to the static 2-input NAND corresponding to (b) is shown. These use the transistor arrangement of FIG. VDD power supply line 17 'for the field shield gate 10''of the p-type MISFET
Connection contact 26 '' with n-type MISFE
VDD for T field shield gate 10 ''
Except for the connection contact 26 '' with the power line 17 '',
A circuit and a layout can be configured in the same manner as in FIGS. 16A and 15A. Although not shown in the figure, the second
It is obvious that other logic elements, two-input NORs, and clocked gates of the above embodiment can be similarly formed.

In this embodiment, the regions 19 and 19 'are
For example, Ar, N2, Ge, and F2 are 10 ¹³ to 10 ¹⁶ c
The regions formed by the m ⁻² implantation are regions 11 and 11 ′.
It may be formed and replaced within the depletion layer and the diffusion length of minority carriers from the body. With such ions, a defect serving as a generation center is formed at the junction between the source / drain layer and the body electrode, and the reverse current increases, so that the same effect can be obtained.

In this embodiment, (3) of the second embodiment is used.
In addition to the above effects, the following effects can be obtained. (1) By adjusting the impurity addition amount and position of 19, it is possible to control the difference in threshold between the source and drain of the p-type MISFET depending on the current direction. Further, by adjusting the amount and position of the impurity added in 19 ', the difference in threshold value between the source and drain of the n-type MISFET in the current direction can be controlled independently of the p-type MISFET.

(2) The region 11 or 11 'having poor junction characteristics serves as the drain only when the transistors are formed in series, and normally the junction property is good 15 or 1
The 5'region can be used as a drain. Therefore, the drain breakdown voltage can be improved as compared with the case where 19 ′ is formed in all the source / drain regions. Furthermore, when a current is caused to flow through the transistors connected in series, voltage distribution is caused by the plurality of transistors, so that the voltage applied between the drain and source of each transistor decreases. Therefore, in this case, the probability that electron-hole pairs are generated is reduced, and the deterioration phenomenon due to hot electrons is less likely to occur.

[0100]

As described above, according to the present invention, in the semiconductor device having the gate array structure, the back gate electrode is provided in the support substrate facing the channel region of each transistor, and the position facing the drain is provided. In this case, a depletion layer is formed on the support substrate. Therefore, the parasitic capacitance between the source / drain electrodes and the supporting substrate is reduced.

[Brief description of drawings]

FIG. 1 is an SOI-MI according to a first embodiment of the present invention.
The schematic sectional drawing of SFET.

FIG. 2 is an SOI-MI according to the first embodiment of the present invention.
The schematic sectional drawing of SFET.

FIG. 3 is an SOI-MI according to the first embodiment of the present invention.
The schematic plan view of SFET.

FIG. 4 is an SOI-MI according to the first embodiment of the present invention.
Schematic circuit diagram of the SFET.

FIG. 5 is an SOI-MI according to the first embodiment of the present invention.
Schematic circuit diagram of the SFET.

FIG. 6 is an SOI-MI according to the first embodiment of the present invention.
Schematic circuit diagram of the SFET.

FIG. 7 is a graph of back gate voltage dependence of threshold value according to the first embodiment of the present invention.

FIG. 8 is a graph of a back gate voltage that realizes a constant threshold voltage according to the first embodiment of the present invention.

FIG. 9 is a graph of back gate voltage that realizes constant current driving capability according to the first embodiment of this invention.

FIG. 10 is an SOI-M according to the second embodiment of the present invention.
The schematic plan view of ISFET.

FIG. 11 is an SOI-M according to the second embodiment of the present invention.
The schematic sectional drawing of ISFET.

FIG. 12 is an SOI-M according to the second embodiment of the present invention.
The schematic sectional drawing of ISFET.

FIG. 13 is an SOI-M according to the second embodiment of the present invention.
The schematic sectional drawing of ISFET.

FIG. 14 is a diagram illustrating a threshold change in the source / drain direction of the transistor according to the second embodiment of the present invention.

FIG. 15 is an SOI-M according to the second embodiment of the present invention.
Schematic circuit diagram of ISFET.

FIG. 16 is an SOI-M according to the second embodiment of the present invention.
The schematic plan view of ISFET.

FIG. 17 is an SOI-M according to the second embodiment of the present invention.
The schematic plan view and circuit diagram of ISFET.

FIG. 18 is an SOI-M according to the third embodiment of the present invention.
The schematic plan view of ISFET.

FIG. 19 is an SOI-M according to the third embodiment of the present invention.
The schematic sectional drawing of ISFET.

FIG. 20 is an SOI-M according to the third embodiment of the present invention.
The schematic plan view and circuit diagram of ISFET.

FIG. 21 is a schematic sectional view of a conventional SOI-MISFET.

FIG. 22 is a schematic circuit diagram of a conventional SOI-MISFET.

[Explanation of symbols]

1 n-type back gate region 2 p-type back gate region 3 insulating film 4 channel region 5 supporting substrate 6 insulating film 7 voltage source 8 voltage supply control circuit 9 gate insulating film 10 gate electrode 11 source / drain region 12 interlayer insulating film 13 Element isolation insulating film 14 Contact 15 Source shared by transistors connected in series
Drain region 16 contacts 17 and 18 electrode 19 p-type semiconductor region 20 body region

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (4)

(57) [Claims] 1. An insulating film, a first conductivity type first impurity region formed on the insulation film, and a second conductivity type first impurity region formed adjacent to the first impurity region. A channel region, a second impurity region of the first conductivity type formed adjacent to the first channel region, and a second impurity region of the second conductivity type formed adjacent to the second impurity region. A channel region; a third impurity region of the first conductivity type formed adjacent to the second channel region; a first gate insulating film formed on the first channel region; A second gate insulating film formed on the second channel region, a first gate electrode formed on the first gate insulating film, and a second gate insulating film formed on the second gate insulating film. And a gate electrode formed directly below the first channel region via the insulating film. A first conductivity type first back gate region, a first conductivity type second back gate region formed directly below the second channel region with the insulating film interposed therebetween, and the first back gate region And a second power source for supplying a second potential different from the first potential to the second back gate region. apparatus. 2. The semiconductor device according to claim 1, further comprising a first semiconductor region of a second conductivity type that covers the first and second back gate regions. 3. An insulating film, a first impurity region of the first conductivity type formed on the insulating film, and a first impurity region of the second conductivity type formed adjacent to the first impurity region. A channel region, a second impurity region of the first conductivity type formed adjacent to the first channel region, and a second impurity region of the second conductivity type formed adjacent to the second impurity region. A channel region; a third impurity region of the first conductivity type formed adjacent to the second channel region; a first gate insulating film formed on the first channel region; A second gate insulating film formed on the second channel region, a first gate electrode formed on the first gate insulating film, and a second gate insulating film formed on the second gate insulating film. And a first conductive layer formed under the second impurity region via the insulating film. An electric conductivity type fourth impurity region, a second conductivity type fifth impurity region that covers the fourth impurity region, a first power supply that supplies a first potential to the fourth impurity region, A second power supply that supplies a second potential different from the first potential to the fifth impurity region, the semiconductor device. 4. An insulating film, a first impurity region of the first conductivity type formed on the insulating film, and a first impurity region of the second conductivity type formed adjacent to the first impurity region. A channel region, a second impurity region of the first conductivity type formed adjacent to the first channel region, and a second impurity region of the second conductivity type formed adjacent to the second impurity region. A channel region; a third impurity region of the first conductivity type formed adjacent to the second channel region; a first gate insulating film formed on the first channel region; A second gate insulating film formed on the second channel region, a first gate electrode formed on the first gate insulating film, and a second gate insulating film formed on the second gate insulating film. And a first conductive layer formed under the second impurity region via the insulating film. A fourth impurity region of electrical conductivity type, fifth and sixth impurity regions of second conductivity type that face each other with the fourth impurity region interposed therebetween, and a first potential is applied to the fifth impurity region. A first power supply for supplying the second power to the sixth impurity region having a second potential different from the first potential;
And a second power supply for supplying the electric potential of the semiconductor device.