JP2002368210A - Power mos transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power MOS transistor which can have a desired sub strate potential, while being reduced in element area. SOLUTION: A channel region is formed in the surface layer of an N-type silicon substrate 1, and a source area is formed in the surface layer of the channel region. On the surface side of the N-type silicon substrate 1, a gate electrode is arranged at least to a portion of the channel region across a gate insulating film. On the top surface side of the N-type silicon substrate 1, a source electrode is arranged in contact with the source region through a contact hole. In neither the contact hole for a source nor a source cell at its peripheral part, a body contact region to be at the substrate potential is provided, a body contact region 14 is provided outside the source cell, and another electrode 15 is extended from the source electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOS transistor.

[0002]

2. Description of the Related Art As a conventional technique, in a stripe type LDMOS using a multilayer wiring structure, a wiring area can be reduced by using a multilayer wiring to reduce wiring resistance. An example of this structure is shown in FIGS. In this case, as shown in the plan view of FIG. 20, it has a stripe type conventional structure. Each terminal of the source, drain, and gate leads a different wiring. However, regarding the substrate potential, as shown in FIG.
⁺ P ⁺ body contact region 1 in addition to source region 101
02 is formed to have a substrate potential common to the source.
To control the substrate potential and the source potential independently,
As shown in FIG. 22, it is necessary to increase the contact portion in the source cell, and the area occupied by the source cell increases, which results in a problem that the element area increases.

[0003]

SUMMARY OF THE INVENTION The present invention has been made under such a background, and an object of the present invention is to provide a power MOS transistor which can obtain a desired substrate potential while reducing the element area. To provide.

[0004]

In the power MOS transistor according to the present invention, a body contact region for obtaining a substrate potential is provided in a source or emitter contact hole and in a source or emitter cell at a peripheral portion thereof. Is provided, and a body contact region is provided outside the cell. This allows
A desired substrate potential can be obtained while reducing the element area.

A power MOS transistor according to a second aspect of the present invention is the power MOS transistor according to the first aspect, wherein an electrode different from the source or emitter electrode is extended from a body contact region provided outside the source or emitter cell. It is characterized by having been established. Then, a substrate potential control circuit for controlling the substrate potential is connected to an electrode extending from the body contact region provided outside the source or emitter cell. This will increase versatility.

According to a fourth aspect of the present invention, in the power MOS transistor according to the third aspect, the substrate potential control circuit applies a voltage for making the potential difference between the gate electrode and the substrate constant by turning on and off the transistor. It is characterized by being. Thereby, switching characteristics can be improved.

A power MOS transistor according to a fifth aspect of the present invention is the power MOS transistor according to the third aspect, wherein the substrate potential control circuit applies a reverse bias to the substrate when the transistor is off. Thereby, the threshold voltage Vt can be optimized.

According to a sixth aspect of the present invention, in the power MOS transistor of the third aspect, a plurality of body contact regions are provided in the transistor forming region, and the substrate potential control circuit corresponds to each body contact region. This is characterized in that the on / off control of the transistor cell is controlled independently. This makes it possible to control the output current of the entire device.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a plan view of a power MOS transistor according to the present embodiment.
This power MOS transistor is an N-channel LDMO
S, which has a stripe-type conventional structure. Further, as shown in the vertical cross-sectional view of FIG. 6, it is a stripe type LDMOS using a multilayer wiring structure.

FIG. 2 is a plan view of the outermost layer of the semiconductor substrate, showing the arrangement of cells (source cell S, drain cell D, and substrate contact cell B). FIG. 3 shows the gate wiring 17 on the cell, and FIG. 4 shows the source second-layer wiring 18 and the drain second-layer wiring 19. FIG. 5 shows a substrate potential wiring 22.

FIG. 6 is a sectional view taken along line U--U of FIG.
FIG. 3 is a vertical cross-sectional view of a (source cell / drain cell). FIG. 7 is a longitudinal sectional view taken along line VV (drain cell / substrate contact cell / drain cell) of FIG. FIG. 8 is a longitudinal sectional view taken along line WW (substrate contact cell / source cell / source cell / source cell) of FIG.

In the source cell of FIG. 6, a channel P well region 2 is formed in a surface layer portion of an N type silicon substrate (a semiconductor region of the first conductivity type) 1 and a channel P well region 2 is formed in a surface layer portion of the channel P well region 2. An N ⁺ source region 3 is formed. On the surface side (upper surface side) of N-type silicon substrate 1, a polysilicon gate electrode 5 is arranged via a gate oxide film (gate insulating film) 4 at least for a part of channel P well region 2. . The polysilicon gate electrode 5 is covered with a silicon oxide film 6.
Further, on the front side (upper side) of the N-type silicon substrate 1, a source electrode (source first layer wiring) 7 made of aluminum is arranged on the silicon oxide film 6, and the source electrode (aluminum layer) 7 is formed. Is N ⁺ through contact hole 8
It is in contact with the source region 3. A source cell is formed in the contact hole 8 and its peripheral portion, and a large number of such source cells are formed as shown in FIG. In particular, with respect to the layout of the source cells S, the source cells S are linearly and continuously arranged, and a large number of source cell groups forming this column are arranged.

Further, in the drain cell of FIG.
An N well layer 9 is formed in a surface layer portion of the mold silicon substrate 1, and an N ⁺ region 10 is formed in a surface layer portion of the N well layer 9. A drain electrode (drain first layer wiring) 11 made of aluminum is arranged on the silicon oxide film 6 described above, and this drain electrode (aluminum layer) 11 is in contact with the N ⁺ region 10 through a contact hole 12. . The inside of the contact hole 12 and the periphery thereof become drain cells, and a large number of such drain cells are formed as shown in FIG. In particular, regarding the layout of the drain cells D, the drain cells D are arranged linearly and continuously, and a large number of drain cell groups forming this column are arranged in parallel. In FIG. 2, the columns of the source cells and the columns of the drain cells are arranged alternately.

As shown in FIG. 6, a LOCOS oxide film 1 is provided between cells (for example, between a source and a drain cell).
3 are formed. Further, the substrate contact cell of FIG. 7 is formed at a position where the source cell is to be originally arranged in the source cell group arranged in a row. In this substrate contact cell, a P well layer 2 is formed in a surface layer portion of an N-type silicon substrate 1 and a P well layer 2 is formed.
The P ⁺ body contact region 14 is provided on the surface layer of the well layer 2.
Are formed. A substrate potential dedicated electrode 15 made of a metal such as aluminum is arranged on the silicon oxide film 6. The substrate potential dedicated electrode (aluminum layer) 15 passes through the contact hole 16 to the P ⁺ body contact region 1.
4 is in contact. The inside of the contact hole 16 and the periphery thereof become substrate contact cells, and a large number of such substrate contact cells are formed as shown in FIG.
In particular, regarding the layout of the substrate contact cells B, the substrate contact cells B are arranged every few cells in the source cell row.

That is, in the stripe type LDMOS, a region dedicated to the substrate potential contact is provided in a part of the source cell column by utilizing the fact that the substrate portion is common in each source cell column. Thus, the substrate potential can be controlled independently of the source without increasing the element area.

In the multilayer wiring structure, a gate wiring 17 is arranged as shown in FIG. 3, and the above-mentioned polysilicon gate electrode 5 is connected to the wiring 17 at the outer periphery of the element (transistor formation region). Further, as shown in FIG. 4, a source second-layer wiring 18 and a drain second-layer wiring 19 are formed. The source second layer wiring 18 is connected to the via hole 2
0 is connected to the source wiring (source electrode) 7 of the first layer. On the other hand, the second-layer drain wiring 19 in FIG. 4 is connected to the first-layer drain wiring (drain electrode) 11 through the via hole 21. Further, as shown in FIG. 5, a substrate potential wiring 22 is formed, and this substrate potential wiring 22
5 is connected. Therefore, the substrate potential at each location can be extracted by the common wiring 22.

Referring to FIGS. 6, 7, and 8, the multilayer wiring structure will be described. A silicon oxide film 23 is formed on a drain electrode (aluminum layer) 11 and a source electrode (aluminum layer) 7, and a source second layer is formed thereon. A layer wiring 18 and a drain second layer wiring 19 are formed.

In such a MOSFET, FIG.
As shown in FIG. 5, when a voltage is applied to the polysilicon gate electrode 5, a current from the drain electrode (aluminum layer) 11 becomes N
⁺ Region 10 → N well layer 9 → surface layer of channel P well region 2 → N ⁺ region 3 → source electrode (aluminum layer) 7.

As a circuit configuration, as shown in FIG. 9, a power MOS transistor Tr1, a gate drive circuit 30, and a substrate potential control circuit 40 are formed in a chip. A load is connected to the power MOS transistor Tr1 outside the chip. This external load is arranged on the drain side of the power MOS transistor Tr1, the source is grounded, and the power MOS transistor T1 is connected to the ground side with respect to the load arranged between the high potential and the ground side.
r1 is arranged. The gate drive circuit 30 is provided with a buffer 31, and a transistor drive command signal (transistor ON / OFF signal) φ0 is input to the gate terminal of the power MOS transistor Tr1 via the buffer 31. The substrate potential control circuit 40 includes an operational amplifier 41 and a resistor 4
2 and 43, and a signal obtained by inverting the transistor drive command signal φ0 described above is supplied to the operational amplifier 41 via the resistor 43.
Is input to the non-inverting input terminal. The operational amplifier 41
Have a positive power supply voltage (+12 volts) and a negative power supply voltage (−12 volts).
Bolt) is connected. Further, the output terminal of the operational amplifier 41 is connected to the substrate potential dedicated electrode 15 of each substrate contact cell B via the substrate potential wiring 22 of FIG.

Here, a power MOS transistor (LD)
The MOS transistor Tr1 has a parasitic capacitance C1 due to its structure, and charging and discharging of the parasitic capacitance C1 causes a delay in switching. In this circuit configuration, the transistor
When turned off (gate voltage = 0 volt), the substrate voltage is -V
g (eg, -5 volts). On the other hand, when the transistor is turned on (for example, Vg = 5 volts), the substrate potential is set to 0 volt. By doing so, the potential difference between the gate potential and the substrate potential becomes constant. This allows
There is no charge / discharge in the parasitic capacitance C1, the switching delay is reduced, and the control stability of the buffer 31 is improved.

Thus, for the element body of FIG.
It comprises a source cell S, a drain cell D and a substrate contact cell B, and the columns of the source cell S and the drain cell D are alternately arranged, and the substrate contact cells B are arranged every few cells in the source cell column. By providing the substrate contact portion separately from the source portion, the substrate potential can be easily made independent of the source potential without increasing the element area, and the substrate potential can be controlled on a circuit.

At the same time, by arranging the P ⁺ region 102 for substrate contact between the N ⁺ source regions 101 and 101 in the transistor structure shown in FIG. 22 at another position, the area of the element itself is reduced. ing.

As described above, the conventional LDMO
Although the S substrate potential contact was common to the source contact, in the present embodiment, the substrate contact cell B is provided independently to separate the substrate potential from the source potential. Thus, the substrate potential can be controlled independently. That is, the body contact region 14 (see FIG. 7) is provided outside the cell without providing a body contact region for obtaining a substrate potential in the source contact hole 8 in FIG. Is provided, a desired substrate potential can be obtained while reducing the element area. Further, an electrode 15 different from the source electrode 7 is extended from the body contact region 14 provided outside the source cell, and a substrate potential control circuit 40 for controlling the substrate potential is connected to the electrode 15. This will increase versatility. Further, the substrate potential control circuit 40
Applies a voltage that makes the potential difference between the gate electrode 5 and the substrate constant when the transistor is turned on and off, whereby the switching characteristics can be improved.

In other words, the substrate potential control circuit 40 as a drive circuit for the power MOS transistor has a gate electrode 5
A voltage for applying a voltage to make the potential difference between the substrate and the substrate constant by turning on and off the transistor is applied. For this purpose, a substrate potential is provided in the source contact hole 8 and the inside of the source cell at the periphery thereof. The body contact region 14 may be provided outside the source cell without providing the body contact region, and an electrode 15 different from the source electrode 7 may be extended from the body contact region 14.

Hereinafter, an application example will be described. The circuit configuration shown in FIG. 10 may be used in addition to the circuit configuration shown in FIG.
In FIG. 10, the threshold voltage Vt can be controlled by the circuit 50 by utilizing the fact that the threshold voltage Vt increases due to the substrate effect when a reverse bias is applied to the substrate. For details, when the transistor is off (gate voltage = 0 volt)
, A reverse bias (for example, several volts) is applied to the substrate to increase the threshold voltage Vt. Further, when the transistor is turned on (for example, Vg = 5 volts), the substrate potential is set to 0 volts to lower the threshold voltage Vt. As described above, the substrate bias circuit 50 as the substrate potential control circuit applies a reverse bias to the substrate when the transistor is turned off, thereby optimizing the threshold voltage Vt.

In other words, the substrate potential control circuit 50 as a drive circuit for the power MOS transistor applies a reverse bias to the substrate when the transistor is turned off. For this purpose, the substrate potential control circuit 50 has a structure in the source contact hole 8 and its peripheral portion. A body contact region for providing a substrate potential is not provided inside a certain source cell, and a body contact region is provided outside the source cell.
What is necessary is just to extend the electrode 15 different from this.

As another configuration example, the substrate contact cell B is provided in the source cell row in FIG. 2, but the substrate contact cell B is not provided in the source cell row as shown in FIG. Substrate contact cell B may be provided only at the end of the source cell row, and the substrate potential may be obtained only at the end of the source cell column.

Alternatively, as shown in the plan view of FIG. 12 and FIG. 13 which is a cross section taken along line X--X of FIG. The substrate potential may be taken in the section. Specifically, a P-well region 61 and an N-well region 62 are formed from the upper surface of the substrate 60 by double diffusion, and a P-region 63,
An N ⁺ source region 64 and a P ⁺ region 65 are formed. In FIG. 13, a channel region is constituted by the P region 63 and the P ⁺ region 65, and a gate electrode 67 is arranged on at least a part of the regions 63 and 65 via a gate insulating film 66. The N ⁺ source region 64 is a contact hole 68
Is in contact with the source electrode 69. Further, an N region 70 and an N ⁺ region 71 are formed in the surface portion of the N well region 62. N ⁺ region 71 is in contact with drain electrode 72. A P region 73 and a P ⁺ region 74 are formed in the outer periphery of the source / drain cell group. The P-type body contact regions 73 and 74 are in contact with a substrate potential exclusive electrode 76 through a contact hole 75.

In the resurf type LDMOS,
Since the substrate contact cells (P regions 73 and 74) are connected through the P well region 61, either a mesh type or a stripe type can be easily applied.

Further, as shown in FIGS.
You may apply to OSFET. FIG. 14 is a plan view,
FIG. 15 is an AA cross section of FIG. When the source portions are arranged in stripes in the VDMOS, the substrate potential can be independently obtained in the same manner. For details, see FIG.
In this case, an N ⁺ type silicon substrate 80 serving as a drain region
The upper N ^- type silicon layer 81 is epitaxially grown. That is, the N ⁻ type silicon layer 81 is formed on the N ⁺ type silicon substrate 80 and has a lower concentration than the N ⁺ type silicon substrate 80. The gate oxide film 8 is formed on the surface of the N ⁻ type silicon layer 81.
2, a polysilicon gate electrode 83 is arranged. A channel P well region 84 is formed in the surface layer of the N ⁻ type silicon layer 81 at the end of the polysilicon gate electrode 83, and an N ⁺ source region 85 is formed in the surface layer inside the channel P well region 84. Are formed. As described above, the polysilicon gate electrode 83 is arranged on at least a part of the channel P well region 84 in the N ⁻ type silicon layer 81 via the gate oxide film 82. Further, outside the source cell, a deep N ⁺ region 86 reaching the N ⁺ type silicon substrate 80 from the surface layer portion of the N ⁻ type silicon layer 81 is formed, and the deep N ⁺ region 86 is connected to a substrate potential through a contact hole (not shown). It is in contact with a dedicated electrode (not shown).

Further, even when the substrate portion of the other MOS structure has a common potential in a plurality of source cells, the substrate potential can be independently obtained by the same means. Specifically, I
When the emitter section is arranged in a stripe shape in the GBT, or when the base section (channel region) is common in the trench IGBT, the substrate potential can be independently taken in the same manner. When applied to an IGBT, the source electrode (source region) in FIG. 6 becomes an emitter electrode (emitter region), and the drain electrode becomes a collector electrode.

Also, a stripe type (conventional L)
In the case of DMOS / VDMOS, the substrate potential may be divided into a plurality. More specifically, as shown in FIG.
Substrate potential wirings 22a, 22b, and 22c are formed, and each of the substrate potential wirings 22a, 22b, and 22c is connected to each of the substrate contact cells B in the m (two in FIG. 16) source cell rows. 17, the divided substrate potential wirings 22a, 22b, and 22c are connected to a substrate bias circuit 90, and a potential is independently applied to each of the wirings to independently apply a transistor cell. On
Turn off. That is, as shown in the equivalent circuit of FIG. 18, the plurality of transistor cells Tr10, Tr11, Tr12 are selectively turned on / off.

For example, with the gate voltage at 5 volts, the substrate potential of the transistor cells Tr10 and Tr11 is turned off by setting the substrate potential to several volts, and the substrate potential of the transistor cell Tr12 is turned on at 0 volts. Thereby, a predetermined amount of current can flow through the transistor cell Tr12.

As described above, a plurality of body contact regions 14 are provided in the transistor formation region, and a substrate bias circuit 90 as a substrate potential control circuit is provided with a transistor cell Tr1 corresponding to each body contact region 14.
By independently controlling ON / OFF of 0, Tr11 and Tr12, the output current of the entire device can be controlled.

In other words, the substrate potential control circuit 90 as a drive circuit for the power MOS transistor controls the substrate potential of each transistor cell independently, and controls each transistor cell independently on / off. As a structure for this purpose, a body contact region 14 for forming a transistor is formed outside the source cell without providing a body contact region for obtaining a substrate potential in the source contact hole 8 and inside the source cell as a peripheral portion thereof. A plurality of transistors may be provided in the region to form a transistor cell corresponding to each body contact region 14, and an electrode 15 different from the source electrode may be extended from each body contact region 14.

Although the case of the N-channel LDMOS has been described, a P-channel LDMOS may be used. In FIG. 8, the substrate potential is applied independently. However, as shown in FIG. 19 instead of FIG. 8, the source area and the substrate potential may be made common to reduce only the element area.

[Brief description of the drawings]

FIG. 1 is a plan view of a power MOS transistor according to an embodiment.

FIG. 2 is a plan view of the outermost layer of the semiconductor substrate.

FIG. 3 is a plan view showing a gate wiring on a cell.

FIG. 4 is a plan view showing a source second-layer wiring and a drain second-layer wiring on a cell.

FIG. 5 is a plan view showing substrate potential wiring.

FIG. 6 is a longitudinal sectional view taken along the line UU in FIG. 1;

FIG. 7 is a vertical sectional view taken along line VV in FIG. 1;

FIG. 8 is a longitudinal sectional view taken along line WW of FIG. 1;

FIG. 9 is a circuit configuration diagram in an embodiment.

FIG. 10 is a circuit configuration diagram in another example.

FIG. 11 is a plan view of a power MOS transistor in another example.

FIG. 12 is a plan view of a power MOS transistor in another example.

FIG. 13 is a longitudinal sectional view taken along line XX of FIG. 12;

FIG. 14 is a plan view of a power MOS transistor in another example.

FIG. 15 is a longitudinal sectional view taken along line AA of FIG. 14;

FIG. 16 is a plan view of a power MOS transistor in another example.

FIG. 17 is a circuit configuration diagram in another example.

FIG. 18 is an equivalent circuit diagram in another example.

FIG. 19 is a longitudinal sectional view in another example.

FIG. 20 is a plan view for explaining a conventional technique.

FIG. 21 is a longitudinal sectional view for explaining a conventional technique.

FIG. 22 is a longitudinal sectional view for explaining a conventional technique.

[Explanation of symbols]

1 ... N-type silicon substrate, 2 ... Channel P-well layer, 3 ...
N ⁺ source region, 4 gate oxide film, 5 polysilicon gate electrode, 6 silicon oxide film, 7 source electrode (aluminum layer), 8 contact hole, 9 N-well layer, 1
0 ... N ⁺ region, 11 ... Drain electrode (aluminum layer), 12
... contact hole, 13 ... LOCOS oxide film, 14 ...
P ⁺ body contact region, 15: substrate potential dedicated electrode (aluminum layer), 16: contact hole, 17: gate wiring, 18: source second layer wiring, 19: drain second layer wiring, 20: via hole, 21: via hole , 22: substrate potential wiring, 40: substrate potential control circuit, 50: substrate bias circuit, 90: substrate bias circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F048 AA01 AC06 BA01 BB05 BC06 BC07 BF16 BF17 5F140 AA00 AB01 AC09 AC21 AC23 AC24 BA01 BB13 BD19 BF01 BF04 BF44 BF53 BH02 BH03 BH30 BH43 BJ01 BJ05 CA06

Claims (6)

[Claims] A second conductive type channel region formed on a surface portion of a first conductive type semiconductor region on a semiconductor substrate; and a second conductive type channel region formed on a surface layer portion of the channel region. A gate insulating film (4) for the source or emitter region (3) of the first conductivity type and at least a part of the channel region (2) on the surface side of the semiconductor region (1) of the first conductivity type. Gate electrode (5) arranged via
A source or emitter electrode (7) disposed on the surface side of the first conductivity type semiconductor region (1) through a contact hole (8) for each cell so as to be in contact with the source or emitter region (3); In the power MOS transistor having the above structure, a body contact region for obtaining a substrate potential is not provided in the source or emitter contact hole (8) and in a source or emitter cell at a peripheral portion thereof. In the body contact region (1
4) A power MOS transistor comprising: 2. An electrode (15) different from a source or emitter electrode (7) extending from a body contact region (14) provided outside the source or emitter cell. 3. The power MOS transistor according to claim 1. 3. An electrode (1) extending from a body contact region (14) provided outside said source or emitter cell.
5) a substrate potential control circuit (40, 5) for controlling the substrate potential;
3. The power MOS transistor according to claim 2, wherein (0, 90) is connected. 4. The substrate potential control circuit according to claim 3, wherein said substrate potential control circuit applies a voltage for keeping a potential difference between said gate electrode and said substrate constant by turning on / off said transistor. Power MOS transistor. 5. The power MOS transistor according to claim 3, wherein the substrate potential control circuit (50) applies a reverse bias to the substrate when the transistor is off. 6. A plurality of body contact regions (14) are provided in a transistor formation region, and said substrate potential control circuit (90) is provided in each body contact region (1).
4. The power MOS transistor according to claim 3, wherein the on / off control of the transistor cell corresponding to 4) is performed independently.