JP3537431B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a MISFE formed on a semiconductor layer on an insulating substrate.
T, so-called SOI-MISFET (Silicon on insul
ator-Metal InsulatorSemiconductor Field Effect Tra
nsistor).

[0002]

2. Description of the Related Art An SOI-MISFET, that is, a MISFE formed on a semiconductor layer formed on an insulating substrate.
T is a MISFET formed on a bulk semiconductor substrate
For example, since it is possible to reduce the junction capacitance between the source / drain region and the substrate, it is expected as a low power consumption and high speed device.

In particular, a so-called fully-depleted SOI-MISFET in which the thickness of an SOI layer is equal to or less than the thickness of a depletion layer in a channel region during operation is a so-called portion in which the SOI layer is larger than the thickness of a depletion layer in the channel region during operation. Depleted SOI
-Unfavorable phenomena such as kink characteristics and current overshoot effect, which are problems in MISFETs, can be eliminated or suppressed.

Further, fully depleted SOI-MISFET
Is to suppress short channel effect, improve punch-through withstand voltage,
Numerous benefits are obtained, such as improved sub-threshold coefficients and increased channel mobility.

[0005]

FIG. 21 shows MISFET transistors Q _n1 and Q _n2 formed on an SOI substrate.
1 is a cross-sectional view of a conventional semiconductor device in which is formed in a gate array structure. An n-type gate serving as a back gate electrode is provided in the support substrate 5 facing the SOI layer region where the gate array is formed.
A gate region 1 is formed. As an example of a method of forming the back gate region 1, p
An n-type silicon region is formed by ion-implanting an n-type impurity such as phosphorus, arsenic, or antimony into the support substrate 5 made of type silicon. By forming the voltage node 18 to the back gate region 1, it becomes possible to apply a voltage to the back gate region . Therefore, according to the structure of FIG. 21, it is possible to apply a back gate voltage equal to the MISFET transistors _Qn1 and _Qn2 .

However, the back gate region 1 shown in FIG.
In the structure described above, there is a problem that the parasitic capacitance CD with the drain electrode 15 is large. Further, independent back gate voltages cannot be applied to the MISFET transistors Q _n1 and Q _n2 . Therefore, it is impossible to individually control the back gate voltage of the transistor.

Next, a description will be given of a problem that occurs in a circuit in the semiconductor device shown in FIG. FIG. 22 is a circuit diagram showing a NAND circuit. In FIG. 22, Q _n1 , Q
_n2 is an n-type MISFET, and Q _p1 and Q _p2 are p-type MISFETs. A common back gate electrode is provided for each of Q _n1 , Q _n2 and Q _p1 , Q _p2 , and an n-type MISFET, a p-type MISF
The back gate voltages VB1 and VB2 can be applied to each of the ETs.

[0008] In this circuit _{configuration,} the source electrode of _{Q n2 are} connected in series to the drain electrode of _{Q n1. Therefore,} in a state where the input voltage of _{Q n1} and _{Q n2} is conductive for _VDD, the voltage of the source electrode of _{Q n2} is for series resistance of _{Q n1,} raised for example by Vs. On the other hand, Q
The voltage of the source electrode of _n1 is 0 V because it is grounded. If the source voltage of Q _n2 rises than the source voltage of _{Q n1.}

[0009] _Therefore, the gate voltage input to the _{Q n2} is Vgs2 = (VDD-Vs) becomes _smaller than Vgs1 = VDD the gate voltage of _{Q n1.} Also, Q _n2
Similarly, the back gate voltage of VBS2 = (VB2-V
_s), and the back-gate voltage of _{Q n1} VBS1 = V
It becomes smaller than B1.

For this reason, even if this circuit is formed of transistors having the same threshold value for Q _n1 and Q _n2 , the same current driving capability or the same threshold value cannot be obtained.
Therefore, there arises a problem that the delay times of Q _n1 and Q _n2 are different, which is a problem in circuit timing design.

The present invention is directed to a semiconductor device using a SOI-MISFET having a back gate electrode which solves such a problem, and particularly to an SOI-MISFE in a gate array structure.
A semiconductor device according to T is provided.

[0012]

According to one embodiment of the present invention, an insulating film, a first impurity region of a first conductivity type formed on the insulating film, and a region adjacent to the first impurity region are provided. A first channel region of the second conductivity type formed, a second impurity region of the first conductivity type formed adjacent to the first channel region, and a second impurity region of the second conductivity type. A second channel region of the second conductivity type formed; a third impurity region of the first conductivity type formed adjacent to the second channel region; and a second impurity region formed on the first channel region. A first gate insulating film formed on the second channel region; a second gate insulating film formed on the second channel region; a first gate electrode formed on the first gate insulating film; A second gate electrode formed on the first gate insulating film, the first impurity region, and the third gate electrode. Characterized in that it comprises at least one and the fourth impurity region of the first or second high impurity concentration than the channel region second conductivity type between the insulating film of the impurity regions.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of the semiconductor device according to the first embodiment, FIG. 2 is a sectional view, FIG. 3 is a plan view, and FIG. 4 is a circuit diagram. 1 and 2 show cross-sectional structures along AA 'and BB' in FIG. 3, respectively. FIG. 4 shows a circuit diagram including a NAND circuit. FIG. 2 shows a contact electrode (17) to a gate formed on an extension of the BB 'section on the A side,
A contact electrode (18) to the back gate is not included in the cross section, but is illustrated for explanation.

Next, reference numerals used in this embodiment will be described. 1 is an n-type back gate region, 2 is a p-type back gate region
A gate region, 3 an insulating film on the gate side wall, 4 a channel region, 5 a support substrate, 6 a buried insulating film in the SOI, 9
Is a gate insulating film, 10 is a gate electrode, 11 is a source / drain region, 12 is an interlayer insulating film, 13 is an element isolation insulating film, 14 is a contact, 15 is a source / drain region shared by transistors connected in series, 16 , 16 ′ are contacts for the SOI Si film, 16 ″ is a contact for the gate electrode 10, 17 is an electrode for the SOI Si film, and 18 is an electrode for the support substrate 5.

Hereinafter, a specific configuration example will be described. Here, the configuration of the n-type MISFET will be described. For example, P, As, and Sb are 10 ¹⁵ to 10 ¹⁸ cm.
^A buried insulating film 6 made of, for example, a silicon oxide film or a silicon nitride film is formed to a thickness of 10 to 1000 nm on a support substrate 5 made of an n-type semiconductor doped with, for example, Si or SiGe. On the buried insulating film 6, for example, boron or indium is 10 ¹⁵
P-type silicon or p-type S doped with 〜１０10 ¹⁸ cm ^-3
An SOI substrate is formed from a semiconductor layer made of iGe and having a thickness of 1 to 300 nm. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film,
Tantalum oxide film, made of titanium oxide, or strontium titanium oxide film, a gate insulation thickness 1~200nm film 9, and, for example, phosphorus or boron 10
Polycrystalline silicon film doped with ¹⁹ cm ⁻³ or more or T
The gate electrode 10 is formed by depositing iN, TaN, W, and Al in a thickness of 10 to 300 nm. Gate electrode 10
Are formed with a width of, for example, 0.01 to 1 μm.
Then, for example, P, As, or Sb is added to the semiconductor layer on which the channel region 4 is formed at 10 ¹⁶ to 10 ²¹ cm ^−3.
Source / drain regions 11, 1 of the added n-type region
1 ′ and 15 are formed on both sides of the gate, and these gate electrode 10, channel region 4 and source / drain region 1 are formed.
The n-type MISFET transistors _Qn1 and _Qn2 are formed by ₁ , 11 'and 15 . In order to improve the electrical isolation between the gate electrode 10 and the source / drain regions 11, 11 'and 15 , an insulating film 3 made of, for example, a silicon oxide film or a nitride film is formed on the steep side surface of the gate region.
Are formed with a side thickness of 5 to 200 nm.

The drain region of Q _n1 and the source region of Q _n2 are formed of the same n-type impurity region 15 , and have a so-called gate array structure in which two transistors are connected in series.

In the support substrate 5, for example, B or In
The ¹⁰ 16 ^~10 18 ^{cm -3} the added p-type back gate
A second region 2 is formed. This p-type back gate region 2 is in contact with the buried insulating film 6. And p-type back game
In the region opposed to the channel region of the _{Q n1, Q n2} in preparative region 2, for example, ¹⁰ 16 to 10 P, As or Sb
Back gate made of n-type impurity doped with ²¹ cm ^-3
Regions 1, 1 'are formed. This back gate region 1,
1 'is formed in contact with the buried insulating film 6, and
The potential of the channel regions 4 and 4 'of the I layer can be changed by adjusting the potential of the back gate region . Then, the voltage node 18 of FIG. 2 is formed in the back gate regions 1 and 1 ', and a voltage can be applied. Further, the back gate regions 1 and 1 ′ are each surrounded by the p-type back gate region 2 and do not come into contact with the n-type support substrate 5. Therefore, by applying a reverse bias between the p-type back gate region 2 and the back gate region 1 and between the p-type back gate region 2 and the back gate region 1 ′, the state is electrically separated. I have. Therefore, different voltages can be applied to the back gate region 1 and the back gate region 1 '.

Furthermore, p-type back gate region 2, the pn junction formed between the n-type support substrate 5, by applying a reverse bias between them, the supporting substrate 5 and p-type bar
Electrical isolation from the gate region 2 can be performed. Thereby, the voltage of the p-type back gate region 2 can be set independently of the support substrate 5, and the support substrate 5 can be set such that the capacitance between the n-type back gate region 1 and the p-type back gate region 2 is reduced. And the voltage can be set independently. Therefore, in the present embodiment, the n-type back gate region
It is important that the forward bias condition is not applied between the region 1 or 1 'and the p-type back gate region 2. However, even if these back gate voltages are positively or negatively biased with respect to the source voltage, the p-type The voltage of the back gate region 2
Was more negative than the voltage of the back gate bets regions 1 and 1 ', and further, be adjusted to be more negative than 0V, it is possible to avoid a forward bias condition the potential of the substrate 5 while maintaining a 0V. Therefore, the capacitive coupling between the back gate and the substrate is weakened, so that a voltage change due to the capacitive coupling between the back gates and a latch-up effect due to minority carrier injection can be reduced. Further, since there is no need to bias the supporting substrate 5 having a large capacitance between the substrate and the package, power consumption of the substrate bias circuit can be suppressed.

According to the configuration of the semiconductor structure of the present embodiment,
In a semiconductor device having a gate array structure, a back gate region 1 is provided on a support substrate 5 facing a channel region 4 of each transistor, and independent back gate voltages VB1 and VB2 can be applied to each. Therefore, the threshold value of each transistor can be controlled by the back gate voltage.
Further, the back gate region is formed in the support substrate region facing the channel region, and the source / drain regions 11, 1
1 ′ and 15 , the source / drain regions 11, 1
1 ', p-type back having a conductivity type opposite to the direction of the conductivity type of the 15
A gate region 2 is formed. Source and drain regions 11, 11 ', by applying a potential to 15, p-type back
Gate region 2 and n-type source / drain regions 11, 1
Since the conductivity is different between 1 ′ and 15 , a depletion layer is formed in the back gate region 2 where the concentration of the p-type impurity is low. Therefore, the parasitic capacitance between the source / drain region 11 and the back gate can be reduced as compared with the structure using the back gate electrode shown in FIG. Also,
Since the parasitic capacitance can be reduced, the impedance of the signal transmitted from the drain electrode to the support substrate 5 and the back gate regions 1, 1 'can be reduced, and the crosstalk between devices can be further reduced.

Next, an example will be described in which the problem on the circuit is solved by back gate control in the semiconductor device of this embodiment. FIG. 4 shows a circuit diagram composed of a so-called NAND circuit, and two p-type MISFETs connected in parallel.
It is composed of transistors Q _p1 and Q _p2 and two n-type MISFET transistors Q _n1 and Q _n2 connected in series. The above-mentioned back gate electrode is formed in the n-type MISFETs Q _n1 and Q _n2 ,
Back gate voltages of VB1 and VB2 can be applied to _n1 and _Qn2 , respectively.

[0021] In this circuit _{configuration,} the source voltage of _{Q n2,} in a state _{where Q n1} and _{Q n2} is conductive for the series resistance of _{Q n1,} rises from 0V only Vs. On the other hand, Q
The source voltage of _n1 is grounded and 0V. _{Therefore, the} source voltage of _{Q n2 is} larger than that of the _{Q n1.}

[0022] Thus, for example, in the circuit configuration of FIG. 4 _{Q n1,} equal backgate voltage _{Q n2} (VB1 = V
Upon application of the voltage source _B2), the back gate potential measured from the source potential applied to each transistor Q _{n1, Q n2 is, Q n1} is an VB1 (= VB2),
Q _n2 is _{(VB2-Vs), and the} back gate voltage of _{Q n2} is smaller than that of _{Q n1.}

Incidentally, fully depleted SOI-MISFE
The following formula holds for the threshold value of T when the region of the channel region in contact with the buried oxide film of the SOI layer (hereinafter referred to as a back surface) is in a depleted state.

Vth1, depl2 = Vth1, acc2-CSiCox2
(VG2-VG2, acc) / {Cox1 (CSi + Cox2)}
(1) Here, VG2, acc <VG2 <VG2, inv In the equation (1), Vth1 and acc2 indicate threshold values of the transistor when the back surface is in the accumulation state, and CSi, C
ox1 and Cox2 are the capacitances of the SOI layer, the gate insulating film and the buried insulating film, respectively, VG2 is the back gate voltage, and Vx
G2, acc and VG2, inv indicate the back gate voltage when the back surface is in the accumulation and inversion state.

FIG. 7 is a graph showing the dependence of the threshold value on the back gate voltage in a fully depleted MISFET. The threshold value of the fully depleted MISFET is adjusted by applying a back gate voltage to the back surface of the SOI layer.
Can be changed in a range from the accumulation to the inversion state.

Therefore, in the circuit configuration of FIG. 4, Q _n1 ,
Q _n2 is composed of transistors having the same threshold value,
Then, the back gate voltages (VB1 = V
B2) when the input from the voltage _source, effective back gate voltage of _{Q n2} is the potential difference between the source voltage Vs and the back gate voltage, that is VG2 = (VB1-Vs) becomes, Q
The back gate voltage of _n1 becomes VB1. Therefore Q
_n2 threshold CSiCox2Vs than the threshold value of _{Q n1}
/ {Cox1 (CSi + Cox2) } only increases, the transistor operation is different that problems with _{Q n1} and _{Q n2.}

In the structure of this embodiment, the back gate voltage can be independently applied to each transistor. Therefore, to solve the Kakaru problem with the structure of this embodiment, i.e. by controlling the back gate voltage of Q _n1, Q _n2, realizing the equalizing the threshold of Q _n1 and Q _n2.

More specifically, the back gate voltage VB2 applied to Q _n2 is compared with the back gate voltage VB1 applied to Q _n1 by the following equation: VB2 = VB1 + Vs (2) where VG2, acc <VB2 <VG2, inv. I do. Thus the potential difference between the source electrode and the back gate electrode of _{Q n2} is equal to that of _{Q n1,} threshold resulting _{Q n1} and _{Q n2} are equal. That is, Q
The transistor Q _n2 by adding _n2 source voltage increment of the back gate voltage can achieve the same threshold as Q _n1 also. Therefore, the change amount of the threshold value with respect to the SOI film thickness change can be set to the same condition for Q _n1 and Q _n2 , and a transistor integrated circuit with more uniform characteristics can be realized. Figure 8 is for a change in the source voltage Vs of Q _n2, the back gate voltage VB to achieve the threshold no variation
2 is a graph showing the relationship of FIG. For source voltage Vs,
By inputting VB2 corresponding to the straight line of the graph to the back gate, the threshold values of _Qn1 and _Qn2 can be made equal. The threshold of the _{Q n2} by entering a larger VB2 from this straight line to the back gate _{Q n1}
Smaller than that of.

Further, by providing a control circuit for controlling the back gate voltage as shown in FIG. 5, it is possible to suppress a threshold variation due to a change in the source voltage of _Qn2 . Figure 5 is a circuit diagram of a semiconductor device having a control circuit 8 of the voltage supply to set the back gate voltage controlled by feedback source voltage Vs of Q _n2, is applied.
The control circuit 8 monitors the source voltage Vs of _{Q n2,} by setting the back gate voltage VB2 satisfying the formula (2) is input to the back gate electrode of the transistor _{Q n2.} By the back gate voltage controlled by the control circuit, it is possible to suppress the threshold variations of Q _n2.

[0030] By the _way, since the source voltage of _{Q n2} becomes the _Vs, the effective gate voltage is input to the _{Q n2} also (V
_DD-Vs), and the smaller than VDD of the gate voltage of _{Q n1.} Thus, lower the current driving capability of the Q _n2, a problem that the gate delay time becomes large.

The drain current Idsat in the saturation region
Is represented by the following equation. Idsat = 1/2 · W / L · μeff · Cox · (Vgs−
Vth) 1.3-2 (3) In equation (3), W is the gate width, L is the gate length, μef
f is the mobility, Cox is the capacitance of the gate insulating film, Vgs is the gate voltage with reference to the source potential, and Vth is the threshold value of the transistor.

As can be seen from equation (3), the current driving capability of the transistor is represented by a function of the gate voltage. As the gate voltage increases, the current driving capability also increases. Therefore, in the circuit configuration of FIG. 22, when Q _n1 and Q _n2 perform the same threshold value operation, the gate voltage of Q _n2 decreases by Vs as described above, so that the current driving capability is lower than that of Q _n1. .

The signal propagation delay time τ is expressed by the following equation. τ = Cload · VDD / Idsat (4) In the equation (4), Cload represents a load capacity.

The propagation delay time τ is the saturation drain current Ids
It is inversely proportional to at, and the delay time increases as the saturation drain current decreases. The circuit arrangement of FIG. 22 Thus, when a 4 in VB1 = VB2 In other _{words, Q n2
Qn2} is smaller than that of _Qn1.
Is longer than that of _Qn1 . The occurrence of a difference in transition time due to such a difference in input terminals poses a problem in circuit timing design.

Hereinafter, a back gate control method for solving such a problem in the present embodiment will be described. As mentioned above,
The current driving capability is proportional to (Vgs-Vth) 1.3 to 2. Therefore, Q _n1 and Q _n2 in the circuit configuration of FIG.
When equal threshold (Vth1 = _Vth2), the current driving capability of the _{Q n2} because the gate voltage is smaller by Vs compared to the _{Q n1,} the current driving capability of the _{Q n2} is smaller than that of _{Q n1.}

Therefore, in order to make the current driving capabilities of Q _n1 and Q _n2 equal, the reduction is realized by compensating the decrease Vs of the gate voltage input to Q _n2 by a threshold value. That is, by the back gate voltage control _the threshold V of _{Q n2}
By reducing th2 to Vth2 '= Vth1-Vs, Q
_A current driving capability equal to _n1 is realized. This Vth2 '=
The back gate voltage VB2 'required to realize Vth1-Vs satisfies the following equation.

VB2 ′ (Vs) = Vs / γ + VB1 (5) In the equation (5), γ is γ = CSiCox2 / ｛Cox1 (CSi
+ Cox2)}, which can be approximated as tox1 / tox2. tox1 and tox2 represent the thicknesses of the gate insulating film and the buried insulating film. Therefore, the back gate voltage VB2 'for keeping the current driving capability constant is determined by the source voltage Vs and the thickness ratio of the gate insulating film and the buried insulating film.

[0038] Figure _9, the source voltage Vs of _{Q n2,} is a graph showing the relationship between the back gate voltage VB2 'required to equalize the current driving capability and _{Q n1.} Q
_In a circuit in which _n1 and _Qn2 are formed with equal threshold values, it is possible to make the current driving capabilities substantially equal by applying the back gate voltage VB2 'satisfying the expression (5). In other words, in FIG. 9, by applying the back gate voltage VB2 ′ corresponding to the straight line of the graph to Vs, it is possible to make the current driving capabilities substantially equal. However, the transistor control is performed in a range where the back surface is in a depletion state, that is, the back gate voltage VB
2 ′ is possible within the range of VG2, acc <VB2 ′ <VG2, inv.

The above-described control circuit 8 shown in FIG. 5 can be used as a control circuit for keeping the current driving capability constant. That feedback of the source voltage Vs of _{Q n2,} the back gate voltage VB satisfying 9
2 'is set and applied to _Qn2 . Thus, it is possible to form a semiconductor device in which the current driving capability does not change with respect to the variation in Vs.

Here, it is understood that VB2 <VB1 should be satisfied in order to improve the effect of either of the equations (2) and (5), that is, to improve the current driving capability of _Qn2 as compared with the conventional example. Here, in order to control the VB2, as shown in FIG. 4 _{(b), Q n1} and _{Q n2} and equivalent transistors Q
_The back gate voltage VB2 may be obtained from a source voltage obtained by a dummy circuit formed by connecting _n1 ′ and _Qn2 ′ in series, or VB2 may be commonly applied to a plurality of NAND circuits.

According to the structure of this embodiment, the following effects can be obtained. (1) As shown in FIG. 1, in this embodiment, a back gate region is provided in a support substrate facing a channel region of each transistor in a semiconductor device having a gate array structure. Is such that a depletion layer is formed on the supporting substrate. Therefore, since the parasitic capacitance between the source / drain region and the supporting substrate is reduced, for example, the operation power consumption is reduced and the S factor is reduced. Then, the signal propagation delay time can be reduced. Thus, it greatly contributes to low power consumption and high speed.

[0042] (2) back gate region provided in each transistor, the back gate territory of adjacent transistors
Since the transistor is formed so as to be electrically separated from the region, the transistor can be controlled by individually applying a back gate voltage.

Further, according to the control example of the present embodiment, the following effects can be obtained. (3) As shown in FIG. 8, by controlling the back gate voltage of Q _n2, suppressing threshold increase due to the source voltage increase of Q _n2, it can be equal to the threshold value of Q _n1 is there. Therefore, for example, the delay time in the triode operation can be shortened, and the margin of the operation time of the logic circuit in the triode operation is reduced, and high-speed operation is realized. In addition, as shown in the circuit configuration of FIG. 5, by controlling the back gate voltage by feeding back the change in the source voltage of _Qn2, a semiconductor device with small threshold fluctuation can be realized.

[0044] (4) As shown in FIG. 9, by controlling the back gate voltage of Q _n2, it is possible to suppress the current driving capability decreases due to source voltage drop of Q _n2. Therefore, a signal propagation delay time in a logic circuit is suppressed, and high-speed operation is realized. In addition, the difference between the maximum value and the minimum value of the switching time can be suppressed, and the operation speed of the circuit can be made more uniform.

FIG. 10 is a plan view showing the structure of the second embodiment of the present invention. 10 is a top view in which the wiring layer and the contact layer are omitted, and FIGS. 11, 12 and 13 are cross-sectional views taken along arrows AA ', BB', and CC 'in FIG. 10, respectively. The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted. This embodiment differs from the first embodiment in the method of controlling the threshold value and the back gate structure of the transistors connected in series, and discloses a so-called gate array configuration method. In this embodiment, the supporting substrate 5 is formed in p-type semiconductor, n-type back gate region 1 and the n-type back gate in the supporting substrate 5
DOO region 1 'is formed. These are the p-type back gate regions 2 ′ of FIG. 10 electrically connected to the support substrate 5.
Are electrically separated from each other.

As shown in FIG. 11, a p-type back gate region 2 is formed so as to be surrounded by an n-type back gate region 1 . The p-type back gate region 2 is electrically separated from the support substrate 5 by the n-type back gate region 1 . These p-type back gate region 2 and n-type back
The gate region 1 functions as a back gate electrode of the p-type MISFET.

P-type acting as back gate electrode
For one semiconductor island region opposing the back gate region 2 and the n-type back gate region 1 via the insulating film 6,
A plurality of p-type MISFETs are formed. In this embodiment, an example is shown in which two semiconductor island regions are formed, but more semiconductor island regions may be formed. here,
Adjacent p-type MIS formed in one semiconductor island region
The FET has a source / drain region 15 made of a p-type semiconductor shared by transistors connected in series. Furthermore, a p-type source / drain is sandwiched between the gate electrodes 10.
The region 1 made of a p-type semiconductor is opposed to the rain region 15.
1 is formed. These regions 15 and 11
Forms a source region and a drain region or a drain region and a source region of a p-type MISFET. Further, a region 4 made of an n-type or doped with a p-type impurity of 10 ¹⁶ cm ⁻³ or less is formed with the gate electrode 10 and the gate insulating film 9 interposed therebetween, and serves as a channel region of the p-type MISFET.

As shown in FIG. 12, a p-type back gate region 2 'is formed so as to be surrounded by an n-type back gate region 1'. This p-type back gate region 2 ′ is electrically separated from the support substrate 5 by an n-type back gate region 1 ′. The p-type back gate region 2 ′ and the n-type back gate region 1 ′ function as a back gate electrode of the n-type MISFET.

P-type acting as back gate electrode
Back gate region 2 'and n-type back gate region 1 '
A plurality of n-type MISFETs are formed for one semiconductor island region opposed to the semiconductor device via the insulating film 6. In this embodiment, an example is shown in which two semiconductor island regions are formed, but more semiconductor island regions may be formed. Here, the adjacent n-type M formed in one island-shaped semiconductor region
The ISFET has a source / drain region 15 'made of an n-type semiconductor shared by transistors connected in series. Further, the n-type region 1 is sandwiched between the gate electrodes 10 '.
A region 11 'made of an n-type semiconductor is formed to face 5'. These regions 15 'and 11'
A source region and a drain region or a drain region and a source region of the n-type MISFET are formed. Further, a region 4 'made of p-type or doped with n-type impurity of 10 ¹⁶ cm ^-3 or less is formed with the gate electrode 10' and the gate insulating film 9 interposed therebetween, and serves as a channel region of the n-type MISFET.

Here, as shown in FIG. 10, the n-type MISFE
It is desirable that the T and p-type MISFETs be formed in an array in order to form a multi-stage logic circuit by connecting metal wires. In this case, by forming the structure of FIG. 10 in an array on the left and right sides of the paper, the semiconductor regions 1, 1 ′, and 2 ′ serving as back gates are connected continuously,
Even if the voltage application terminal is not formed on the back gate of each array, for example, by forming the voltage application terminal at the end of the array, a voltage can be applied to the back gates of all the arrays formed continuously.

Here, the gate electrodes 10 and 10 ′
Semiconductors having different conductivity types may be used to control the threshold. Specifically, the gate electrode ^10, a polysilicon electrode added with 10 19 ^{cm -3} or more B, as the gate electrode 10 ^{', 10} 19 cm
A polysilicon electrode to which P or As is added to ⁻³ or more may be used.

On the side surfaces of the gate electrodes 10 and 10 ', an insulating film 3 is formed from, for example, a silicon oxide film or a silicon nitride film. This is because the gate electrode 10 and the source / drain region 15 or the source / drain region 1
This is for maintaining good electrical insulation from the first. Further, an element isolation insulating film 13 made of, for example, a silicon oxide film is formed between the semiconductor island regions. further,
An interlayer insulating film 12 made of, for example, a silicon oxide film is formed above the MISFET.

The feature of this embodiment is that, in a p-type MISFET as shown in FIG. 11, a conductive substrate opposite to a source / drain region 11 is provided on a support substrate 5 opposed to a channel region 4 via an insulating film 6. N-type back gate region having
1 is formed, and a p-type back gate region 2 having the same conductivity as the source / drain region 11 is formed on the support substrate 5 opposed to the source / drain region 15 shared by the adjacent transistors via the insulating film 6. That is.

In addition, as shown in FIG.
In the SFET, a source / drain region 11 ′ is provided on a support substrate 5 opposed to a channel region 4 ′ via an insulating film 6.
Back gate region 2 ′ having the opposite conductivity to that of source / drain region 15 ′ shared by adjacent transistors and facing support substrate 5 via insulating film 6.
In addition, an n-type back gate region 1 'having the same conductivity as the source / drain region 11' is formed.

With such a structure, two transistors whose thresholds change depending on the direction of the current flowing through the source / drain can be formed in series. First, with reference to FIG. 14, it will be described that the threshold value is changed by the present back gate structure. FIG. 14 (a)
FIG. 9 is a cross-sectional view corresponding to a state where one n-type MISFET of the present embodiment is extracted, and shows a source / drain region 11 ′.
a and 11'b are electrodes 17a and 17
b is connected. Further, a p-type back gate region 2 ′ is formed below 11 ′ a and below the channel region via an insulating film 6. Here, the p-type back gate region 2 ′ is formed through the high-concentration p-type back gate region 2 ″.
It is electrically connected to the electrode 18. Although not shown, the electrode 18 is connected to a voltage source, and the p-type back gate region 2 ′ is controlled to have a constant voltage. Further, under 11′b, an n-type back-gate
Port region 1 'is formed. Here, the n-type back gate
Over preparative region 1 'through the high-concentration n-type back gate region 1 ", the electrode 18' in is electrically connected to the. Figure, although not shown, the electrode 18 'is connected to the voltage source, the n-type bar
The lock gate region 1 'is controlled to have a constant voltage. Here, in order to suppress the power consumption of the voltage source, a p-type
The, n-type bar so that a large leakage current flows in the back gate region 2 'and the n-type back gate region 1'
Or positively biased to than 'a p-type back gate region 2' Kkugeto region 1, it is necessary to bias below the forward voltage. Under such conditions, the potential DD ′ on the back gate surface is as shown in FIG. 14B, and the conduction band Ec and the valence band Ev are the depletion layers including the boundary between the region 1 ′ and the region 2 ′. By n-type back
The gate region 1 'has a structure that bends downward. Therefore,
D side, that is, the channel 4 ′ close to 11′a and the insulating film 6
And the interface between the channel 4 ′ and the insulating film 6 on the D ′ side, that is, near 11′b, is in an inversion state of the p-type layer. . Therefore, as shown in FIG. 14C, when the electrode 17b is used as the drain electrode and the electrode 17a is used as the source electrode, the pentode threshold value is such that the maximum point of the potential of the channel portion that determines the threshold value is the channel potential. Since it is formed on the 17a side rather than the 17b side in 4 ′, it is difficult to form an inversion layer and a high threshold value is obtained. On the other hand, as shown in FIG. 14D, when the electrode 17a is used as the drain electrode and the electrode 17b is used as the source electrode, the pentode threshold value is such that the maximum point of the potential of the channel portion which determines the threshold value is the channel potential. Since it is formed on the 17b side rather than the 17a side in 4 ′, an inversion layer is easily formed and the threshold value is low. As described above, depending on the direction of the source / drain electrodes, a difference is formed in the threshold value even under the same voltage applied to the back gate. In particular, when the transistor is a fully depleted transistor, the depletion layer extending from the back gate portion reaches the channel portion, so that the threshold value greatly changes depending on the back gate potential, which is a desirable mode for this embodiment.

Hereinafter, a direction is indicated by a black circle on the side of the source electrode under the condition that the threshold value becomes high when the source electrode is used as the source electrode. As apparent from the above description, in order to form a difference in the threshold value, the potential of the back gate electrode facing the channel 4 'only needs to be asymmetric with respect to the source / drain. Therefore, the boundary between the p-type back gate region 2 ′ and the n-type back gate region 1 ′ may be formed not at the position facing the source region but at the position facing the channel 4 ′. p
Similarly, in the type MISFET, the boundary between the p-type back gate region 2 and the n-type back gate region 1 is formed not at the position facing the source region but at the position facing the channel 4. Is also good.

Next, FIG. 15 shows an example of a logic circuit using the transistor of this embodiment. FIG. 15A is a circuit diagram for a static 2-input NAND, and FIG.
Is a circuit diagram for a static two-input NOR. FIG. 16A shows a layout of a wiring layer for a static two-input NAND corresponding to FIG. 15A, and uses the transistor arrangement of FIG. FIG. 16B shows a layout of a wiring layer for a static 2-input NOR corresponding to FIG. 16A, and uses the transistor arrangement of FIG.

First, in FIGS. 15 (a) and 16 (a), Q _n1 and Q _n2 are n-type MISFETs having different thresholds depending on the above-described current directions, and Q _p1 and Q n
_p2 is a p-type MISFET having a different threshold value depending on the current direction described above. These are desirably formed facing each other as shown in FIG. 16A in order to suppress wiring delay. In FIG. 16A, 17, 17 'and 1
7 ″ indicates a metal wiring made of W, Cu or Al;
17 'is connected to VDD, 17 "is connected to 0 V. 26 is a p-type source / drain electrode 1
Shown are contact electrodes for 1 or 15, 2
6 'is an n-type source / drain electrode 11' or
26 ″ indicates a contact electrode for the drain electrode 15 ′, and 26 ″ indicates the gate electrode 10 or 10 ′, 10 ″
2 shows a contact electrode with respect to FIG.

Here, the drain electrode on the side other than the common electrode of _Qn2 is connected to the output node. Also, Q _n2
Is connected to the drain electrode of _Qn1 . Further, the source electrode of Q _n1 is G
ND and a voltage node 17 ″ having 0V, which is indicated in FIG. _The gate electrode of _{Q n1 is} connected to the gate electrode of _{Q p1,} and has a first voltage input terminal (IN1). _Furthermore, the gate electrode of _{Q n2 is} connected to the gate electrode of _{Q n1,} and has a second voltage input terminal (IN2). Further, the source electrodes of Q _p1 and Q _n1 are both connected to a voltage node having a voltage of, for example, VDD, and the drain electrode is connected to an output node. In other words, this configuration is a two-input NAN
4 shows a logic circuit of D, IN1, IN2, OUT
Operate to have voltages corresponding to two logical values of approximately 0 V and approximately VDD. In FIG. 15, voltages V1, V2, V3, and V4 are applied to regions 2 ', 1', 2, and 1, respectively, as a back gate. Here, in order to prevent a current from flowing due to a forward bias between the back gates,
Assuming that the t-in voltage is Vi, V3> V4-Vi, and V1
> V2-Vi.

[0060] In this circuit _{configuration,} the source electrode of _{Q n2,} for the series resistance of _{Q n1,} in a state where the input voltage of _{Q n1} and _{Q n2} is conductive for VDD, Vs than 0V
Just rise. On the other _hand, the source electrode of _{Q n1} is connected to _0V, and towards the _{Q n2} than _{Q n1} source voltage increases. Therefore, when a transistor having a threshold value equal to Q _n1 and Q _n2 is used, the current driving capability of Q _n2 becomes
Compared to the current driving capability of the Q _n1, the gate voltage (VDD-
Vs). Therefore, Q
The transition time when _n2 is turned on is longer than the transition time when _Qn1 is turned on, and there is a difference in the transition time due to the difference between the input terminals, which is a problem in circuit timing design.

[0061] Here, as described in the first embodiment, in order to suppress the current driving capability decreases for _{Q n1} of _{Q n2} by the source voltage _rises, the threshold Vth2 of _{Q n2 Q n1} Works A condition for lowering the threshold value than Vth1 is required. In particular, if Vth2 = Vth1−Vs,
The current driving capabilities of _Qn2 and _Qn1 are almost equal, and the delay times can be almost equal regardless of the input terminal.

Here, in this embodiment, the current direction of _{Qn2 is} the direction in which the threshold value becomes lower, and the current direction of _{Qn1 is} the direction in which the threshold value becomes higher.
This condition can be satisfied by adjusting the back gate voltages V1 and V2 of the FET. At this time, current flows in both p-type MISFETs Q _p1 and Q _p2 in the direction of increasing the threshold. Therefore, two p-type MIS
The transition time when the FET is turned on is substantially equal, and the difference in transition time caused by the difference between the input terminals does not change even when the back gate voltages V1 and V2 are changed. That is,
To reduce the difference according to the input terminal of the delay time of the 2-input NAND circuit, a transition time during Q _n1 on may be controlled V1 and V2 so as to be substantially equal to the transition time when Q _n2 on.

On the other hand, in FIGS. 15 (b) and 16 (b), Q _n1 and Q _n2 are n-type MISFETs having different threshold values depending on the above-mentioned current directions, and Q _p1 and Q n
_p2 is a p-type MISFET having a different threshold value depending on the current direction described above. These are desirably formed facing each other as shown in FIG. 16B in order to suppress wiring delay. In FIG. 16B, 17, 17 'and 1
7 ″ indicates a metal wiring made of W, Cu or Al;
17 'is connected to VDD, 17 "is connected to the drain electrode output node of _{.Q p2} connected to 0V. _The source electrode of _{Q p2 is} connected to the drain electrode of _{Q p1} Further, a source electrode of Q _p1 is connected to a voltage node having, for example, VDD, and a gate electrode of Q _p1 is connected to a gate electrode of Q _n1 to form a first voltage input terminal ( has become IN1). _further, the gate electrode of _{Q p2 is} connected to the gate electrode of _{Q n2,} and has a second voltage input terminal (IN2). _further, the source electrode of _{Q n1} and _{Q n2} are ,
Both are connected to, for example, a voltage node 17 ″ having a voltage of 0V, and the drain electrode is connected to the output node. That is, this configuration shows a two-input NOR logic circuit, and IN1, IN2, and OUT Operate to have voltages corresponding to two logical values of approximately 0 V and approximately VDD.

In FIG. 15, V1, V2, V1, V2, V1
3 and V4 are applied. Here, in order to prevent a current from flowing due to a forward bias between the back gates, the build-in voltage between the back gates is set to Vi,
It is necessary to satisfy the conditions of 3> V4-Vi and V1> V2-Vi.

[0065] In this circuit _{configuration,} the source electrode of _{Q p2,} due to the series resistance of _{Q p1,} in a state where the input voltage of _{Q p1} and _{Q p2} is conductive for 0V, than VDD Vs
Just drop. On the other _hand, the source electrode of _{Q p1} is connected to _0V, and towards the _{Q p2} source voltage becomes lower than _{Q p1.} Therefore, when a transistor having a threshold value equal to Q _p1 and Q _p2 is used, the current driving capability of Q _p2 becomes
Compared to the current driving capability of the Q _p1, a gate voltage equivalent to that raised by Vs, it decreases. Thus, towards the transition time when turning on the Q _p2 is longer than the transition time when turning on the Q _p1, differences in the transition time by the difference between the input terminals is generated, the timing design issues of the circuit.

[0066] Here, as described in the first embodiment, in order to suppress the reduction current driving capability for _{Q p1} of _{Q p2} by the source voltage _rises, the threshold Vth3 of _{Q p2 Q p1} Works A condition for lowering the threshold value than Vth4 is required. In particular, if approximately Vth4 = Vth3−Vs, Q
The current driving capabilities of _p2 and _Qp1 are almost equal, and the delay time can be almost equal regardless of the input terminal.

Here, in the present embodiment, the current direction of Q _{p2 is} a direction in which the threshold value is lower, and the current direction of Q _{p1 is} a direction in which the threshold value is higher.
This condition can be satisfied by adjusting the back gate voltages V3 and V4 of the FET. At this time, a current flows in both the n-type MISFETs Q _n1 and Q _n2 in the direction of increasing the threshold value. Therefore, two n-type MIS
The transition times for turning on the FETs are substantially equal, and the difference between the transition times caused by the difference between the input terminals does not change even when the back gate voltages V3 and V4 are changed. That is, in order to reduce the difference by the input terminal of the delay time of the two-input NOR circuit, the transition time when Q _p1 on may be controlled V3 and V4 so as to be substantially equal to the transition time when Q _p2 on .

As described above, even if the NAND circuit and the NOR circuit of the present embodiment are formed on the same substrate and share the back gate terminal, the transition time difference caused by the difference between the input terminals is independently V1 and V2. , V3 and V4, respectively, can be minimized. Therefore, in a logic circuit in which these are combined with a one-input inverter, it is possible to minimize a delay time shift caused by a difference between input terminals.

FIG. 17B is a circuit diagram for a clocked inverter, and FIG. 17A shows a layout of a wiring layer for the clocked inverter corresponding to FIG. The arrangement is used. In FIG. 17 (a) and FIG. 17 (b),
Q _n1 and Q _n2 are n-type MISFETs with different thresholds depending on the current direction described above, and Q _p1 and Q _p2 are p-type MISFEs with different thresholds depending on the current direction described above.
T. These are desirably formed facing each other as shown in FIG. 17A in order to suppress wiring delay. In FIG. 17 (a), 17, 17 'and 17 "
W, represents a metal wiring made of Cu or Al, 17 'are connected to VDD, 17 "is connected to 0V. Connections The drain electrode of the side not common electrode of Q _n2 is an output node is. also, the common electrode to become the source electrode of Q _n2 is connected to the drain electrode of Q _n1. in addition, the source electrode of Q _n1, the voltage having a 0V that is denoted in GND and 15 Node 1
7 ''. Further, the drain electrode of the non-common electrode of _Qp2 is connected to the output node.
Further, a source electrode serving as a common electrode of _Qp2 is connected to a drain electrode of _Qp1 . Further, the source electrode of Q _p1 is connected to the voltage node 17 '' having a 0V that is denoted in GND and 15.

[0070] _The gate electrode of _{Q n2 is} connected to the gate electrode of _{Q p2,} the inverter voltage input terminal (I
N). _Furthermore, the gate electrode of _{Q n1} is connected to the clock input _fai, the gate electrode of _{Q p1} is
It is connected to the inverted input / fai of the clock input.
That is, in the present configuration, an inverted output of IN is obtained when fai is VDD and / fai is 0 V, and / fai is obtained when fai is 0 V.
Shows a logic circuit of a clocked inverter whose output becomes a high impedance state when VDD is VDD, and IN, fa
i, / fai, and OUT operate to have voltages corresponding to two logical values of approximately 0 V and approximately VDD.
Also, in FIG. 15, V1, V2, V3, and V3 are provided in regions 2 ', 1', 2, 1 as back gates, respectively.
The voltage V4 is applied. Here, in order to prevent forward current due to forward bias between back gates,
Assuming that the built-in voltage between the back gates is Vi, V3> V
It is necessary to satisfy the conditions of 4-Vi and V1> V2-Vi.

[0071] In this circuit _{configuration,} the source electrode of _{Q n2,} for the series resistance of _{Q n1,} in a state where the input voltage of _{Q n1} and _{Q n2} is conductive for VDD, Vs than 0V
Just rise. Therefore, the current driving capability of _Qn2 is Q
_As compared with the case where the source electrode of _n2 is grounded to 0 V, the gate voltage is reduced by (VDD-Vs). On the other _hand, the source electrode of _{Q p2,} due to the series resistance of _{Q p1,} the input voltage of _{Q p1} and _{Q p2} is in a state where the conduction 0V, thereby lowering only the Vs than VDD. _Therefore, the current driving capability of the _{Q p2 is} the source electrode of _{Q p2} V
This corresponds to increasing the gate voltage by Vs, which is lower than the case of connecting to DD. Therefore, to connect the source electrode of Q _p2 to VDD, a source electrode of Q _n2 compared to conventional inverters connected to 0V, and the delay time of the inverter is increased even with the same transistor size. Further, the current drivability reduction in Q _p2 and Q _n2, compared with the input clock signal fai and / fai, since the delay time of the output signal to the signal applied to IN is increased, a problem timing design of the circuit .

[0072] Here, as described in the first embodiment, in order to suppress the reduction current driving capability for _{Q n1} of _{Q n2} by the source voltage _rises, the threshold Vth2 of _{Q n2 Q n1} Works A condition for lowering the threshold value than Vth1 is required. In particular, if approximately Vth2 = Vth1−Vs, Q
The current driving capabilities of _n2 and _Qn1 are almost equal, and the delay time can be almost equal regardless of the input terminal. Furthermore, in order to suppress the reduction current driving capability for _{Q p1} of _{Q p2} by the source voltage _rises, the threshold Vth3 of _{Q p2} Q
A condition for lowering the threshold value than the threshold value Vth4 of _p1 is required.
In particular, when almost Vth4 = _{Vth3-Vs, Q p2} and Q
The current driving capability of _p1 is substantially equal, and the delay time can be substantially equal regardless of the input terminal.

Here, in the present embodiment, the current direction of _{Qn2 is} the direction in which the threshold value decreases, and the current direction of _{Qn1 is} the direction in which the threshold value increases.
This condition can be satisfied by adjusting the back gate voltages V1 and V2 of the FET. Further, in the present embodiment, the current direction of _{Qp2 is} a direction in which the threshold value is lower, and the current direction of _{Qp1 is} a direction in which the threshold value is higher. Therefore, the back gate voltage V3 of the p-type MISFET is By adjusting V4 and V4, this condition can be satisfied.

As described above, the output delay time of the input IN can be made equal to or shorter than the output delay time for the clock inputs fai and / fai, and an inverter that switches faster can be formed.

The feature of suppressing the deterioration of the current driving capability when cascade-connected transistors whose thresholds differ depending on the direction of the current flow is not limited to the above-described static logic circuit, but also to a further multi-input circuit. The present invention can be used for a logic circuit or a dynamic circuit, and a difference in delay time depending on an input terminal can be reduced.

According to the present embodiment, the following effects can be obtained. (1) The regions 1, 1 ′, 2 and 2 ′ that function as back gate electrodes of the transistor are electrically isolated from the supporting substrate 5. Therefore, the region to which the back gate is applied can be made smaller than the entire chip, and
The capacity of 1 ', 2, 2' can be reduced. Therefore, a power supply having a smaller capacity can be used as the substrate bias power supply connected to the regions 1, 1 ', 2, 2', and the circuit area and power consumption of the substrate bias power supply can be reduced. Further, the influence of noise through the substrate is reduced, and a low-noise circuit can be stably realized.

[0077] (2) the voltage of the n-type back gate region 1 which acts as a back gate electrode 11 and p-type back gate
By controlling the voltage of the gate region 2 , the p-type MI
It is possible to control the threshold value of the SFET and the difference in threshold value depending on the current direction of the source and the drain.
In addition, an n-type bus acting as a back gate electrode in FIG.
By controlling the voltages of the gate region 1 ′ and the p-type back gate region 2 ′, the difference between the threshold value of the n-type MISFET and the threshold value depending on the current direction of the source and drain can be independently controlled. . Therefore, for example, after the semiconductor element is formed up to the wiring layer and enters an actual operation state, the difference in threshold value can be controlled by external voltage input, and the delay time of the logic circuit can be optimized.

(3) The difference between the maximum delay and the minimum delay of the NOR or NAND circuit and the clocked inverter logic circuit can be reduced without changing the wiring layout pattern. Therefore, the time required for the synchronization margin of the logic circuit can be reduced, and the logic circuit can be operated at higher speed.

(4) As the back gate of the MISFET, a back gate of the same conductivity type as the source / drain region is formed on the entire surface under the source / drain layer and the channel layer. The capacity of one of the source / drain layers on which the conductive back gate is formed with respect to the back gate can be reduced. In particular, when a back gate of the opposite conductivity type is formed in the drain region, when the drain voltage is high, the drain capacitance with respect to the back gate is reduced because the back gate region is depleted, and the logic connected to the drain is reduced. The load capacity of the circuit output can be reduced and high-speed operation can be performed.

On the other hand, the depletion of the back gate region facing the channel is smaller than when the back gate of the conductivity type opposite to that of the source / drain region is formed on the entire lower surface of the source / drain layer and the channel layer. , The channel potential can be kept more constant, and the threshold value is less likely to decrease even if the gate length is shortened.

(5) As shown by regions 1 and 2 ′ in FIG. 10, a semiconductor region having one conductivity type serving as a back gate can be shared by two transistors. Therefore, even if the gate length is smaller than the length of the source / drain regions along the gate length, the length in the channel direction of the regions 1 'and 2' can be ensured to be wider than the gate length. For this reason, the design rule of the back gate can be relaxed from the design rule for the gate,
The back gate can be formed using an inexpensive lithography apparatus with lower resolution. In addition, since the widths of the regions 1 ′ and 2 ′ can be made large, the back gate resistance can be kept small, and a stable back gate voltage can be applied even if the channel width increases.

FIG. 18 is a structural plan view of the third embodiment of the present invention. FIG. 18 is a top view in which the wiring layer and the contact layer are omitted, and FIGS. 19A and 19B are cross-sectional views taken along arrows AA ′ and BB ′ in FIG. 10, respectively.
The same parts as those in the first and second embodiments are denoted by the same reference numerals, and detailed description is omitted. This embodiment is partially different from the second embodiment in the method of controlling the threshold value of the transistors connected in series and the element isolation structure. In FIG. 19, two p-type MISFETs are connected in series, and two n-type MISFETs are connected in series.
One is formed.

An adjacent p-type MISFET formed in one semiconductor island region shown in FIG. 19A has a source / drain region 15 made of a p-type semiconductor shared by transistors connected in series. Further, the gate electrode 10 is opposed to the source / drain region 15 with the gate electrode 10 interposed therebetween.
A region 11 made of a mold semiconductor is formed. these,
The region 15 and the region 11 form a source region and a drain region or a drain region and a source region of the p-type MISFET. Further, the region 4 formed by adding an n-type impurity under the gate electrode 10 and the gate insulating film 9 is
It is a channel region of the type MISFET. here,
An undepleted region under this channel region (FIG. 19)
(Dotted line portion) is referred to as a body region 20.

Further, below or on the side surface of the junction between the p-type source / drain region 11 and the n-type body region 20, for example, P and A are formed as 10 ¹⁸ to 10 ²⁰ cm ⁻³ n-type impurities.
A region 19 to which s or Sb is added is formed,
The tunnel leakage current of the pn junction is set to increase. Here, the region 19 is the source / drain region 11
And is not formed in the shared source / drain region 15 or the dummy source / drain region 11 ′ ″. Further, a dummy gate electrode 10 ″ for performing field shield isolation is formed on the side surface of the region 11 on the side where the gate electrode 10 is not formed. The dummy gate has a dummy source / drain region 11 ′ ″ having the same conductivity type as the dummy 11 in a portion in contact with the element isolation 13 made of, for example, an oxide film.
A gate for electrically separating from the source / drain region 11 and a dummy source / drain region 11 '''
This is for reducing the influence of side leakage along the element isolation 13 between the substrate and the substrate 4, and is normally connected to VDD and is in a cutoff state. The dummy gate 10 ″ in the center of the figure is for separating the source / drain region 11 of the two p-type MISFETs from the field shield, and is normally connected to VDD and is in a cutoff state.
In FIG. 19, four p-type MISFETs used as circuit elements, ie, Q
_Although an example in which _p1 , _Qp2 , _Qp3 , and _Qp4 are formed is shown, more may be formed by extending a semiconductor island region in the AA 'direction and forming a field shield gate. Absent.

On the other hand, an adjacent n-type MISFET formed in one semiconductor island region shown in FIG. 19B has a source / drain region 15 ′ made of an n-type semiconductor shared by transistors connected in series. ing. Further, the n-type source / drain region 1 is sandwiched between the gate electrodes 10 '.
A source / drain region 11 'made of an n-type semiconductor is formed opposite to 5'. These regions 15 'and 11' form a source region and a drain region or a drain region and a source region of the n-type MISFET. Further, a region 4 ′ formed by adding a p-type impurity below the gate electrode 10 ′ and the gate insulating film 9 is an n-type
This is the channel region of the SFET.

Further, n-type source / drain regions 11 '
Below or on the side of the junction between
For example, a region 19 ′ to which B or In is added as an n-type impurity of 10 ¹⁸ to 10 ²⁰ cm ⁻³ is formed, and the region 19 ′ is set so as to increase the tunnel leakage current of the pn junction. Here, the region 19 'is selectively formed in contact with the source / drain region 11', and is not formed in the shared source / drain region 15 'or the dummy source / drain region 11 "". Further, a dummy gate electrode 10 ″ for performing field shield isolation is provided on the side surface on the side where the gate electrode 10 ′ of 11 ′ is not formed.
Is formed. This dummy gate electrode 10 ″
For example, a dummy source having the same conductivity type as the dummy 11 'in a portion in contact with the side surface of the element isolation 13 made of an oxide film.
The drain region 11 ″ ″ is connected to the source / drain region 1
A gate for electrically separating the substrate from the dummy source / drain region 11 '''' and the substrate 4 'to reduce the influence of side leakage along the element isolation 13; Usually, it is connected to 0V and is in a cutoff state. The dummy gate electrode 10 ″ at the center of the figure is
This is for separating the source / drain regions 11 of the two n-type MISFETs from each other in a field shield, and is normally connected to 0 V and is in a cutoff state. In FIG.
For one semiconductor island region, four n-type MISFETs used as circuit elements, ie, Q _n1 ,
Although an example in which Q _n2 , Q _n3 , and Q _n4 are formed is shown,
The semiconductor island region may be extended in the BB 'direction and the field shield gate may be formed to form a larger number.

Here, as shown in FIG. 18, the n-type MISFE
It is desirable that the T and p-type MISFETs be formed in an array in order to form a multi-stage logic circuit by connecting metal wires. Here, the gate electrodes 10 and 10 ′
May be semiconductors having different conductivity types to control the threshold. Specifically, the gate electrode 10 is a polysilicon electrode to which B is added at 10 ¹⁹ cm ⁻³ or more, and the gate electrode 10 ′ is 10 ¹⁹ c
^Any polysilicon electrode to which P or As is added to m ⁻³ or more may be used.

On the side surfaces of the gate electrodes 10 and 10 ′, an insulating film 3 is formed from, for example, a silicon oxide film or a silicon nitride film. This is because the gate electrode 10 and the source / drain region 15 or the source / drain region 1
This is for maintaining good electrical insulation from the first. Further, an element isolation insulating film 13 made of, for example, a silicon oxide film is formed between the semiconductor island regions. further,
An interlayer insulating film 12 made of, for example, a silicon oxide film is formed above the MISFET.

The feature of this embodiment is that FIG.
2A, the same conductivity as that of the body region 20 is provided so as to be in contact with the lower portion or the side surface of the p-type source / drain region 11 opposed to the p-type source / drain region 15 shared by the adjacent transistors with the gate electrode 10 interposed therebetween. Has,
In addition, an n-type semiconductor region 19 having a high impurity concentration is formed, and the resistance of the body region 20 and the source / drain region 11 at the time of reverse bias is made smaller than the resistance of the body region 20 and the source / drain region 15. It is that you are.

Further, in FIG. 19B, the n-type source / drain regions 1 shared by adjacent transistors
P-type semiconductor region 1 having the same conductivity as body region 20 'so as to be in contact with the lower portion or side surface of n-type source / drain region 11' opposite to 5 'with gate electrode 10 interposed therebetween.
9 ′ is formed, and the resistance at the time of reverse bias between the body region 20 ′ and the source / drain region 11 ′ is reduced by the body region 2 ′.
This is to reduce the resistance between 0 ′ and the source / drain region 15 ′.

In this way, the current driving capability can be made different depending on the direction of the source / drain. To explain this, for example, FIG.
In n-type MISFET having marked _{Q n1} in, 11 'serves as the source region is grounded to 0V, 15' if becomes VDD becomes the drain electrode, region 11 'and the body region 2
Since the resistance between 0 ′ is lower than the resistance between region 15 ′ and body region 20 ′, the voltage of the body becomes close to 0V due to the resistance division. Conversely, when 15 'is grounded to 0V and becomes a source region, and 11' becomes VDD and becomes a drain electrode, the resistance between the region 11 'and the body region 20' is reduced by the resistance between the region 15 'and the body region 20'. , The voltage of the body becomes close to VDD due to the resistance division. Here, in the n-type MISFET, when the voltage of the body decreases, the threshold increases due to the substrate bias effect. Therefore, the threshold becomes lower when 15 ′ is the source region than when 15 ′ is the drain region. . In particular,
In the case where the transistor is a partially depleted transistor, an electrically neutral body region is formed, so that this embodiment is a desirable mode.

From the above, it is clear that a logic circuit similar to that described in the second embodiment can be formed by using a transistor whose threshold value changes depending on the direction of current flow. For example, FIG. 20B is a circuit diagram for a static two-input NAND, and FIG.
10B shows a layout of a wiring layer for a static two-input NAND corresponding to FIG. These use the transistor arrangement of FIG. VDD power supply line 17 'for field shield gate 10 "of p-type MISFET
Contact ″ with n-type MISFE
VDD for field shield gate 10 ″ of T
Except for the connection contact 26 '' with the power supply line 17 '',
The circuit and layout can be configured similarly to FIGS. 16A and 15A. Although not shown in FIG.
It is clear that other logic elements of the embodiment of the present invention can be formed in the same manner, and a two-input NOR and a clocked gate can be formed.

In this embodiment, the regions 19 and 19 '
For example Ar or N2, Ge, F2 to ¹⁰ 13 ^{to 10 16} c
The regions formed by m ⁻² implantation are defined as regions 11 and 11 ′.
In the depletion layer and the diffusion length of minority carriers from the body. Such ions form a defect at the junction between the source / drain layer and the body electrode, which is a generation center, and increase the reverse current, so that the same effect can be obtained.

In this embodiment, (3) of the second embodiment
In addition to the effects described above, the following effects can be obtained. (1) By adjusting the amount and position of the impurity added in 19, the difference in threshold value depending on the current direction of the source and drain of the p-type MISFET can be controlled. Further, by adjusting the amount and position of the impurity addition of 19 ′, the difference in threshold value depending on the current direction of the source and drain of the n-type MISFET can be controlled independently of the p-type MISFET.

(2) The region 11 or 11 'having poor junction characteristics becomes a drain only when transistors are formed in series, and usually, the region 15 or 1 having good junction characteristics is used.
The region 5 'can be used as a drain. Therefore, the drain withstand voltage can be improved as compared with the case where 19 ′ is formed in all the source / drain regions. Further, when a current flows through transistors connected in series, a voltage distribution is generated by a plurality of transistors, so that the voltage applied between the drain and the source of each transistor decreases. Therefore, in this case, the probability of generation of electron-hole pairs is reduced, and deterioration due to hot electrons is less likely to occur.

[0096]

As described above, according to the present invention, a back gate electrode is provided in a support substrate facing a channel region of each transistor in a semiconductor device having a gate array structure, and a position facing a drain is provided. , A depletion layer is formed on the supporting substrate. Therefore, the parasitic capacitance between the source / drain electrodes and the supporting substrate is reduced.

[Brief description of the drawings]

FIG. 1 shows an SOI-MI according to a first embodiment of the present invention.
FIG. 2 is a schematic sectional view of an SFET.

FIG. 2 is an SOI-MI according to the first embodiment of the present invention;
FIG. 2 is a schematic sectional view of an SFET.

FIG. 3 is an SOI-MI according to the first embodiment of the present invention;
FIG. 2 is a schematic plan view of an SFET.

FIG. 4 is an SOI-MI according to the first embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of an SFET.

FIG. 5 is an SOI-MI according to the first embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of an SFET.

FIG. 6 is an SOI-MI according to the first embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of an SFET.

FIG. 7 is a graph of the back gate voltage dependence of the threshold value according to the first embodiment of the present invention.

FIG. 8 is a graph of a back gate voltage for realizing no threshold change according to the first embodiment of the present invention.

FIG. 9 is a graph of a back gate voltage for realizing a constant current driving capability according to the first embodiment of the present invention.

FIG. 10 shows an SOI-M according to a second embodiment of the present invention.
FIG. 2 is a schematic plan view of an ISFET.

FIG. 11 shows an SOI-M according to a second embodiment of the present invention.
FIG. 2 is a schematic sectional view of an ISFET.

FIG. 12 shows an SOI-M according to a second embodiment of the present invention.
FIG. 2 is a schematic sectional view of an ISFET.

FIG. 13 shows an SOI-M according to a second embodiment of the present invention.
FIG. 2 is a schematic sectional view of an ISFET.

FIG. 14 is a diagram illustrating a change in a threshold value in a source / drain direction of a transistor according to a second embodiment of the present invention.

FIG. 15 shows an SOI-M according to the second embodiment of the present invention.
FIG. 2 is a schematic circuit diagram of an ISFET.

FIG. 16 shows an SOI-M according to the second embodiment of the present invention.
FIG. 2 is a schematic plan view of an ISFET.

FIG. 17 is an SOI-M according to the second embodiment of the present invention.
1 is a schematic plan view and a circuit diagram of an ISFET.

FIG. 18 is an SOI-M according to the third embodiment of the present invention.
FIG. 2 is a schematic plan view of an ISFET.

FIG. 19 is an SOI-M according to the third embodiment of the present invention.
FIG. 2 is a schematic sectional view of an ISFET.

FIG. 20 shows an SOI-M according to the third embodiment of the present invention.
1 is a schematic plan view and a circuit diagram of an ISFET.

FIG. 21 is a schematic sectional view of a conventional SOI-MISFET.

FIG. 22 is a schematic circuit diagram of a conventional SOI-MISFET.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 n-type back gate region 2 p-type back gate region 3 insulating film 4 channel region 5 support substrate 6 insulating film 7 voltage source 8 voltage supply control circuit 9 gate insulating film 10 gate electrode 11 source / drain region 12 interlayer insulating film 13 Device isolation insulating film 14 Contact 15 Source / source shared by transistors connected in series
Drain region 16 Contact 17 and 18 Electrode 19 P-type semiconductor region 20 Body region

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-51083 (JP, A) JP-A-6-291142 (JP, A) JP-A-2-54967 (JP, A) JP-A-7-510 94754 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 27/118 H01L 27/08 H01L 27/092

Claims (3)

(57) [Claims] An insulating film, a first conductive type first impurity region formed on the insulating film, and a second conductive type first impurity region formed adjacent to the first impurity region. A channel region; a second impurity region of a first conductivity type formed adjacent to the first channel region; and a second impurity region of a second conductivity type formed adjacent to the second impurity region. A channel region; a first conductivity type third impurity region formed adjacent to the second channel region; a first gate insulating film formed on the first channel region; A second gate insulating film formed on the second channel region; a first gate electrode formed on the first gate insulating film; and a second gate electrode formed on the second gate insulating film. a gate electrode of both said first impurity region and the third impurity regions
The semiconductor device characterized by comprising a fourth impurity region of the first through higher second conductivity type impurity concentration than the second channel region between said insulating film and people. 2. A third channel region of a second conductivity type formed adjacent to the first impurity region, and a fifth channel region of a first conductivity type formed adjacent to the second channel region. An impurity region, a third gate insulating film formed on the third channel region, a third gate electrode formed on the third gate insulating film, and an adjacent to the fifth impurity region 2. The semiconductor device according to claim 1, further comprising: an element isolation region formed by: 3. The non-depleted body region exists in the first and second channel regions, and the fourth impurity region is formed between the body region and the first and third impurity regions. 3. The semiconductor device according to claim 1, wherein the semiconductor device is formed below or on a side surface of the junction.