JPH04219019A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To avoid adverse effect on other elements on a same chip by arranging a collector, an emitter and a base electrode of a bipolar transistor(TR) being a component of an inverter circuit on one major plane. CONSTITUTION:Collectors, emitters and base electrodes of two bipolar TRs 47, 48 are all arranged onto one major plane. Since the collectors differ from the substrate, a collector current does not flow in the substrate and fluctuation of the substrate level is avoided thereby eliminating adverse effect such as saturation of the bipolar TRs or disabled high speed switching. Moreover, since all the electrodes are placed on the same major plane, the freedom of degree of wiring is increased and large scale circuit integration of the circuit is facilitated.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an inverter circuit.
In particular, it relates to the device structure of a high-speed, low-power semiconductor integrated circuit that combines field-effect transistors and bipolar transistors.

0002

2. Description of the Related Art An example of an inverter circuit that combines MOS transistors and bipolar transistors is described in Japanese Patent Laid-Open No. 148469/1983. This circuit is CM
This solves the problem of insufficient driving power in the OS circuit.

[0003] Also, IEEE Trans. ElectronDevi
ces, vol. ED-16, No. 11. Nov, 1
969, p945-952 Fig. It is described in 1.

0004

SUMMARY OF THE INVENTION In the conventional inverter circuit described above, complementary NPN and PNP bipolar transistors are used, and it is difficult to match their switching characteristics.

[0005] Furthermore, since PNP is used, there are the following problems. That is, in PNP, the carriers are holes, and due to problems with today's manufacturing technology, high-performance transistors equivalent to NPN cannot be manufactured. By the way, with today's process and device technology, it is easy to obtain NPN with an fT of several GHz, but the fT of PNP is several tens to several tens of GHz.
It is 0MHz. Therefore, in this circuit, the switching speed of the circuit is limited by the performance of the PNP, and it is difficult to increase the switching speed.

[0006] Furthermore, in the above conventional device structure, NPN
Since the collector of the bipolar transistor is formed of the substrate, the following problems occur.

That is, in such a structure, a collector current flows through the substrate, but since the substrate has a low impurity concentration, the collector resistance, Rc, becomes large. Therefore, during switching, the potential of the collector substrate decreases. Due to this fluctuation in substrate potential, other elements on the same chip are affected by various adverse effects such as Vth fluctuation and latch-up. Therefore, it is difficult to implement it into an LSI. Furthermore, the collector potential becomes lower than the base potential due to a decrease in the collector potential, which saturates the bipolar transistor, making high-speed switching impossible. Furthermore, since the electrodes are present on both surfaces of the substrate, it is not possible to have a sufficient degree of freedom in wiring, and the degree of freedom in LSI is small.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a semiconductor integrated circuit that is high speed, has low power consumption, and is suitable for LSI integration.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the present invention has a collector of one conductivity type, a base of the other conductivity type, and an emitter of one conductivity type, and the collector and emitter current paths are connected to a first conductivity type. A first bipolar transistor is connected between the potential level section and the output terminal, and has a collector of one conductivity type, a base of the other conductivity type, and an emitter of one conductivity type, and the collector-emitter current path is connected to the output terminal. a second bipolar transistor connected between the terminal and the second potential level section; and a second bipolar transistor connected between the first potential level section and the first potential level section in response to an input signal applied to the at least one input terminal. at least one other conductivity type field effect transistor forming a current path to the base of the bipolar transistor and from the output terminal to the base of the second bipolar transistor in response to the input signal applied to the input terminal; at least one first single conductivity field effect transistor forming a current path between the base of the first bipolar transistor and the second potential level in response to the input signal applied to the input terminal. at least one second one-conductivity type field effect transistor connected between the base of the second bipolar transistor and the second potential level section; a charge extraction element for extracting accumulated charges from the base of the first,
collector, emitter of the second bipolar transistor,
The base electrode is characterized in that it is on one major surface.

0010

According to a feature of the present invention, the collector, emitter, and base electrodes of the two bipolar transistors constituting the semiconductor integrated circuit are all located on one main surface. First, since the collector is not formed of a substrate, it does not have an adverse effect on other elements as described above. Furthermore, since all the electrodes are on the same main surface, the degree of freedom in wiring increases. These features allow the circuit to be easily integrated into an LSI.

According to another feature of the present invention, two bipolar transistors are configured vertically. This enables high performance of bipolar transistors and higher density of semiconductor integrated circuits.

According to yet another feature of the invention, the drain, source and gate electrodes of one and the other field effect transistor are located on the same major surface as the bipolar transistor. This further facilitates LSI implementation.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an inverter circuit diagram showing an embodiment of the present invention. In the figure, 43 is a PMOS which is a field effect transistor of the other conductivity type, 44, 45, 46 is a NMOS which is a field effect transistor of one conductivity type, 47, 48
are first and second NPN bipolar transistors. PMOS43 and NMOS44 constitute a CMOS inverter, each gate G is connected to the common input terminal 40, and each drain D is connected to the base B of the first NPN47.
It is also connected to the gate G of the NMOS 46. Sources S of the PMOS 43 and NMOS 44 are connected to the power supply terminal 42 which is a first potential and the ground potential GND which is a second potential, respectively. The drain D of the NMOS 45 is connected to the output terminal 41, the gate G is connected to the input terminal 40, and the source S
is connected to the drain D of the NMOS 46 and the base B of the second NPN 48. A source S of the NMOS 46 is connected to the ground potential GND. In addition, the collector C of the first NPN 47 is connected to the power supply 42, and the base B is connected to the PMOS 43 and NMOS.
44 common drain connection point, emitter E is NMOS4
5, the collector C of the second NPN 48, and the output terminal 41. The base B of the second NPN 48 is commonly connected to the source S of the NMOS 45 and the drain D of the NMOS 46, and the emitter E is connected to the ground potential GND. Further, CL is the load capacity.

Next, the operation of the inverter circuit of this embodiment will be explained. Now, when the input VI switches from a low level to a high level, the PMOS 43 is turned off, the NMOS 44 is turned on, and the base of the first NPN 47 is at a low level, so the NPN 47 and NMOS 46 are turned off. on the other hand,
Since the NMOS 45 is turned on, the second
A current path is formed to the base of the second NPN48.
PN48 turns on and output V0 switches from high level to low level.

Next, when the input VI switches from high level to low level, NMOS 45 and second NPN 48 are turned off. On the other hand, PMOS43 is turned on and NMOS
44 is turned off, the first NPN
A current path is formed to the base of the first NPN4.
7 base switches to high level, first NPN47
and NMOS46 turns on. Therefore, the output V0 switches from a low level to a high level. Here NMOS4
6 is important for high-speed switching. N.M.
The OS 46 acts as a dynamic discharge circuit. That is, when input VI switches from low level to high level, PMOS 43 is turned off and NMOS 44 is turned off.
is turned on, and the gate of the NMOS 46 is switched from high level to low level in response to the base signal of the first NPN 47, so that the NMOS 46 is turned off. Therefore, the second
Since there is no current path between the base B of the second NPN 48 and the ground potential GND, all current flowing from the output V0 through the NMOS 45 flows to the base B of the second NPN 48.
The second NPN 48 can be turned on quickly. next,
When the input VI switches from a high level to a low level, the gate G of the NMOS 46 switches from a low level to a high level in response to the base signal of the first NPN 47, so that the NMOS 46 is turned on. Therefore, the second N
The base B of the PN48 is grounded with low impedance to quickly discharge parasitic charges in the base region. Therefore, the second NPN 48 is quickly turned off, and all the current flowing from the second NPN 48 is transferred to the load C.
The charging current becomes L, and charging is performed at high speed.

FIG. 2 shows the input/output characteristics of the inverter circuit of this embodiment. Circuit logic threshold voltage VL
T is normally set to a value of 1/2 of the power supply voltage, but if VLT is to be changed depending on the application, VLT can be easily changed by selecting the size ratio of PMOS 43 and NMOS 44.

FIG. 3 shows the delay time characteristics of the CMOS inverter and the inverter circuit of this embodiment with respect to the load capacitance CL. In the figure, (A) shows the delay time characteristics of the CMOS inverter circuit, and (B) shows the delay time characteristics of the inverter of this embodiment. As is clear from the figure, the inverter circuit of this embodiment is slightly slower than the CMOS inverter below the minute load range C1, but is much faster in the high load range where high drive capability is required.

FIG. 4 shows a cross-sectional structure of a device for realizing the circuit of FIG. 1, and the same parts as in FIG. 4 are given the same numbers. In addition, to avoid complicating the drawing, the PMOS shown in Figure 1 is
43, NMOS 44, and NPN 47 are shown in FIG.

In FIG. 4, 70 is a P-type semiconductor substrate;
1 is a P-type isolation layer for isolating elements from each other. P
The MOS 43 uses an N-type epitaxial layer 73 as a substrate and a P
+ Diffusions 74 and 75 form drain and source regions. The substrate 73 of the PMOS 43 has an ohmic collector formed by an N+ diffusion 76 and is connected to the power supply 42 . M.O.S.
44, a well region 80 is formed by P-type diffusion on an N-type epitaxial layer, and a source 81 and a drain 82 are formed in the well region 80 by N+ diffusion. The substrate 80 of the NMOS 44 is in ohmic contact with the P+ diffusion 83 and connected to the ground potential. Note that 77 and 84 are gate electrodes of PMOS and NMOS, respectively, and are formed of polysilicon.

The NPN 47 is of vertical type, has an N-type epitaxial layer 90 as its collector, and is connected to the power source 42 through ohmic contact by N+ diffusion. The base is formed by a P type base diffusion 92, within which the emitter is formed by an N+ diffusion 93.

As is clear from the figure, the collector of the NPN 47 is located on the same principal plane as the base and emitter. Further, the sources and drain gates of the PMOS 43 and NMOS 44 are also located on the same main plane as described above. That is, according to the device structure of this embodiment, all the electrodes of the semiconductor element are located on the same main plane, which increases the degree of freedom in wiring and the degree of freedom in LSI integration.

In the figure, NBL indicates an N+ type heavily doped buried layer, which is mainly used to reduce the collector resistance of the NPN47.

[0023]

As is clear from the above description, according to the present invention, a semiconductor integrated circuit with high speed and low power consumption can be realized. Further, the device structure of the semiconductor integrated circuit of the present invention is as follows:
It is possible to realize LSI with a high degree of freedom, and the effect is remarkable when applied to memory LSI and logic LSI.

[Brief explanation of the drawing]

FIG. 1 is an inverter circuit diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing the transfer characteristics of the inverter circuit of FIG. 1;

FIG. 3 is a diagram showing delay time characteristics of the inverter circuit of FIG. 1;

FIG. 4 is a diagram showing a device cross-sectional structure of the inverter circuit of FIG. 1;

[Explanation of symbols]

43...PMOS, 44, 45, 46...NMOS, 47,
48...NPN.

Claims (5)

[Claims] 1. a first bipolar transistor having a collector of one conductivity type, a base of the other conductivity type, and an emitter of one conductivity type, the collector-emitter current path being connected between the first potential level section and the output terminal; , a second bipolar transistor having a collector of one conductivity type, a base of the other conductivity type, and an emitter of one conductivity type, the collector-emitter current path being connected between the output terminal and the second potential level section; a transistor, and in response to an input signal applied to at least one input terminal, from the first potential level portion to the first potential level portion.
at least one other conductivity type field effect transistor forming a current path to the base of the bipolar transistor; and in response to the input signal applied to the input terminal;
at least one first single conductivity type field effect transistor forming a current path from the output terminal to the base of the second bipolar transistor; at least one second one-conductivity type field effect transistor connected between the base of the first bipolar transistor and the second potential level; and the base of the second bipolar transistor and the second potential level section. and a charge extraction element for extracting accumulated charge from the base of the second bipolar transistor, wherein the collector, emitter, and base electrodes of the first and second bipolar transistors are disposed on one main surface. A semiconductor integrated circuit characterized by: 2. In claim 1, the above-mentioned first and second
A bipolar transistor is a semiconductor integrated circuit characterized by being vertical. 3. In claim 2, the above-mentioned first and second
A semiconductor integrated circuit characterized in that bipolar transistors are separated from each other and from a substrate. 4. In claim 2, the above-mentioned first and second
A semiconductor integrated circuit characterized in that the base region of the bipolar transistor is separated from the drain, source and channel regions of the one conductivity type field transistor and the other conductivity type field transistor. 5. 2. The semiconductor integrated circuit according to claim 1, wherein the sources, drains, and gates of the one conductivity type field transistor and the other conductivity type field transistor are located on the one main surface.