JPH0441505B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and more particularly to a structure that allows an integrated semiconductor device to be made faster and more highly integrated.

[Background of the invention]

CMOS (Complementary Metal Oxide Se−
The microconductor has excellent characteristics in terms of power consumption and noise tolerance, and is an LSI (Large Scale
It occupies an important position in the field of integration. However, CMOS LSI is single channel
Compared to nMOSLSI, it is difficult to increase the degree of integration because it is necessary to separate the n-channel MOS and p-channel MOS. Switching speed is also limited by the low channel mobility of pMOS.

Figure 1 shows a cross-sectional schematic diagram A and an equivalent circuit B of an inverter constructed using CMOS. Here, 1 is a semiconductor substrate, 2 is an n-well, 3 is a p-well, and 4 is a pMOS
The p-type impurity layer 5 becomes the source and drain of
n-type impurity layer that becomes the source and drain of nMOS,
6 is a conductive band layer serving as a gate of the MOS, and 7 is a gate oxide film. The nMOS and pMOS are separated from each other by a thick oxide film shown at 8. p-well 3
is at ground potential, and the voltage of the power supply 9 is applied to the n-well 2. 11 in FIG. 1B is a load capacity for examining the performance of the inverter.

Let's consider the switching characteristics of this inverter. The rise characteristics of the inverter output are pMOS1
2 is determined by the speed at which the load capacitance C _L is charged,
The output rise time constant τ _p can be expressed as follows.

τ _p = C _L / β _0p W/L (V _DD + V _Tp )...(1) β _0p = μ _p C _0x , where μ _p : hole mobility in the channel, W:
MOS gate width, L: MOS gate length, V _DD :
Voltage of power supply 9, V _Tp : Threshold voltage of pMOS, C _0x :
This is the gate oxide film thickness.

Here, C _L = 1pF, β _0p = 20μS/V, W/L =
20/3, V _DD = 5V, V _Tp = -0.5V, τ _p =
It becomes 1.67ns.

On the other hand, the output rise characteristic is determined by the speed at which the nMOS 13 discharges the load capacitance C _L , and the output fall time constant τ _o is as follows.

τ _o = C _L / β _0o W/L (V _DD + V _To )...(2) β _0o = μ _o C _0x , where μ _o : electron mobility in the channel, V _To
This is the threshold voltage of nMOS. β _0o = 40μS/V,
Assuming that V _To =0.5V and other constants as in the case of rising, τ _o =0.83ns.

In this way, when the W/L of pMOS and nMOS of an inverter configured with CMOS is made equal, the rise time constant becomes larger than the fall time constant due to the difference in mobility between holes and electrons. To improve the rise characteristics, increase the W/L of pMOS and increase τ _p
It is conceivable to make it smaller. However, since L cannot be made less than a certain value due to limitations in processing accuracy, it is necessary to increase W, which increases the dimensions of the element and expands the chip area. Increasing the element size to increase speed impedes higher integration of the element.

Therefore, there has been a desire for an element structure that can simultaneously achieve higher device integration and higher speed.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having an element structure capable of high speed and high integration.

[Summary of the invention]

FIG. 2A shows a cross-sectional view of the device structure according to the present invention. In the present invention, the thick oxide film 8 disposed in the region separating the pMOS and nMOS of the conventional example is made to have the same or similar thickness as the gate oxide film 7, and the conductive film 10 is formed in this region, It is characterized by having the element shown in FIG. 2B. In other words, 10 is the gate, n-well 2 is the drain, and p-well 3 is the gate.
nMOS 14 whose source is the n-type impurity layer 5 inside
A pMOS 15 is formed in the same manner, with 10 as the gate, the p-well 3 as the drain, and the p-type impurity layer 4 in the n-well 2 as the source. The feature of this structure is that the area previously used for element isolation is used for the new element, so there is only a slight increase in the area associated with element formation, and in a CMOS structure, the p-well 3 is usually at the lowest potential Since the well 2 is connected to the highest potential, each MOS drain is fixed at each potential, and there is no need for wiring.

[Embodiments of the invention]

FIG. 3A is a schematic cross-sectional view of an inverter to which the present invention is applied. In this structure, the element of the present invention shown in FIG. 2 is formed in the separation region between the pMOS 12 and nMOS 13 of the conventional inverter shown in FIG. Source of inverter load pMOS12
Connect the drain of nMOS14 and the source of nMOS14 to the drain of pMOS12, and drive nMOS13.
The source of pMOS15 is connected to the drain of
The drain of pMOS15 is connected to the source of . If a terminal C is provided at the common gate of the nMOS 14 and pMOS 15, and a signal having the opposite phase to the input signal of the terminal A is applied to the terminal C, the circuit shown in FIG. 3 works as a high-speed inverter.

When the input of terminal A is low and the input of terminal C is high, nMOS13 and pMOS15 are turned off, and pMOS1
2 and nMOS14 are turned on, and the load capacitance C _L is charged. When the input of terminal A is high and the input of terminal B is low, nMOS13 and pMOS15 are turned on and pMOS
12 and nMOS14 are turned off, and the load capacitance C _L is discharged. In this way, nMOS14 and pMOS15 are respectively driven by the inverter load pMOS12.
Since it is turned on and off in synchronization with the nMOS 13, the load capacitance C _L is charged and discharged more quickly. Particularly during charging, since the nMOS 14 with a large β ₀ is turned on, a significant improvement in the output rise time constant can be expected compared to when charging with the pMOS 12 alone.

In addition, nMOS14 and pMOS15 are formed in an element isolation region where active elements could not be formed in the past, and the n-well, which is the drain of nMOS14, is fixed at the highest potential, and the p-well, which is the drain of pMOS15, is at the lowest potential. Since it is fixed, this wiring is unnecessary, and there is no need to take up a wiring area or a contact area. Therefore, it becomes possible to construct a high-speed inverter without significantly increasing the area.

Figure 4 shows a pattern for incorporating the circuit in Figure 3 into an actual IC. The inside of 16 is p
The outside of the well is an n-well, and the inside of the well 17 is a region where an element can be formed, and the outside is covered with a thick oxide film. 18 is a conductive band layer which becomes the gate of MOS, 19
is a contact hole connecting the wiring 20 and the region 17 or the wiring 20 and the conductive band layer 18. A p-type impurity is introduced into the n-well region to form a pMOS,
An n-type impurity is introduced into the p-well region to create an nMOS
is formed. The portion from which the terminal C is taken out is the conductive band layer 18 which becomes the gate of the MOS of the present invention.

Let's estimate the degree of improvement in inverter characteristics due to the addition of nMOS14 and pMOS15.
Both nMOS14 and pMOS15 W/L are 10/5
shall be. The time constant τ _oa for charging C _L by the nMOS 14 alone is calculated using equation (2) with β _0o =40 μS/V and V _To =0.5V, and becomes τ _oa =2.78ns. In addition, the time constant τ _pa for discharging C _L by the pMOS15 alone is given by β _0p = 20μS/V, V _Tp = 0.5V (1)
When found using the formula, τ _pa =5.56ns.

From this τ _oa and the previously determined output rise time constant τ _p of the pMOS12, the rise time constant τ _poa of the inverter with the new structure shown in Fig. 3 is determined as 1/τ _poa = 1/τ _p +1/τ _oa . Therefore, τ _poa = 1.04 ns Similarly, if we calculate the falling time constant τ _opa of the inverter with the new structure, we get τ _opa = 0.72 ns.

It can be seen that the rise characteristics are improved by about 38% and the fall characteristics are improved by about 13% compared to the inverter with the conventional structure.

FIG. 5 shows an example of applying the new structure inverter to an actual circuit. This is a high-speed buffer circuit that uses bipolar NPN transistors 26 and 27 connected to a totem pole at the output, with the dashed line 2
The part surrounded by 8 is the inverter of the present invention.

When input terminal F goes from low to high, node A
is low, node B is high, and MOS12,1
A current is supplied to the base of the transistor 26 through the transistor 26, and a collector current Ic determined by the current amplification factor of the transistor 26 flows. At this time, MOS23
is also on, so the load capacitance C _L is MOS2
3 and the transistor 26. Furthermore, since the MOS 25 is also on, the base current of the transistor 27 does not flow, and the accumulated charge between the base and emitter is also discharged, so that the transistor 27 is quickly cut off.

Next, when terminal F goes from high to low, node A
becomes high, but since MOS13 and 15 are turned on, node B becomes low. Therefore, at the same time that the MOSs 23 and 25 and the transistor 26 are turned off, the accumulated charge between the base and emitter of the transistor 26 is also discharged via the MOSs 13 and 15. On the other hand, the MOS 24 is turned on, current flows from the capacitor C _L to the base of the transistor 27, a collector current determined by the current amplification factor of the transistor 27 can flow, and the charge stored in the capacitor C _L is rapidly discharged. .

The output rise of such a high-speed buffer circuit,
The improvement in falling characteristics is achieved by transistors 26 and 27.
The key point is to improve the ability to supply current to the base. By using the inverter according to the present invention, the rise and fall characteristics of the buffer circuit can be improved compared to the conventional ones.

Now, in the inverter configuration shown in Fig. 3, the output fall characteristics depend on the conductance of MOS13 and MOS15, but the normal
In the CMOS inverter, the β ₀ of MOS13 is relatively large nMOS. Therefore, in the conventional inverter configuration shown in FIG. 1, the falling time constant of the output is already smaller than the rising time constant. Furthermore, in the circuit shown in FIG. 3, since the MOS 15 is a pMOS with relatively small β ₀ , the degree of improvement in the falling characteristic due to the addition of the MOS 15 is smaller than in the case of the rising characteristic. Although the estimate based on the numerical calculation shown earlier shows that the addition of nMOS14 improves the rise characteristics by 38%,
The improvement in fall characteristics by adding pMOS15 is 13
It remains at %.

Therefore, even if the pMOS15 is omitted and the structure shown in FIG. 6 is used, the characteristics will not deteriorate significantly compared to the structure shown in FIG. 3, and at least an inverter with better start-up characteristics than the conventional structure can be obtained. . Note that 29 is an n-type impurity layer.

Up to this point, we have described ICs with a CMOS structure that forms both an n-well and a p-well, or ICs that partially have this structure, but the device according to the present invention uses an n-type substrate to form a p-well.
It can also be easily applied to an IC having at least a portion of a CMOS structure or a CMOS structure in which an n-well is formed using a p-type substrate.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a semiconductor device, more specifically a CMOS inverter, having an element structure that allows high speed and high integration without changing the conventional IC manufacturing process.

[Brief explanation of drawings]

Figure 1 shows a conventional CMOS inverter.
Fig. 2 is a diagram showing the structure of an element according to the present invention, Fig. 3 is a diagram showing a structure in which the element according to the invention is applied to a CMOS inverter, and Fig. 4 is a pattern diagram when the inverter circuit of Fig. 3 is integrated into an IC. , FIG. 5 is a diagram showing an example of a buffer circuit incorporating an inverter according to the present invention, and FIG. 6 is a diagram showing a modification of the embodiment of the present invention shown in FIG. 3. 1...Semiconductor substrate, 2...n well, 3...p
well, 4... p-type impurity layer, 5... n-type impurity layer, 6... gate conductive band layer, 7... gate oxide film, 8... thick oxide film, 9... power supply, 10... conductive film , 11...Load capacitance, 12...Load pMOS,
13... Drive nMOS, 14... nMOS, 15...
pMOS, 16...Boundary between n-well and p-well, 1
7... Boundary between element formation region and field region, 1
8... Conductive band layer, 19... Contact hole, 20...
...Wiring layer, 21...pMOS, 22, 23, 24,
25...nMOS, 26,27...Bipolar
NPN transistor, 28... Inverter portion according to the present invention, 29... n-type impurity layer, A to G...
Nodes in a circuit.

Claims (1)

[Claims] 1. A semiconductor region of a second conductivity type and a semiconductor region of a first conductivity type are formed in a semiconductor substrate of a first conductivity type,
a first MOS transistor whose source and drain are a semiconductor layer of a first conductivity type provided in a semiconductor region of a second conductivity type, and whose gate is a first conductive film provided via an insulating film disposed on both the semiconductor regions; 1st
A second conductive type semiconductor layer provided in a conductive type semiconductor region is used as a source and a drain, and a conductive film provided via the insulating film is used as a gate. In the semiconductor device, a conductive film is provided on the boundary between the two semiconductor regions via the insulating film, and the conductive film is used as a gate, and the semiconductor region of the first conductivity type and the semiconductor layer of the first conductivity type are connected as a drain and a conductive film. A third MOS transistor is formed as a source, and a fourth MOS transistor shares a gate with the third MOS transistor and uses the second conductivity type semiconductor region and the second conductivity type semiconductor layer as a drain and a source. semiconductor device. 2. In claim 1, the semiconductor device is an inverter circuit in which the first MOS transistor is a drive MOS transistor and the second MOS transistor is a load MOS transistor;
The drain of the fourth MOS transistor is connected to the source of the transistor, the drain of the third MOS transistor is connected to the source of the second MOS transistor, and the drains of the first and second MOS transistors and the sources of the third and fourth MOS transistors are connected to each other. The semiconductor device is characterized in that the common gates of the third and fourth MOS transistors are connected to each other as output terminals of an inverter circuit, and a signal having an opposite phase to a signal input to the gates of the drive and load MOS transistors is input to the common gates of the third and fourth MOS transistors. . 3 forming a second conductivity type semiconductor region and a first conductivity type semiconductor region in a first conductivity type semiconductor substrate;
a first MOS transistor whose source and drain are a semiconductor layer of a first conductivity type provided in a semiconductor region of a second conductivity type, and whose gate is a conductive film provided via an insulating film disposed on both the semiconductor regions; A second conductive type semiconductor layer provided in a first conductive type semiconductor region is used as a source and a drain, and a conductive film provided through the insulating film is used as a gate. In the semiconductor device, a conductive film is provided on the boundary between the two semiconductor regions via the insulating film, and the conductive film is used as a gate and the semiconductor region of the first conductivity type and the semiconductor layer of the first conductivity type are connected as a drain. and a third MOS transistor serving as a source. 4. The semiconductor device according to claim 3, wherein a surface portion of the semiconductor region of the first conductivity type, which becomes the drain of the third MOS transistor, near the boundary includes an impurity layer of the first conductivity type. 5 In claim 3 or 4, the semiconductor device drives the first MOS transistor.
This is an inverter circuit in which a MOS transistor is used as a load MOS transistor, and a second MOS transistor is used as a load MOS transistor.
The drains of the three MOS transistors are connected, and the drains of the first and second MOS transistors and the source of the third MOS transistor are connected to each other to form the output terminal of the inverter circuit.
A semiconductor device characterized in that a signal having an opposite phase to a signal input to the gates of the drive and load MOS transistors is input to the gate of the 3MOS transistor.