JPH04207068A - Composite type semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to embody a BiCMOS circuit with a small area by incorporating integrally a p channel MOS transistor and an n channel MOS transistor into a bipolar transistor. CONSTITUTION:As for a first complex circuit A, an electrode 17, which is a source electrode of a p channel MOS transistor which is a collector electrode of an npn transistor, is connected with a power source Vcc where an n channel MOS transistor and gate electrodes 11 and 13 for the p channel MOS transistor are connected with each other in common, thereby forming an input terminal In while an electrode 15, which is a source electrode of the n channel MOS transistor which is an emitter of the npn transistor, forms an output terminal OUT. Then, as for a second complex circuit B, a gate electrode 37 of an n channel MOS transistor forms the input terminal IN which a drain electrode 42 and a collector electrode 41 form an output terminal OUT in common. An emitter electrode 39 is grounded. When the first complex circuit A is connected with the complex circuit B in serial, a BiCMOS inverter is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION CObject of the Invention] (Industrial Application Field) The present invention relates to a composite semiconductor device in which a bipolar transistor and an MO5I transistor are integrated on one semiconductor substrate.

(Prior Art) A BiCMO3 circuit that combines a bipolar transistor and an MO5I-transistor is known as a semiconductor integrated circuit that achieves a balance between low power consumption and high speed. This uses a CMOS structure for the logic circuit portion with low power consumption, and uses bipolar transistors in the logic circuit's 8 power stages, which require large current drive capability.

(Problems to be Solved by the Invention) Conventional BiCMOS circuits have a problem in that the chip area increases because bipolar transistors and MOS transistors are formed in separate regions of the substrate and electrically isolated from each other. Ta.

An object of the present invention is to solve such problems and provide a composite semiconductor device in which bipolar transistors and MOS transistors are integrated in a small area.

C. Configuration of the Invention (Means for Solving the Problems) A composite semiconductor device according to the present invention includes a semiconductor substrate, a first conductivity type collector layer, a second conductivity type base layer, and a second conductivity type base layer formed on the substrate. A bipolar transistor having an emitter layer of one conductivity type, a second conductive channel MOS transistor formed in the collector layer of the bipolar transistor, and a first conductive channel MOS transistor formed in the base layer of the bipolar transistor. It is characterized by

(Function) According to the present invention, a p-channel MO3 transistor and an n-channel MOS transistor can be integrated into a bipolar transistor to realize a BiCMOS circuit in a small area.

(Example) The present invention will be explained in detail below.

FIG. 1 is an example integrated circuit structure. here,
A first composite circuit A in which an npn transistor, a p-channel MOS transistor, and an n-channel MO3 transistor are formed therein using an epitaxial wafer in which an n-type epitaxial layer 3 is formed on a p-type silicon substrate 1, an npn transistor and n-channel MO in it
Second composite circuit B1 and n forming S transistors
A state in which a channel MOS transistor circuit C is formed is shown. In the composite circuits A and B, high concentration n+ type collector buried layers 21 and 22 are formed between the substrate 1 and the n- type epitaxial layer 3 in order to form an npn transistor.

In the first composite circuit A, a p-type base layer 4 and an n+-type emitter layer 5 are formed in an n-type epitaxial layer 3 to constitute an npn transistor. Continuously with the p-type base layer 4, an n-type well 6 is formed which serves as an external base layer of an npn transistor and also serves as a formation region of an n-channel MOS transistor. An n-channel MOS transistor is formed within this n-type well 6, that is, substantially within the base region of the npn transistor.

That is, the n+ type emitter layer 5 is used as a source layer, the n+ type drain layer 7 is formed in the n type well 6 at a predetermined distance from the source layer, and the n + type drain layer 7 is formed on the surface of the n type well 6 between them with the gate insulating film 10 interposed therebetween. A gate electrode 11 is formed, and n
A channel MOS transistor is configured. An n-channel MOS transistor is formed in the collector region on the opposite side of the n-channel MOS transistor with the emitter layer 5 in between. The n-channel MOS transistor uses the p-type base layer 4 as it is as a train layer, and a p-type source layer 9 is formed at a predetermined distance from these layers, and a gate electrode 13 is formed on the wafer surface between them via a gate insulating film 12.
It is composed of

In this embodiment, an epitaxial layer 3 is provided in the substrate region of this n-channel MOS transistor for threshold voltage control.
A higher concentration n-type well 8 is also formed. This n-type well 8 also functions to prevent thyristor operation. An n+ type layer 14 serving as a collector extraction layer is diffused to a depth that reaches the collector buried layer 2 so as to surround the first composite circuit A. The n-type layer 14 does not have to completely surround the composite circuit A. An electrode 17 is formed on the n + -type layer 14 and the source layer 9 of the n-channel MOS transistor to simultaneously contact them and serve as a collector electrode and a source electrode of the n-channel MOS transistor. An electrode 15 is formed in the n+ type emitter layer 5 and serves as an emitter electrode and a source electrode of an n-channel MOS transistor. n channel M
An electrode 1 short-circuiting the drain of the n-channel MOS transistor and the base of the npn transistor extends from the drain layer 7 of the OS transistor onto the n-type well 6.
6 is formed.

In the second composite circuit B, a p-type base layer 31 and an n+-type emitter layer 32 are formed in the n-type epitaxial layer 3, and an npn transistor is also configured. p
An n-type well 33 serving as an external base layer is formed continuous with the type base layer 31, and an n-channel MOS transistor is configured within this n-type well 33. Here, the n-channel MOS transistor has an n+ type source layer 34 . A drain layer 35 is formed, and a gate electrode 37 is formed on the well surface between these layers with a gate insulating film 36 interposed therebetween. An n1 type layer 38 serving as a collector extraction layer is formed by diffusion to a depth that reaches the collector buried layer 2.

A collector electrode 41 is formed in this n+ type layer 38, an emitter electrode 39 is formed in the emitter layer 32, and an electrode serving as a base electrode and a source electrode is formed in the p-type well layer 33 so as to straddle the source layer 34 of the MOS transistor. 40 is formed, and a drain electrode 42 is formed on the drain layer 35.

1st. A deep n-type well 20 is formed between the second composite circuits A and B, and this n-type well 20 is an n-channel MO
This is the area of the S transistor circuit C. In the figure, one n-channel MOS transistor is formed in this p-type well, that is, n"-type source and drain layers 21 and 22.
, an n-channel MOS transistor consisting of a gate electrode 24 formed with a gate insulating film 23 interposed therebetween is shown. The n-type well 20 of this n-channel MOS transistor circuit C is connected to the first . It also functions as an isolation region that electrically isolates the npn transistors of the second composite circuits A and B.

The operation of the composite semiconductor device configured as described above will be described next.

First, in the first composite circuit A, an electrode 17 which is a collector electrode of an npn transistor and a source electrode of a p-channel MOS transistor is connected to a power supply Vcc, and a gate electrode 11 of an n-channel MOS transistor and a p-channel MOS transistor is connected to a power supply Vcc. .13 are connected in common and the input terminal IN
The electrode 15, which is the emitter electrode of the npn) run risk and the source electrode of the n-channel MOS l-run risk, serves as the output terminal OUT. This first composite circuit A is therefore represented by the equivalent circuit of FIG. Output terminal O
Once the appropriate switching stage is connected to the UT, the BiCM
It becomes an OS inverter. The operation will now be described assuming that the output terminal OUT is grounded via a switching stage not shown in the figure. “L level (-V
ss) or enters, p channel MO5) run risk Q1
is turned on, a base current is supplied from the p-type source layer 9 to the p-type base layer 4 through the channel, and as a result, the npn
Transistor T1 is turned on. The npn transistor T1 and the p-channel MOS transistor T1 are the same as a so-called IGBT. Once, a base current is supplied to the p-channel MOS transistor RO 1 to turn it on, and electrons are injected from the emitter layer 5 to the p-type base layer 4, which pass through the n-type layer 3 to the p-type drain layer. 3, the device exhibits a low on-voltage due to the conduction modulation effect. As the current increases further,
Holes from the p-type source layer 9 are directly injected into the n-type layer 3, resulting in thyristor operation. In this embodiment, by forming an n-type well 8 around the p-type source layer 9, such a risk operation is prevented. Further, in order to suppress the thyristor operation, it is effective to shorten the width of the p-type source layer 9. On the other hand, when the input terminal IN reaches the "H" level -V cc), n
Channel MOS transistor Q2 is turned on and npn)
The base and emitter of run risk T1 are short-circuited, and np
n) Run risk is turned off. If the thyristor is designed so that it does not operate, high-speed off operation is possible.

Next, in the second composite circuit B, the gate electrode 37 of the n-channel MOS transistor is the input terminal IN, and the drain electrode 42 and collector electrode 41 are the common output terminal OUT.
Therefore, three emitter electrodes are grounded (Vss). This second composite circuit B is therefore shown in the equivalent circuit of FIG. If a suitable load is connected to this output terminal OUT, it becomes an inverter. To explain the operation assuming that an appropriate load is connected, the input terminal IN or “L”
When n-channel MOS) run risk Q3 is off, therefore npn) run risk T2 is also off.

When the input terminal "H" level is input, n-channel MOS) run risk Q3 is turned on, and this MOS) run risk Q3 is turned on.
A base current is supplied to the npn transistor T2 through the npn transistor T2, and the run risk T2 is turned on. This second composite circuit B differs from the first composite circuit A in that it has a pnp
There is no n structure, so there is no I GET operation,
Of course, the thyristor does not operate.

If the first composite circuit A and the second composite circuit B are connected in series, a BiCMOS inverter is directly configured. Fourth
The figure shows the equivalent circuit, and the output terminal OU of the circuit in Figure 2
T and the output terminal OUT of the circuit in Figure 3 are connected to a common output terminal O.
UT is assumed to be 1, and the respective input terminals IN are also used as a common input terminal IN.

According to this embodiment as described above, high-speed operation is possible and the iCMOS circuit can be constructed in a small area.

FIG. 5 shows an example in which the first composite circuit A and one n-channel MOS transistor Q4 in the n-channel MOS transistor circuit C are connected in series to form a BiCMOS inverter.

FIG. 6 shows another embodiment of the present invention, which is a modification of the first composite circuit A portion of FIG. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. In this embodiment, first, a base lead electrode 52 is formed from a polycrystalline silicon film in the bipolar transistor region before forming the p-type base layer. This base lead 52 is doped with a p-type impurity, for example, an n-channel MOS.
The gate electrode 13 of the transistor is patterned using the same polycrystalline silicon film at the same time. Using these base extraction electrodes 52 and gate electrodes 13 as masks, impurity ions are implanted to form the p-type base layer 4 which becomes an internal base layer. Then, the impurities in the base extraction electrode 52 are diffused into the wafer to form the p-type layer 6 which becomes the external base layer. After that, the base extraction electrode 52 and the gate electrode 1
3 is covered with an oxide film 58, a polycrystalline silicon film 51 is deposited in the emitter opening, and impurities are doped through this polycrystalline silicon film 51 to form an n'' type emitter layer 5. In this embodiment, a p-type well 53 forming an n-channel MO3) run lister is formed outside the bipolar transistor region, apart from the p-type base layer 6.

This p-type well 53 has an n″-type drain, and a drain layer 54
．． 55 is formed, and a gate electrode 11 is formed between these with a gate insulating film 10 interposed therebetween. n-channel MO
The drain electrode 56 of the S transistor is commonly connected to the base electrode 16 that contacts the base extraction electrode 52 of the bipolar transistor. A source electrode 57 is arranged so as to contact the source layer 55 and the p-type well 53 at the same time, and is connected to the emitter electrode 15 of the bipolar transistor. As a result, a composite circuit represented by the equivalent circuit in FIG. 2, which is the same as the first composite circuit A in FIG. 2, is obtained.

FIG. 7 shows an embodiment in which the structure of FIG. 6 is modified.

In this embodiment, the isolation structure between the bipolar transistor region and the n-channel MOS transistor region is different from that in FIG. That is, a trench 61 deep enough to reach the substrate 1 is formed in the isolation region, and an oxide film 62 is formed in the trench 61.
Undoped polycrystalline silicon 63 is buried therein.

FIG. 8 shows another embodiment in which the structure of FIG. 6 is modified. In this embodiment, the internal base layer is a silicon-germanium alloy layer (SiGe layer) 71 which is a strained epitaxial layer.
The bipolar transistor is a heterojunction bipolar transistor. That is, after forming the p-type external base layer 6 with some kind of mask formed in the emitter region, the mask in the emitter region is removed and the p-type 5iGe alloy layer 71 is epitaxially grown.

A polycrystalline silicon emitter layer 7 is formed on this 5iGe layer 71.
form 2. The portion of the SiGe layer 71 extending over the oxide film 58 is formed into a base electrode 16 by the polycrystalline silicon film 73.
It is connected to the. The external base layer 6 has the effect of lowering the base resistance and is in contact with the 5iGe layer 71.

The embodiments shown in FIGS. 6 to 8 can also provide the same effects as the previous embodiments.

The present invention is not limited to the above embodiments. For example, in the embodiment, an npn) run lister is used as the bipolar transistor, but a pnp) run lister may also be used. In that case, the n-channel MOS transistor of the embodiment and the n-channel MOS transistor may be reversed.

[Effects of the Invention] As described above, according to the present invention, a bipolar transistor and a MOS (MOS) run lister are integrated to form a BiC in a small area.
A composite semiconductor device that can realize an MO5 circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the structure of a composite semiconductor device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of part A of the first composite circuit in FIG. 1, and FIG. Figure 4 is an equivalent circuit diagram of a BiCMOS inverter obtained by connecting the first composite circuit A and the second composite circuit B in series. Figure 5 is an equivalent circuit diagram of the first composite circuit A. An equivalent circuit diagram of a BiCMOS inverter obtained by connecting an n-channel MOS transistor in series, FIG. 6 is a diagram showing the structure of a composite semiconductor device according to another embodiment, and FIG. 7 is a diagram showing the structure of a composite semiconductor device according to another embodiment. FIG. 8 is a diagram showing the structure of a composite semiconductor device according to yet another embodiment. 1...p-type silicon substrate, 2...n'' type collector buried layer, 3...n-type epitaxial layer, 4...p-type base layer (also drain layer), 5...n'' type Emitter layer (drain layer), 6...n-type well, 7...n"
type source layer, 8... n-type well, 9... p-type source layer, 10.12... gate insulating film, 11.13...
Gate electrode, 14... n+ type collector extraction layer, ]5
゜16.17... Electrode, 20... N-type well, 21
, 22...n" type source, drain layer, 23... gate insulating film, 24... gate electrode, 31...p type base layer, 32...n+ type emitter layer, 33・・・
・N-type well, 34...n+ type source layer, 35...
n" type drain layer, 36... gate insulating film, 37...
・Gate electrode, 38... n+ type collector extraction layer, 3
9,40,4],,42...electrode. 0UT 112 figure ss figure 4 ss figure 3 ss figure 5

Claims (1)

[Scope of Claims] (1) A bipolar transistor having a semiconductor substrate, a first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type emitter layer formed on the substrate; a second conductive channel MOS transistor in which a second conductivity type source and drain layer are formed in the collector layer; and a first conductive channel MOS transistor in which a first conductivity type source and drain layer are formed in the base layer of the bipolar transistor.
A composite semiconductor device comprising: an S transistor; (2) The drain layer of the second conductive channel MOS transistor is shared with the base layer of the bipolar transistor, and the source layer of the first conductive channel MOS transistor is shared with the emitter layer of the bipolar transistor. The composite semiconductor device according to claim 1, characterized in that: (3) a semiconductor substrate; a first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type emitter layer formed on the substrate;
a second conductive channel MOS transistor in which a source and drain layer of a second conductivity type are formed in the collector layer of the first bipolar transistor; and a first conductive channel MOS transistor in the base layer of the first bipolar transistor. a first composite circuit in which a first conductive channel MOS transistor having type source and drain layers is formed; a first conductive type collector layer, a second conductive type base layer and a first conductive type collector layer formed on the substrate; a second type emitter layer;
a second composite circuit in which a first conductive channel MOS transistor having a first conductive type source and drain layer formed in a base layer of the second bipolar transistor is formed; , a first conductive channel type MOS transistor circuit in which a first conductive channel type MOS transistor is formed in a second conductive type well formed in a region different from the second bipolar transistor; Composite semiconductor device. (4) The drain layer of the second conductive channel MOS transistor is shared with the base layer of the bipolar transistor, and the source layer of the first conductive channel MOS transistor is shared with the emitter layer of the bipolar transistor. The composite semiconductor device according to claim 3, characterized in that: (5) In the first composite circuit, the collector of the first bipolar transistor and the source of the second conductive channel type MOS transistor serve as a power supply, and the emitter of the first bipolar transistor and the source of the first conductive channel type MOS transistor serve as a power supply. The gates of the first conductive channel type MOS transistor and the second conductive channel type MOS transistor are commonly connected to the input terminal, respectively, to the output terminal, and the second composite circuit connects the collector of the second bipolar transistor and the first conductive channel type MOS transistor. The source of the channel type MOS transistor is connected to the output terminal, the emitter of the second bipolar transistor is connected to the ground terminal, and the first conductive channel type MOS transistor
4. The composite semiconductor device according to claim 3, wherein a gate of a transistor is connected to the input terminal, and a BiCMOS inverter is configured by the first and second composite circuits.