JPH09191054A - Cmos transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase in a chip area and also to improve latch-up immunity of a complementary MOS (CMOS) transistor. SOLUTION: A p short-circuiting region 8 of a stripe shape having a minimum width for interconnection between a p well region 3 and a VSS electrode 1 is provided parallel to a gate electrode 6 so as to isolate an n source region 7 within the p well region 3, thereby lowering a base resistance of a parasitic npn transistor. Or such a p short-circuiting region as to separate an n source region 17 in a direction normal to the strip-shaped gate electrodes 6 provided at regular intervals may be provided in part of the n source region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary (complementary) MOS transistor (hereinafter referred to as a CMOS transistor), particularly a CMOS which requires a relatively large drive current such as an output circuit of a semiconductor integrated circuit or a clock buffer circuit. Regarding transistors.

[0002]

2. Description of the Related Art A cross-sectional view of a general CMOS transistor is shown in FIG. In addition, in the following, the areas with n and p are
It is assumed that the majority carriers are electrons and holes, respectively. p source region 57 and p drain region 59 formed on the surface layer of the n-type substrate 50, and the n-type substrate 5 between them.
P-channel MOSFET 64 including a gate electrode 56 formed on the surface of 0 through a gate oxide film 51.
, An n source region 47 and an n drain region 49 formed in the surface layer of the p well region 43 formed in the surface layer of the n type semiconductor layer 50, and a gate oxide film 52 on the surface of the p well region 43 therebetween. There is an n-channel MOSFET 65 composed of a gate electrode 46 formed via the electrode, and the two drain regions are connected to a common output terminal 63 via an electrode (not shown). The two gate electrodes are connected to a common gate terminal 62. p source region 57
Together with the n contact region 54 formed in the surface layer of the n-type semiconductor layer 50 to the V _DD terminal 60, and the n source region 4
Reference numeral 7 is connected to the V _SS terminal 61 together with the p contact region 44 formed in the surface layer of the p well region 43.

Since this CMOS transistor is composed of a combination of pn junction structures, various parasitic elements exist. For example, p source region 57, n type substrate 50
And a p-well region 43, and a parasitic pnp transistor 71, and an n-source region 47 and a p-well region 4.
There is a parasitic npn transistor 72 consisting of 3 and n-type substrate 50. Here, 50 is an n-type substrate, but it goes without saying that it may be an n-type layer on a p-type substrate.

The latch-up phenomenon of the CMOS transistor will be briefly described. Latch-up is a danger that a large current flows from the V _DD power supply terminal 60 to the V _SS power supply terminal 61 due to noise or the like entering or exiting the semiconductor integrated device, it does not stop, and sometimes permanent damage occurs. It is a phenomenon. The latch-up occurs when the parasitic pnpn transistor 71 and the parasitic npn transistor 72 are turned on to operate the parasitic pnpn thyristor. Once latch-up occurs, it becomes uncontrollable and current drains until the V _DD power supply is turned off.

To prevent latch-up, a parasitic pnp
Do not operate n thyristor, that is, parasitic pn
p-transistor 71 and parasitic npn-transistor 72
Is not turned on, and for that purpose, it is important not to increase the current amplification factor of each transistor. FIG.
Is an n-channel MOSFET of a CMOS transistor
FIG. 65 is a plan view of a portion 65. In general, the internal circuit of a semiconductor integrated device has a layout as shown in the plan view of FIG. 4 for higher integration. In the figure, an n source electrode 47 and an n drain region 4 are provided in the p well region 43.
9 is formed, and the gate electrode 46 is provided on the surface of the p well region 43 between them via an insulating film. The n source region 47 and the n drain region 49 are respectively connected to the V _SS electrode 41 and the drain electrode 42 through a contact hole 45 (shown by a dotted line) formed in the insulating film above them. The V _SS electrode 41 is also connected to the p contact region 44 formed in the p well region 43.

On the other hand, the parasitic pnp transistor 71 is used for the input and output portions susceptible to noise and the bus driver and clock buffer circuit in which the current of the parasitic element is large.
The distance between the p-channel type MOSFET 64 and the p-well region 43, which is the base width of the, is increased to make it difficult to turn on the parasitic transistor. There is also a method of reducing the base resistance of the parasitic transistor, the current amplification factor, and the operation of the parasitic thyristor by reducing the substrate resistance 73 and the p-well resistance 74 of FIG.

FIG. 5A shows a plan view of an n-channel MOSFET of a CMOS transistor in the output portion. In this case, p-guard ring region 84 having a high impurity concentration is provided in p-well region 83 for the above-mentioned purpose so as to surround n-source region 87 and n-drain region 89. 8
6 is a gate electrode provided on the insulating film, and 81 is V
_{The SS} electrode and 82 are drain electrodes. Gate electrode 86
Are connected to each other at portions not shown. FIG.
5B is a sectional view taken along the line AA ′ of FIG. Reference numeral 92 is an insulating film such as an oxide film that insulates the silicon substrate from each electrode.

[0008]

However, in the MOS device having a large channel width as shown in FIG. 5, the p-guard ring region 84 reduces the resistance of the portion close to the periphery of the p-well region 83, but the central region of the p-well region 83 reduces the resistance. In the part, the value of the p-well resistance is considerably large. Therefore, as a countermeasure against latch-up, it is necessary to greatly separate the p-channel MOSFET 64. Increasing the distance increases the dead space in which elements cannot be formed, which reduces the area efficiency of the semiconductor integrated device and is disadvantageous in terms of cost.

In addition, SOS (Silicon on Saphire),
A CMOS transistor such as SOI (Silicon on Insulator) made on thin film silicon on an insulator is known as latch-up free, but it is expensive and unrealistic to use only for latch-up countermeasures. In view of the above problems, an object of the present invention is to provide a CMOS transistor having a large latch-up resistance while avoiding an increase in element area.

[0010]

In order to solve the above problems, the present invention provides a second conductivity type well region formed in a surface layer of a first conductivity type semiconductor layer and a surface layer of the second conductivity type well region. A first conductivity type source region and a first conductivity type drain region, both of which are formed in a stripe shape, and a gate on the surface of the second conductivity type well region between the first conductivity type source region and the first conductivity type drain region. In a CMOS transistor having a gate electrode formed through an oxide film, a source electrode provided in contact with a first conductivity type source region, and a drain electrode provided in contact with a first conductivity type drain region , A second conductivity type short circuit region connecting the second conductivity type well region and the source electrode in the first conductivity type source region.

By doing so, the base resistance of the parasitic transistor can be reduced, and the current amplification factor of the parasitic npn transistor is lowered. In particular, it is assumed that the second conductivity type short circuit region divides the first conductivity type source region. By doing so, a high-concentration short-circuit path close to the surface can be formed, and the base resistance of the parasitic transistor can be further reduced.

The second-conductivity-type short-circuit region has a stripe shape and is formed parallel to the gate electrode. By doing so, the distance of the short circuit is short and the effect of reducing the base resistance is large. Further, it has a contact hole extending over the second conductivity type short-circuit region and the first conductivity type source region.

By doing so, the second conductivity type short circuit region can be formed with the minimum processing dimension width. Further, the second conductivity type short-circuit region may have a strip shape, and the first conductivity type source region may be divided in a direction perpendicular to the gate electrode. By doing so, the distance of the short circuit is short and the effect of reducing the base resistance is large. The insulating film on the second-conductivity-type short-circuit region has contact holes of the same size as the first-conductivity-type source region and equally spaced.

By doing so, the effect of reducing the base resistance acts evenly.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows an n-channel MOSF of a CMOS transistor according to the first embodiment of the present invention.
A plan view of the silicon surface seen through the electrode of the ET portion,
FIG. 1B is a sectional view taken along the line BB ′ of FIG. In particular, MOSFE with a large channel width such as the output section
It is a structure suitable for T. The ends of the electrodes are shown by thick lines, and the boundaries of the diffusion regions on the silicon substrate surface are shown by thin lines.

In FIG. 1A, an n source region 7 and an n drain region 9 are formed in the p well region 3,
A gate electrode 6 of polysilicon is provided on the surface of the p well region 3 between them with an insulating film interposed therebetween. The n-source region 7 and the n-drain region 9 are both formed in stripes and arranged alternately, as in the conventional example of FIG. 5, but in this embodiment, the n-source region 7 is formed in the n-source region 7. A thin p short circuit region 8 parallel to the stripe is formed. The n source region 7 and the p short-circuit region 8 are connected to the V _SS electrode 1 made of an Al alloy through a contact hole 5 (shown by a dotted line) formed in the insulating film above them. The V _SS electrode 1 is also connected to the p guard ring region 4 formed near the periphery of the p well region 3. A contact hole 5 is also opened in the insulating film on the n-drain region 9 and is connected to the drain electrode 2.

Since the n source region 7 and the p well region 3 have the same potential, the p short-circuit region 8 in FIG. 1 has a thin striped shape that can be processed in the impurity ion implantation step. It is short-circuited with the n source region 7. Normally, the contact hole 5 for contacting the V _SS electrode 1 and the drain electrode 2 with the diffusion region may be formed inside by a certain distance from the diffusion region for the convenience of alignment accuracy of the photomask during manufacturing. Although necessary, if a contact hole extending over the p short-circuit region and the n source region is provided, the p short-circuit region can be formed with the minimum processing dimension width, and the increase in area can be minimized.

FIG. 1B is a sectional view taken along the line BB ′ of FIG. An n source region 7 and an n drain region 9 are alternately formed on the surface layer of the p well region 3 formed on the surface layer of the n type substrate 10, and the p region between them is formed.
An n-channel type MOSFE composed of a gate electrode 6 formed on the surface of the well region 3 with a gate oxide film 11 interposed therebetween.
A cross section of T can be seen. A p short circuit region 8 is formed in the center of the n source region 7. A p guard ring region 4 is formed near the periphery of the p well region 3.
The upper surface and the side surface of the gate electrode 6 are covered with the insulating film 12,
Insulated from other electrodes.

As described above, by forming the stripe-shaped p short-circuit region 8 connected to the p-well region 3 in the n-source region 7 of the n-channel MOSFET part, the parasitic n-type region is formed.
The p-well resistance value serving as the base resistance of the pn transistor is significantly reduced. For this reason, the current amplification factor of the parasitic npn transistor is lowered, and the latch-up withstand capability of the CMOS transistor can be improved.

In particular, as shown in FIG. 1A, the p short circuit region is n
In the case where the source region is divided, a high-concentration short circuit path close to the surface is formed, and the base resistance of the parasitic transistor can be further reduced. FIG. 2 shows an n-channel MOSF having a large channel width of a CMOS transistor according to another embodiment of the present invention.
It is a top view of an ET portion.

A part of the n source region 27 is replaced with a p short circuit region 28.
As a structure, a conductive contact with the p-well region 23 is obtained. The p short-circuit region 28 does not need to have a large area, and may have an area sufficient to obtain conductivity with one contact hole 25. In addition, they are formed at regular intervals. In the example of FIG. 2, four short-circuit p short-circuit regions 28
Are formed.

In this case as well, the p-well resistance value which is the base resistance of the parasitic npn transistor is significantly reduced. For this reason, the current amplification factor of the parasitic npn transistor is lowered, and the latch-up withstand capability of the CMOS transistor can be improved. As shown in FIG. 2, if contact holes 25 having the same size as the n source region 27 and having equal intervals are formed in the insulating film on the p short-circuit region 28, the mask can be easily manufactured and the effect of reducing the base resistance can be made uniform. To work.

[0023]

As described above, according to the present invention, the second conductivity type p short circuit region connected to the first conductivity type well region is formed in the second conductivity type source region in the first conductivity type well region.
By forming a striped or strip shape,
Since the well resistance value serving as the base resistance of the parasitic bipolar transistor is lowered and the current amplification factor of the parasitic bipolar transistor is lowered, the latch-up resistance of the CMOS transistor can be improved.

This method does not require a large distance between the MOSFET serving as the base resistance of the parasitic pnp transistor and the well region, does not require a large device area, and improves device integration and reduces manufacturing cost. It is advantageous.

[Brief description of the drawings]

FIG. 1A is a plan view of an n-channel MOSFET portion of a CMO transistor of an embodiment of the present invention, and FIG. 1B is a sectional view taken along line BB ′ of FIG.

FIG. 2 is a plan view of another embodiment of the present invention.

FIG. 3 is a sectional view of a general CMOS transistor.

FIG. 4 is an n-channel MOSF of a CMOS transistor
Plan of ET part

FIG. 5A is a plan view of an n-channel MOSFET portion of a conventional semiconductor integrated device, and FIG. 5B is a line AA ′ of FIG.
Cross section along the line

[Explanation of symbols]

1, 41, 81 V _SS electrode 2, 42, 82 drain electrode 3, 23, 43, 83 p well region 4, 84 p ⁺ guard ring region 5, 25, 45, 85 contact hole 6, 46, 56, 86 gate Electrodes 7, 27, 47, 87 n Source region 8, 28 p ⁺ short-circuit region 9, 29, 49, 89 n Drain region 10, 50 n-type substrate 44 p ⁺ contact region 11, 51, 52 Gate insulating film 12, 92 Insulating film 54 n ⁺ contact region 57 p source region 59 p drain region 60 V _DD power supply terminal 61 V _SS power supply terminal 62 gate terminal 63 output terminal 64 p-channel MOSFET 65 n-channel MOSFET 71 parasitic pnp transistor 72 parasitic npn transistor 73 Substrate resistance 74 p-well resistance

Claims (6)

[Claims] 1. A second conductivity type well region formed in a surface layer of a first conductivity type semiconductor layer and a striped first conductivity type source region formed in a surface layer of the second conductivity type well region. A first conductivity type drain region, a gate electrode formed on the surface of the second conductivity type well region between the first conductivity type source region and the first conductivity type drain region via a gate oxide film, and In a CMOS transistor having a source electrode provided in contact with a conductivity type source region and a drain electrode provided in contact with a first conductivity type drain region, a second conductivity type well in the first conductivity type source region A CMOS transistor having a second conductivity type short circuit region connecting the region and the source electrode. 2. The C according to claim 1, wherein the second conductivity type short-circuit region divides the first conductivity type source region.
MOS transistor. 3. The CMOS transistor according to claim 2, wherein the second conductivity type short-circuit region has a stripe shape and is formed in parallel with the gate electrode. 4. The CMOS transistor according to claim 2, further comprising a contact hole extending over the second conductivity type short-circuit region and the first conductivity type source region. 5. The CMOS transistor according to claim 2, wherein the second-conductivity-type short-circuit region has a strip shape and divides the first-conductivity-type source region in a direction perpendicular to the gate electrode. 6. The CMOS transistor according to claim 5, wherein the second conductivity type short-circuit region has contact holes of the same size and equally spaced as the first conductivity type source region.