JPH06349852A - Mos type field-effect transistor - Google Patents

Abstract

PURPOSE:To acquire a device having high electrostatic breakdown strength wherein junction breakdown caused by a current due to static electricity in a low doped drain region is prevented without increasing an occupied area by making a breakdown strength of a junction between a base layer and a drain layer where-with a drain electrode is in contact lower than a drain-to- source breakdown strength. CONSTITUTION:A source/drain layer of an LDD structure which is composed of high doped first regions 81, 82 wherewith an electrode 10 is in contact with a channel region immediately below a gate electrode 5 between and a second region of a low doped region 6 extending immediately below the gate electrode 5 is provided in a surface layer of a base layer 2. A breakdown strength of a lane-type junction formed between the first region 81 of one source/drain layer and the base layer 2 is made lower than a drain-to-source breakdown strength and the source/drain layer is used as a drain. For example, impurity concentration of a layer part 21 of the base layer 2 in proximity to a plane type junction with the drain layer of the first region 81 is made higher than that of other parts of the base layer 2.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an LDD (Lightly dope).
The present invention relates to a MOS type field effect transistor (hereinafter referred to as MOSFET) having a d dvain structure.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of devices, deterioration of the device due to the generation of hot carriers due to a strong electric field in the channel region near the drain region has become a problem with MOSFETs. In order to solve this problem, an LDD structure has been proposed in which a low impurity concentration region is provided near the drain region to relax the electric field.

2 (a) to 2 (c) show a manufacturing process of a MOSFET having such an LDD structure. A p well 2 is formed on one surface of an n-type silicon substrate 1 and then a thin gate oxide film 3 is formed. The surface is covered with a thick selective oxide film 4, and a gate 5 made of polycrystalline silicon is formed on the gate oxide film 3. Then, using the gate 5 and the selective oxide film 4 as a mask, an n region 6 having a low impurity concentration is formed [FIG. 2 (a)]. Next, after depositing a SiO ₂ film on the surface, spacers 7 are left on the side surfaces of the gate 5 by reactive ion etching (RIE), and then the SiO ₂ spacer 7 and the selective oxide film 4 are formed.
With the mask as a mask, the n ⁺⁺ source / drain regions 81, 82 of high impurity concentration in contact with the drain electrode or the source electrode are contacted.
Are formed [Fig. 2 (b)]. After that, the interlayer insulating film 9 is covered, the contact hole is opened, and the Al electrode wiring 10 is brought into contact [FIG. 2 (c)].

[0004]

However, the conventional MOSFET having the LDD structure has a problem that the resistance to static electricity is significantly lowered. The cause of the decrease in withstand voltage is that when a current due to static electricity flows through the n region 6 forming a part of the drain, thermal runaway is likely to occur due to the low impurity concentration, and when the n ⁺⁺ region 81 is used as the drain, This is because the joint at the portion indicated by A is easily broken.

On the other hand, a MOS having an LDD structure
In order to increase the electrostatic discharge withstand capability of the FET, there are a method of using a single drain structure without using the LDD structure only for the output element of the semiconductor integrated circuit, a method of increasing the area, or a method of forming an output protection diode. Therefore, the occupied area is increased, which is contrary to the high integration of the semiconductor device.

An object of the present invention is to provide a MOSFET having a high electrostatic breakdown resistance, which prevents a junction breakdown caused by a current flowing by static electricity in a low impurity concentration drain region of an LDD structure without increasing an occupied area. .

[0007]

In order to achieve the above object, the present invention provides a high impurity concentration in which an electrode is in contact with a surface layer of a base layer of the first conductivity type across a channel region directly below a gate electrode. Between a first region of one source / drain layer and a base layer in a MOSFET provided with a source / drain layer of an LDD structure consisting of a first region of the The withstand voltage of the planar junction formed in 1) is lower than the withstand voltage between the drain and the source, and this source / drain layer is used as the drain. Further, it is effective that the layer portion near the planar junction with the first region of the source / drain layer used as the drain of the base layer has a higher impurity concentration than the other portions of the base layer. It is effective that the breakdown voltage between the source / drain layer and the base layer is adjusted by the impurity concentration of the layer portion of the base layer close to the junction with the first region of the source / drain layer. Further, according to the present invention, the strip-shaped source / drain layer provided on the surface layer of the base layer of the first conductivity type with the channel region immediately below the gate electrode interposed between at least the region of high impurity concentration in contact with the source / drain electrode. , A source / drain layer having an LDD structure consisting of a region of low impurity concentration extending directly under the gate electrode, and a surface layer having a high impurity concentration of the base layer is exposed at the outer periphery of the semiconductor substrate with a rectangular inner periphery. In the above, the source / drain layers facing each other on the inner three sides and the outer three sides of the high-impurity concentration surface layer of the base layer are used as drain regions, and the height of the base layer facing each outer side of the drain region is opposite. The distance from each side of the inner circumference of the impurity concentration surface layer is substantially equal.

[0008]

The breakdown voltage of the junction between the drain layer in contact with the drain electrode and the base layer provided with the channel region is made lower than the breakdown voltage between the drain and source of the MOSFET by increasing the impurity concentration of the base layer surface layer. As a result, when static electricity enters the drain, the junction is used as a current path, and the current due to static electricity is made difficult to flow in the low impurity concentration diffusion region extending directly below the gate electrode of the drain layer of the LDD structure, and the low impurity concentration diffusion region is formed. It is intended to prevent the joint destruction. Further, the place where the breakdown voltage is determined is a planar junction so that the current path is not concentrated at one point, and the current capacity that can be passed through the junction is increased.

In addition, the drain and the source are opposed to each other only on one side, and the drain and the exposed surface layer of the base layer are opposed to each other at equal distances on three sides to increase the opposed peripheral length, thereby making the current path longer. It becomes easier to connect between the drain and base layers, and prevents junction breakdown in the low impurity concentration diffusion region. In this way, by making it difficult for the current to concentrate in the low impurity concentration region junction, when the current is injected into the element by static electricity, the current capacity that can flow in the junction increases.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings in which the same reference numerals are given to common portions including FIG. MOSFE of one embodiment of the present invention shown in FIG.
T was produced as follows. First, the surface impurity concentration is 2 × 10 ¹⁶ c due to diffusion from the surface of the n-type silicon substrate 1.
After forming the p well 2 having m ⁻³ and a diffusion depth of 6 μm, a p ⁺ diffusion region 21 having a higher impurity concentration than the p well having a surface impurity concentration of 2 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 0.5 μm is formed. . Next, the surface is covered with a thin gate oxide film 3 of 250 Å and a thick selective oxide film 4 [FIG. 1 (a)]. Next, a polycrystalline silicon layer is laminated on the gate oxide film 3, and the polycrystalline silicon layer is patterned to form a gate 5. Using the gate 5 and the selective oxide film 4 as a mask, 2 × 10 ¹³ atoms · cm ⁻ As ions are implanted at a dose of about ² and n with a low impurity concentration for LDD structure is used.
Region 6 is formed [FIG. 1 (b)]. Furthermore, on the surface
₂ films were deposited to a thickness of 0.8 μm, As ⁺ was implanted at a high dose using the spacer 7 formed on the side surface of the gate 5 as a mask by etching by RIE, and a high impurity concentration n ^{+ +} region 81, 82 is formed [Fig. 1 (c)]. p ⁺ region 21 and the n ⁺⁺ region 81 to create a planar junction is the drain region, it is a source region other n ⁺⁺ region 82. After that, the interlayer insulating film 9 is covered, contact holes are opened, and Al electrode wiring is formed.
A MOSFET is completed by bringing 10 into contact [Fig. 1 (d)].

The device characteristics of the manufactured MOSFET are that the drain-source breakdown voltage is 20 V, and the n ⁺⁺ drain region is
The planar junction breakdown voltage between 81 and the p ⁺ region 21 of the base layer is 10V.
Becomes As a result, when positive static electricity enters the drain, the current does not flow into the n region 6, but flows through the planar junction formed by the n ^{+ +} region 21 and the p region 82 having a low breakdown voltage, and the n region 6 It can be prevented from being damaged by static electricity. As a result, 20
With the 0PF / 0Ω test method, the withstand capacity of the conventional 150 V is 500 V
I was able to raise it to.

In this embodiment, an n-channel MOSFET is used.
However, the same applies to p-channel MOSFETs.
I was able to get the effect. The present invention also arranges the elements.
Further increase the electrostatic breakdown resistance by specifying
You can FIG. 3 shows the element arrangement of the present invention. p well 2
Is provided on the surface layer of the outer peripheral portion of the p-well 2 for connection with
P⁺⁺A diffusion region 22 surrounds the MOSFET.
A contact 11 is provided. This is a CMOS element
Also serves as a diffusion area for important latch-up prevention in the child
It Two gates 5 are arranged. p ⁺⁺Inside area 22
N provided in close proximity⁺⁺Region 81 is the drain region,
Also, n in the middle of the gate 5⁺⁺Region 82 is the source region
Connected to an external circuit, p⁺⁺Region 22 and n⁺⁺Between area 81
, A and b are equal. To use this structure
Than p on three sides⁺⁺Drain region 81 adjacent to region 22
The peripheral lengths facing each other are the drain region 81 and the source region.
Since it is longer than the perimeter of only one side facing 82,
The current flowing from the rain to the source does not increase, and the drain
Current flowing from the drain to the p-well becomes dominant
On the other hand, the low impurity concentration diffusion region 6 which is a weak junction is protected.
it can. The MOSFET of this embodiment is the saw shown in FIG.
20 compared to conventional MOSFETs with outer region 82 outside
It has become possible to improve the 0 V tolerance.

[0013]

According to the present invention, the breakdown voltage between the drain layer of the LDD structure and the base layer in which the channel is formed is made lower than the breakdown voltage between the drain and the source, or the drain layer and the base of the outer periphery of the semiconductor substrate. By making the peripheral length facing the layer exposed region longer than the drain / source facing peripheral length, the current flowing due to static electricity in the low impurity concentration region is suppressed, and the junction breakdown of the low impurity concentration region is prevented. As a result, it was possible to obtain a MOSFET capable of achieving both an LDD structure and a high electrostatic breakdown resistance.

[Brief description of drawings]

FIG. 1 shows a manufacturing process of a MOSFET according to an embodiment of the present invention.
Sectional views shown in order from (a) to (d)

FIG. 2 (a) shows a manufacturing process of a conventional LDD type MOSFET.
To (c) cross section

FIG. 3 is a plan view of a MOSFET semiconductor element body according to another embodiment of the present invention.

FIG. 4 is a plan view of a conventional MOSFET semiconductor element body.

[Explanation of symbols]

1 n-type silicon substrate 2 p-well 21 p-well high impurity concentration region 3 gate oxide film 5 gate 6 source / drain n-type low impurity concentration region 7 spacer 81 n ⁺ drain region 82 n ⁺ source region 9 interlayer insulating film 10 electrode wiring

Claims (4)

[Claims] 1. A high impurity concentration first region in contact with a channel region immediately below a gate electrode on a surface layer of a base layer of the first conductivity type and a low impurity concentration region extending immediately below a case electrode. In a case where a source / drain layer having an LDD structure composed of two regions is provided, the breakdown voltage of a planar junction formed between the first region of one source / drain layer and the base layer is higher than the breakdown voltage between the drain and the source. A MOS type field effect transistor which is low, and in which this source / drain layer is used as a drain. 2. The MOS according to claim 1, wherein the layer portion adjacent to the planar junction with the first region of the source / drain layer used as the drain of the base layer has a higher impurity concentration than the other portions of the base layer. Type field effect transistor. 3. A breakdown voltage between a source / drain layer used as a drain and a base layer is adjusted by an impurity concentration of a layer portion of the base layer adjacent to a junction with the first region of the source / drain layer. The MOS type field effect transistor according to claim 2. 4. A strip-shaped source / drain layer provided on a surface layer of a base layer of the first conductivity type, sandwiching a channel region immediately below a gate electrode, and at least a region of high impurity concentration in contact with the source / drain electrode. A source / drain layer having an LDD structure consisting of a region of low impurity concentration extending directly below the gate electrode, and a surface layer having a high impurity concentration of the base layer is exposed at the outer periphery of the semiconductor substrate with a square inner periphery. , The source / drain layers facing each other on the inner and outer three sides of the high-impurity-concentration surface layer of the base layer are used as drain regions. MO characterized in that the distance from each side of the inner periphery of the impurity concentration surface layer is substantially equal.
S-type field effect transistor.