JP2826024B2 - Method for manufacturing MOS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor.

[0002]

2. Description of the Related Art FIG. 11 shows an integrated circuit (hereinafter referred to as "IC: in").
MOS field effect transistor (hereinafter referred to as “MOSFET: metal oxid
e semiconductor field effect transistor ")
1 shows a basic cross-sectional structure. As shown in FIG. 11, the MOSFET includes a channel region 2 in a surface layer portion of a P-type silicon substrate 1.
An N-type source region 3 and an N-type drain region 4 are formed sandwiching. Then, a gate 6 is formed on the channel region 2 of the silicon substrate 1 via a gate oxide film 5 so as to bridge the source region 3 and the drain region 4.

[0003] With the recent development of the semiconductor industry, high integration of elements has been desired.
ET is being miniaturized. That is, MOSFET
In accordance with the scaling rule proposed by Dennard et al., The dimensions of each part of the MOSFET are scaled down to cope with high integration of devices. The basic concept of scaling is that when the lateral dimension of the MOSFET, that is, the length and width of the channel region 2 are 1 / α (α: scaling factor), the vertical dimension of the MOSFET, that is, the gate oxide film 5 And the junction depth of the source region 3 and the drain region 4 are also reduced in proportion to 1 / α. At the same time, by setting all voltages to 1 / α, MOS
The potential distribution of each part of the FET is kept constant.

According to the above scaling rule, all voltages must be scaled down to 1 / α. However, in practice, this basic principle was not adhered to, and the power supply voltage of the miniaturized MOSFET was used at a constant power supply voltage before scaling. If the length (channel length) of the channel region 2 is made shorter and shorter with the drain voltage kept constant, the electric field in the channel naturally increases with the scaling factor. This is MOSF
Major problems when ET is operating in the saturation region, i.e., causing short channel effect. This is because, in the pinch-off state, the drain voltage, more precisely, V _D −V _Dsat is almost directly applied to the depletion layer between the pinch-off point and the drain region 4, so that a very large electric field peak appears near the drain region 4. . Generally, electrons that are accelerated by a large electric field and have higher energy than thermal energy are called hot electrons, and a large number of these hot electrons are generated near the drain region, which causes a problem.

[0005] First, impact ionization (impac
This is a phenomenon in which hot electrons collide with the silicon crystal of the silicon substrate 1 and an electron-hole pair is generated to break the bond, thereby causing an excess current to flow. This current is generated as a result of electrons being drawn into the drain region 4 and holes flowing into the substrate 1, and flows between the drain region 4 and the substrate 1. When this current increases, as shown in FIG. 12, a voltage effect occurs due to the resistance of the substrate 1 (effective resistance is expressed as “R _S ”), and the potential of the substrate 1 near the source region 3 increases. . In particular, when the substrate 1 is grounded, IR _sub > φ
_{When the} potential becomes _BI (diffusion potential), the source region 3 becomes forward biased, and a large amount of electrons are injected into the substrate 1. this is,
This is a kind of positive feedback phenomenon, and finally, the source region 3 and the drain region 4 become conductive, and a large amount of uncontrollable current flows, sometimes leading to destruction of the element.

Even if the current does not increase so far, light is generated by the impact ionization in the drain region 4, which generates an electron-hole pair at a PN junction of a nearby device and generates an extra current. This also causes the problem. The worst thing about hot electrons is that electrons with high energy are converted to silicon substrate 1-gate oxide film 5.
This is a phenomenon that gets over the barrier at the interface and enters the gate oxide film 5. This shifts the threshold value in the positive direction because some of the hot electrons are trapped in the gate oxide film 5 and become negative fixed charges. in this way,
When the threshold value shifts in the positive direction, the current gradually becomes difficult to flow while the circuit is operating, and the characteristics of the MOSFET change, thereby lowering the reliability of the IC. This is generally called a hot electron effect.

The short channel effect, specifically the hot electron effect, is caused by a high electric field in the vicinity of the drain region 4. Therefore, various devices for relaxing the electric field have been proposed. A typical example is a MOSFET having an LDD (lightly doped drain) structure (hereinafter, referred to as an “LDDMOSFET”).

FIG. 13 shows a schematic sectional structure of an LDDMOSFET. As shown in FIG. 13, the LDDMOSFET is formed by forming the drain region 4 with an N-type diffusion layer 4a and an N-type diffusion layer 4a so as to make the impurity distribution of the drain region 4 as gentle as possible.
N ⁻ type LDD diffusion layer 4, which is provided at the end of source type diffusion layer 4 a on the side of source region 3 and has a lower impurity concentration than N type diffusion layer 4 a
b. The source region 3 is also a N-type diffusion layer 3a, provided at four side end drain region of the N-type diffusion layer 3a, impurity concentration than the N-type diffusion layer 3a lower N ^-
And the diffusion layer 3b.

A method for manufacturing the above LDD MOSFET will be briefly described with reference to FIG. First, after a field oxide film 7 and a gate oxide film 5 are formed on a P-type silicon substrate 1, a gate 6 is formed on the gate oxide film 5. Next, P ⁺ is implanted and diffused at a low concentration using the gate 6 as a mask, and an N ⁻ -type diffusion layer 3b and an N ⁻ -type LDD diffusion layer 4b are formed with the channel region 2 interposed therebetween. Then, each forming a pair of side spacers 8,9 on both sides of the gate 6, As ⁺ gate 6 and a pair of side spacers 8,9 as a mask to inject diffused P ⁺ high concentration, N ^- -type diffusion layer N-type diffusion layers 3a and 4a are formed on both sides of the channel region 2 outside the gate 6 side end of the N ^- type LDD diffusion layer 4b and the N ^- type LDD diffusion layer 4b.

[0010]

The above-mentioned LDDMOSFE
In the case of T, the N ⁻ -type LDD diffusion layer 4b alleviates the high electric field near the drain region 4, so that the electric field of the depletion layer formed here does not need to be increased. For this reason, the avalanche phenomenon hardly occurs, and high-energy hot electrons hardly occur. Therefore, the hot electron effect can be prevented.

However, in the LDD MOSFET, the thickness of the gate oxide film 5 is reduced due to the aforementioned scale down. Therefore, as shown in FIG. 14, the relationship between the drain-substrate withstand voltage and the gate withstand voltage is such that as the voltage is increased, the drain-substrate withstand voltage X> gate withstand voltage Y, and the current flows to the gate 6 rather than the substrate 1 side. Easy to flow. That is, the electrostatic withstand voltage is low.

This LDDMOSFET is used not only for the internal element part of the IC but also for the input / output part (hereinafter referred to as "I / O (input / output) part") due to the manufacturing process of the IC. Normal. That is, in the I / O section, as shown in FIG. 15, the drain of the LDD MOSFET 10 is directly connected to the input / output pad 11, and when a surge voltage is applied to the input / output pad 11, the drain
Since the substrate withstand voltage> gate withstand voltage, the surge current flows through the N-type diffusion layer 4 as shown by the arrow in FIG.
a, flows to the gate 6 through the N ⁻ type LDD diffusion layer 4 b and the gate oxide film 5. Therefore, the lower gate oxide film 5 on the drain region 4 side of the gate 6 (A in FIG.
May be destroyed. Further, even if the gate oxide film 5 is not destroyed as indicated by A in FIG. 13, the charge is charged in the gate oxide film 5 and soft leak occurs.
Therefore, the internal elements may be adversely affected, and the reliability of the IC may be reduced.

[0013] The present invention has been made in view of the above, even if the thin gate insulating film due to miniaturization, and an object thereof is to provide a method for producing M OS transistor that can increase the electrostatic breakdown voltage.

[0014]

Means and action for solving the problem

[0015]

[0016]

[0017]

[0018]

According to a first aspect of the present invention, there is provided a method of manufacturing a MOS transistor, wherein the LDDMOS transistor is provided in the internal element portion.
Ingress and egress of internal elements in the integrated circuit used
MOS type transistors used for input / output
There, the channel region, and across the channel region
Semiconductor substrate having source and drain regions formed
And a source region and a channel region on the channel region of the semiconductor substrate.
With the drain region bridging, it is formed through the gate insulating film.
And a gate formed, wherein the length of the channel region is:
Longer than the channel length of the LDDMOSFET in the internal element
And at least the drain area of the gate
Gate insulating film in a predetermined region below the region-side end
Is predetermined at the end of the drain region on the source region side.
The gate insulating film in other areas so as to completely cover the
A method for manufacturing a MOS transistor provided with a greater thickness in parallel with the LDDMOS transistor in the internal element portion, wherein a gate insulating film and a gate are sequentially formed on a semiconductor substrate. Forming a pair of side spacers on the source region side and the drain region side of the gate after the LDD ions are implanted into the semiconductor substrate using the gate as a mask. Removing the spacer and the gate insulating film on the drain region side to expose the semiconductor substrate, forming the gate insulating film again on the semiconductor substrate exposed in the above step by thermal oxidation, and using the gate as a mask Forming a drain region and a source region in a self-aligned manner by ion implantation into a semiconductor substrate Than it is.

In the above manufacturing method, after a pair of side spacers for forming an LDD structure are formed by implanting LDD ions, at least the side spacers on the drain region side and the gate region are masked by isotropic etching. By removing the gate insulating film on the drain region side and exposing the semiconductor substrate, the etching proceeds not only in the vertical direction but also in the horizontal direction, and it is possible to remove the gate insulating film below the drain region side end of the gate. Therefore, in the re-gate thermal oxidation process, the gate oxide film in the predetermined region below the end of the gate on the drain region side can be easily formed thicker than the gate insulating film in the other region.

Further, the drain region can be easily formed while completely covering the predetermined region at the end of the drain region on the source region side with the thick gate insulating film of the predetermined region below the end portion of the gate on the drain region side. . That is, the mask alignment of the drain region can be easily and accurately performed. 3. The method for manufacturing a MOS transistor according to claim 2 , wherein the LDD MOS transistor has an internal element portion.
In the integrated circuit used for
MOS type transistor used for input / output unit that performs output
A is, across the channel region and the channel region,
Semiconductor substrate with source and drain regions formed by
Board and a source region and a channel region on a semiconductor substrate.
Through the gate insulating film while bridging the drain and drain regions.
A gate formed and a length of the channel region
Is based on the channel length of the LDD MOSFET in the internal element.
The source region is also provided with a source diffusion region.
A layer and an end of the source diffusion layer on the drain region side,
Consists of a diffusion layer with a lower impurity concentration than the source diffusion layer
It is, the drain region, a single impurity diffusion structure
Has a forming, under the drain region side end portion of the gate
The gate insulating film in the predetermined region in
Complete the predefined area at the source area side end of the area
Thicker than the gate insulating film in other areas to cover
A MOS transistor which is a method for manufacturing in parallel with LDDMOS transistor of the internal element, sequentially forming a gate insulating film and a gate on a semiconductor substrate, a gate as a mask, A step of forming a pair of side spacers on the source region side and the drain region side of the gate after injecting LDD ions into the semiconductor substrate, and a side spacer on the drain region side and a gate insulating film on the drain region side by isotropic etching Removing the semiconductor substrate, exposing the semiconductor substrate by thermal oxidation, forming a gate insulating film again on the semiconductor substrate exposed in the above step, and removing the semiconductor substrate using the side spacers on the gate and source region side as a mask. Forming a drain region and a source region in a self-aligned manner by ion implantation; Is Dressings.

In the above manufacturing method, LDD ions are implanted to form a pair of side spacers for obtaining an LDD structure, and isotropic etching is performed by isotropic etching using the side spacers on the gate and source regions as masks. Remove the side spacer and gate insulating film,
By exposing the semiconductor substrate, the gate insulating film below the edge of the gate on the drain region side is so-called side-etched.
The gate insulating film in the predetermined region below the end of the gate on the drain region side can be easily formed thicker than the gate insulating films in other regions.

Further, a thick gate insulating film of a predetermined region below the end of the gate on the drain region side can easily cover only the drain region while completely covering the predetermined region on the source region side end of the drain region. A single impurity diffusion structure can be used. That is, the mask alignment of the drain region having the single impurity diffusion structure can be easily and accurately performed.

According to a third aspect of the present invention, there is provided a method of manufacturing a MOS transistor, wherein the LDDMOS transistor is provided in the internal element portion.
Ingress and egress of internal elements in the integrated circuit used
MOS type transistors used for input / output
There, the channel region, and across the channel region
Semiconductor substrate having source and drain regions formed
And a source region and a channel region on the channel region of the semiconductor substrate.
With the drain region bridging, it is formed through the gate insulating film.
And a gate formed, wherein the length of the channel region is:
Longer than the channel length of the LDDMOSFET in the internal element
Ku is provided, the source and drain regions
Both are have a single impurity diffusion structure, the gate
Below both ends of the source and drain regions
The gate insulating film in a predetermined region in the source region
Drain region side edge and drain region source region
To completely cover the predetermined area at the area side end,
MO provided thicker than the gate insulating film in other regions
The S-type transistor, a method for manufacturing in parallel with LDDMOS transistor of the internal element,
A step of sequentially forming a gate insulating film and a gate on a semiconductor substrate, a step of implanting LDD ions into the semiconductor substrate using the gate as a mask, and forming a pair of side spacers on the source region side and the drain region side of the gate, and the like. A step of removing the pair of side spacers and the gate insulating film on the source region side and the drain region side by isotropic etching and exposing the semiconductor substrate, and performing a gate insulating process on the semiconductor substrate exposed in the above step by thermal oxidation. The method includes a step of forming a film and a step of forming a drain region and a source region in a self-aligned manner by ion implantation into a semiconductor substrate using a gate as a mask.

In the above manufacturing method, after a pair of side spacers for forming an LDD structure is formed by implanting LDD ions, a pair of side spacers and a source region side and a source region side are formed by isotropic etching using a gate as a mask. By removing the gate insulating film on the drain region side and exposing the semiconductor substrate, the gate insulating film below both ends of the source region side and the drain region side of the gate is side-etched. The gate insulating film in a predetermined region below both ends of the gate on the source region side and the drain region side can be easily formed thicker than the gate insulating films in other regions.

A thick gate insulating film of a predetermined region below both ends of the gate on the source region side and the drain region side, the predetermined region at the drain region side end of the source region and the predetermined region at the source region side end of the drain region , The source region and the drain region can easily have a single impurity diffusion structure. That is, the mask alignment of the source region and the drain region of the single impurity diffusion structure can be easily and accurately performed.

[0027]

1 to 7 show a first embodiment of the present invention.
It will be described in detail based on. FIG. 7 is a diagram schematically showing the configuration of an IC using the MOSFET according to the first embodiment of the present invention. Referring to FIG. 7, the MOSF according to the present embodiment will be described.
The configuration of the IC 20 using the ET will be described.

As shown in FIG. 7, in the IC 20, electronic circuits are formed at high density on one P-type silicon substrate 21 based on a predetermined integrated circuit design. That is, IC20
Has an internal element portion 22 including a CPU or the like formed at a central portion of a P-type silicon substrate 21.
Around the internal element portion 22 and peripheral circuits (not shown)
And a plurality of I / O units 23 that perform input and output between them. The internal element section 22 includes LDDMMOSFE.
T (not shown) is used, and the MOSFET 30 (see FIG. 1) according to the present embodiment is used for each I / O unit 23.

FIG. 1 shows a MOSF according to a first embodiment of the present invention.
It is a schematic sectional drawing which shows the structure of ET. The structure of the MOSFET 30 according to the present embodiment will be described with reference to FIG. The MOSFET 30 of the present embodiment is, as shown in FIG.
The device is isolated by a field oxide film 31 formed on the surface of the P-type silicon substrate 21, and a channel region 32 and a channel region 32 are formed on the surface layer of the silicon substrate 21 in a region separated by the field oxide film 31. N-type source region 33 and N-type drain region 34
Are formed. Then, the source region 33 and the drain region 3 are formed on the channel region 32 of the silicon substrate 21.
4 and the gate 3 via the gate oxide film 35.
6 are provided.

The P-type silicon substrate 21 has a specific resistance of 5-2.
A material having a relatively low impurity concentration of about 0 Ωcm is used. The field oxide film 31 is made of, for example, an insulating material such as SiO _{2 and} has a thickness of about 10,000
It is provided as thick as possible. Then, immediately below the field oxide film 31, to control the threshold of MOSFET 30, to prevent the field oxide film 31 parasitic channel below is formed, for example, a channel Suttopu ion concentration of B ^+, such as high A P-type impurity diffusion layer (hereinafter, referred to as a “channel stopper”) 37 is formed.

Length of channel region 32 (channel length)
Is the LDDMOSFE used in the internal element section 22.
It is set longer than the channel length of T. The N-type source region 33 has a structure in which the impurity distribution of the source region 33 is as gentle as possible. That is, the source region 33 is, for example As ^+, and N-type diffusion layer 33a that high N-type ion concentration of P ^+, etc., provided to protrude into the drain region 34 side end portion of the N-type diffusion layer 33a, for example, P ⁺ LDD ion concentration equal less than N-type diffusion layer 33a N ^-
And the diffusion layer 33b.

The N-type drain region 34 is made of, for example, As ⁺ ,
It has a single drain structure in which the concentration of N-type ions such as P ⁺ is increased. The gate oxide film 35 is made of, for example, SiO ₂
And the like, is provided with a thin film thickness of about 250 ° and is connected to the field oxide film 31. A gate oxide film 35c in a predetermined region below the end of the gate 36 on the drain region 34 side is formed.
Is about 35 to increase the electrostatic withstand voltage of the MOSFET 30.
It is provided approximately 0 ° thicker than the gate oxide film 35 in the other region, and is formed in the source region 33 of the drain region 34.
It completely covers the predetermined area at the side edge.

The gate 36 is made of, for example, a conductive material such as polysilicon whose resistance is reduced by doping phosphorus at a high concentration. At the end of the gate 36 on the source region 33 side, the source region 33 has an LDD structure. For this purpose, a side spacer 38 made of an insulating material such as SiO ₂ is attached. That is, the gate 36 is surrounded by an insulating film such as SiO ₂ .

Further, the entire surface of the silicon substrate 21 is made of PSG (phospho-silicate glass), which is P-doped SiO _2.
BPSG (boron-phospho-silicate gl) mixed with B
ass) or the like. Then, the interlayer insulating film 39 and the gate oxide film 35
, A source contact hole 40 is formed in a portion of the source region 33 corresponding to the N-type diffusion layer 33a, and a source electrode wiring 41 is formed through the source contact hole 40 so as to contact the N-type diffusion layer 33a. ing. Similarly, a drain contact hole 42 is formed in a portion corresponding to the drain region 34, and a drain electrode wiring 43 is formed so as to contact the drain region 34 through the drain contact hole 42. Further, a gate contact hole 44 is formed in a portion corresponding to the gate 36, and a gate electrode wiring 45 is formed through the gate contact hole 44 so as to contact the gate 36. Therefore, the source electrode wiring 41, the drain electrode wiring 43, and the gate electrode wiring 45 are insulated from each other by the interlayer insulating film 39.

Source electrode wiring 41, drain electrode wiring 4
3 and the gate electrode wiring 45 are made of a conductive material such as Al.
A passivation film 46 made of an insulating material such as PSG for protecting the surface of the OSFET 30 and preventing intrusion of contaminants from the outside is laminated on the entire surface of the silicon substrate 21.

In the above structure, the gate oxide film 35c in the predetermined region below the end of the gate 36 on the drain region 34 side is provided thicker than the gate oxide film 35 in the other region. Since the gate oxide film 35c thicker than 35 completely covers a predetermined region at the end of the drain region 34 on the source region 33 side, the relationship between the drain-substrate breakdown voltage and the gate breakdown voltage of the MOSFET 30 is shown in FIG. As shown. That is,
The relationship between the drain-substrate breakdown voltage and the gate breakdown voltage is such that even if the gate oxide film 35 is thinned by miniaturization, the drain-substrate breakdown voltage X <gate breakdown voltage Y is satisfied, and the current flows to the silicon substrate 21 side rather than the gate 36 side. It will be easier. That is,
The electrostatic breakdown voltage of the MOSFET 30 increases.

In the I / O section 23 of the IC 20, a MOS
The drain of the FET 30 is directly connected to an input / output pad (not shown). As described above, MOSFET 30 has a high electrostatic withstand voltage and a drain-substrate withstand voltage <gate withstand voltage. Therefore, when a surge voltage is applied to the input / output pad, a surge current flows from drain region 34 to substrate 21.
To the gate oxide film 35c on the end of the drain region 34.
Is hardly destroyed and the gate oxide film 35 is hardly charged with electric charge, so that soft leak hardly occurs. Therefore, the reliability of the IC 20 can be improved without adversely affecting the internal element section 22.

The drain region 3 of the MOSFET 30
4 has a single drain structure instead of an LDD structure because the channel length of the MOSFET 30 is
This is because the length is set longer than the channel length of the LDD MOSFET used in No. 2 and hot electrons need not be considered so much. 3A to 3D,
4 (a) to 4 (d), FIGS. 5 (a) to 5 (c) and FIG.
(A)-(c) is schematic sectional drawing which shows the manufacturing method of the said MOSFET in order of a process. 3 (a) to 3 (d), FIG.
(A)-(d), FIGS. 5 (a)-(c) and FIG. 6 (a)
A method of manufacturing the MOSFET 30 will be described with reference to FIGS. The MOSFET 30 is formed on the P-type silicon substrate 21 in parallel with the LDD MOSFET of the internal element section 22.

First, element isolation is performed. That is, FIG.
As shown in (a), the P-type silicon substrate 21 is about 900
Thermal oxidation at about 1000 ° C.
A pad oxide film 50 having a thickness of 00 ° is formed. Then, FIG.
As shown in (b), CVD (chemical vapor depositi)
on) silicon nitride (S)
i ₃ N ₄ ) Film 51 is laminated at about 1000 °. And S
A resist pattern 52 is formed on a predetermined region of the i ₃ N ₄ film 51. The resist pattern 52 is a pattern that defines a region where a transistor is to be formed.

Thereafter, as shown in FIG.
Using the pattern 52 as a mask,_ThreeN_FourOne of membrane 51
Etching part. In this etching, for example,
CF _Four/ O_TwoIt is preferable to use plasma etching
No. Next, using the same resist pattern 52 as a mask,
For example, B⁺Channel stop ion¹³cm
^-2About to inject. At this point, the registration
Since the strike pattern 52 is no longer used,_TwoPlasma processing
Ashing the resist pattern 52
I do.

Then, as shown in FIG. 3D, the silicon substrate 21 is oxidized in a steam (H ₂ O) atmosphere at about 1000 ° C. for about 6 to 7 hours, and is not covered with the Si ₃ N ₄ film 51. A field oxide film 31 of about 10000 ° is grown on the surface of a portion of the silicon substrate 21. Then, a P-type channel stopper 37 is formed immediately below field oxide film 31. Here, H ₂ O is used instead of dry oxygen because the oxidation rate is high and the oxidation time can be shortened.

When the above-described device isolation step is completed, gate oxidation and gate formation are performed. That is, as shown in FIG. 4A, the pad oxide film 50 and the Si ₃ N ₄ film 51 are removed by etching, and the surface of the silicon substrate 21 is exposed. Next, as shown in FIG.
1 is thermally oxidized at about 900 to 1000 ° C. to form a gate oxide film 53 of about 250 ° on the silicon substrate 21 exposed in FIG. At this time, both ends of the gate oxide film 53 are connected to the bird's beak of the field oxide film 31.
k). Then, polysilicon is deposited on the entire surface by the CVD method, and for example, P is added to the polysilicon. Thereafter, a resist pattern (not shown) is formed on a predetermined region of the polysilicon, and the polysilicon is etched using the resist pattern as a mask to form a gate 36. Since it is important to perform accurate etching according to a resist pattern for etching of polysilicon, it is preferable to use RIE (reactive ion etching).

When the gate oxidation step and the gate formation step are completed, ions are implanted. That is, FIG. 4 (c), the gate 36 as a mask, the silicon approximately to 10 ¹³ cm ^-2 to LDD ions such as P ⁺ substrate 21
Into the surface layer of Then, as shown in FIG. 4C, SiO ₂ is deposited on the entire surface by the CVD method, and the entire surface is etched back by RIE, thereby forming a pair on both sides (the source region 33 side and the drain region 34 side) of the gate 36. Are formed.

Thereafter, as shown in FIG. 5A, a resist 55 is applied to the entire surface and masked. And FIG.
As shown in FIG. 2B, the silicon substrate 21 is exposed by removing the resist 55 on the drain region 34 side, the side spacers 54 and the gate oxide film 53 by isotropic etching using HF. At this time, the etching proceeds isotropically in both the vertical and horizontal directions, and the gate oxide film 53 below the end of the gate 36 on the drain region 34 side also becomes
It is removed by so-called side etching. As a result, the gate 36 is placed on the remaining gate oxide film 53 in an overhang state protruding toward the drain region 34 side. At this point, since the resist 55 used as the mask is used up, ashing is performed by O ₂ plasma processing.

Then, as shown in FIG. 5C, the silicon substrate 21 is thermally oxidized again at about 900 to 1000 ° C. to form a gate oxide film 35 of about 250 ° on the silicon substrate 21. At this time, the drain region 3 in the gate 36
Since the polysilicon on the fourth side is also oxidized at the same time, the gate 3
The gate oxide film 35c in the predetermined region below the end of the drain region 34 on the side of No. 6 is formed to be about 350 ° thicker than the gate oxide film 35 in other regions. The gate 36 is surrounded by an insulating film. Thereafter, annealing is performed at about 900 ° C. Then, N ⁻ -type diffusion layer 33b and N ⁻ -type LDD diffusion layer 34b are joined to P-type silicon substrate 21 with channel region 32 interposed therebetween in a self-aligned manner.

Next, as shown in FIG.
6 and the side spacer 38 as a mask, for example, A
s ⁺ or the like is implanted into the silicon substrate 21 at about 6 × 10 ¹⁵ cm ^−2,
Is used as a mask, for example, P ⁺ is implanted into the silicon substrate 21 at about 6 × 10 ¹⁵ cm ⁻² . After the completion of the ion implantation, an interlayer insulating film is formed. That is, as shown in FIG. 6B, BPSG is deposited by the CVD method to form the interlayer insulating film 39. Then, reflow is performed to flatten the surface of the interlayer insulating film 39. After that, about 900-9
Anneal at 50 ° C. Then, in a self-consistent manner,
High concentration N-type diffusion layer 33a and N-type drain region 34
Are bonded to the P-type silicon substrate 21 with the channel region 32 interposed therebetween. That is, only the drain region 34 has a single drain structure. The predetermined region at the end of the drain region 34 on the source region 33 side is completely covered with the thick gate oxide film 35c in the predetermined region below the end of the gate 36 on the drain region 34 side.

When the above-described interlayer insulating film forming step is completed, a metallization and a pegation film are formed. That is, as shown in FIG. 6C, a resist (not shown) is applied to the entire surface for mask alignment, and a hole is formed in the resist only at an opening of the wiring. Then, using the resist as a mask, the interlayer insulating film 39 and the underlying gate oxide film 35 are removed by etching by RIE, and the contact holes 40, 42, 44 are respectively opened. Then, after removing the resist, for example, Al or the like is deposited on the entire surface by, for example, sputtering,
Using the mask alignment and RIE, each electrode wiring 41,
Patterns 43 and 45 are formed. Thereafter, for example, PSG is deposited on the entire surface by a CVD method to form a passivation film 46.

According to the above manufacturing method, FIG.
In the step (d), after forming a pair of side spacers 38 and 54 at both ends of the gate 36 for obtaining the LDD structure on the source region 33 side and the drain region 34 side, FIG.
In the step, using the gate 36 and the side spacer 38 on the source region 33 side as a mask, isotropic etching is performed.
By removing the side spacer 54 and the gate oxide film 53 on the drain region 34 side and exposing the silicon substrate 21, the gate oxide film 53 below the end of the gate 36 on the drain region 34 side can be side-etched. In the gate thermal oxidation step, the gate oxide film 35c in the predetermined region below the end of the gate 36 on the drain region 34 side can be easily formed thicker than the gate oxide film 35 in other regions (FIG. 5 ( c)).

A thick gate oxide film 3 of a predetermined region below the end of the gate 36 on the drain region 34 side.
5c, it is possible to easily form only the drain region 34 into a single drain structure while completely covering the predetermined region at the end of the drain region 34 on the source region 33 side (see FIG. 6B). That is, the mask alignment of the drain region 34 having the single drain structure can be easily and accurately performed.

Next, a second embodiment of the present invention will be described in detail with reference to FIGS. FIG. 8 is a schematic sectional view showing the structure of the MOSFET according to the second embodiment of the present invention. FIG.
The structure of the MOSFET 30 according to the present embodiment will be described with reference to FIG. The MOSFET 30 of this embodiment is the first
The difference from the embodiment is that the N-type source region 33 has a single source structure as shown in FIG.
The gate oxide film 35d in a predetermined region below the end of the source region 33 on the side of the source region 33 is provided at a thickness of about 350 ° thicker than the gate oxide film 35 in the other regions, and the source region 34 is formed by the thick gate oxide film 35d. Is completely covered. Other configurations, operations, and effects are the same as those of the first embodiment.

The source region 33 also has a single-source structure because the channel length of the MOSFET 30 is set longer than the channel length of the LDD MOSFET used in the internal element section 22 and hot electrons are taken into account. It is not necessary. FIG. 9 (a)-
(C) and FIGS. 10 (a) and 10 (b) are schematic sectional views showing a method of manufacturing the MOSFET in the order of steps. FIG. 9 (a)
A method of manufacturing the MOSFET 30 will be described with reference to FIGS. In addition,
3 (a) to 3 (d), FIGS. 4 (a) to 4 (d) and FIG.
The steps up to (a) are the same as in the first embodiment, and a description thereof will be omitted.

To obtain the LDD structure, side spacers 38 and 54 are formed at both ends of the gate 36, and after covering the entire surface with a resist 55 (see FIG. 5A), as shown in FIG. The pair of side spacers 38 and 54 and the gate oxide film 53 on the source region 33 side and the drain region 35 side are removed by isotropic etching using HF to expose the P-type silicon substrate 21. At this time, etching proceeds isotropically in both the vertical and horizontal directions, and the gate oxide film 53 below both ends of the gate 36 on the source region 33 side and the drain region 34 side is also removed.
As a result, the gate 36 is mounted on the remaining gate oxide film 53 in an overhang state protruding on both sides of the source region 33 and the drain region 34. Ashing is performed on the resist 60 used as the mask because it is now used up.

Then, as shown in FIG. 9B, the silicon substrate 21 is thermally oxidized again at about 900 to 1000 ° C. to form a gate oxide film 35 of about 250 ° on the silicon substrate 21. At this time, the source region 33 in the gate 36
Since the polysilicon on the side and the drain region 34 is also oxidized at the same time, the gate oxide film 35c in a predetermined region below the end of the gate 36 on the side of the source region 33 and the drain region 34 is reduced to about 350 ° Is formed thicker than the gate oxide film 35 of FIG. The gate 36 is surrounded by an insulating film. Thereafter, when annealing is performed, the N ⁻ -type LDD diffusion layer 3 is self-aligned.
3b and the N ⁻ -type LDD diffusion layer 34b are joined to the P-type silicon substrate 21 with the channel region 32 interposed therebetween.

The subsequent manufacturing steps are the same as those for manufacturing a normal MOSFET. In the source and drain formation step, as shown in FIG. 9C, for example, As ⁺ and P ⁺ are
Inject into In the interlayer insulating film forming step, as shown in FIG. 10A, after the BPSG is deposited to form the interlayer insulating film 39, reflow is performed to flatten the surface of the interlayer insulating film 39. After that, annealing is performed. Then, the N-type source region 33 and the N-type drain region 3 are self-aligned.
4 is the P-type silicon substrate 21 with the channel region 32 interposed therebetween.
To each other. That is, the source region 33 has a single source structure, and the drain region 34 has a single drain structure. The predetermined regions at the end of the source region 33 on the drain region 34 side and the end of the drain region 33 on the source region 33 side are the predetermined regions below the both ends of the gate 36 on the source region 33 side and the drain region 34 side. It is completely covered with the thick gate oxide films 35c and 35d.

In the step of forming a metallization film and a pedge film, as shown in FIG. 10B, contact holes 40, 42, and 44 are opened on the source region 33, the drain region 34, and the gate 36, respectively. The electrode wirings 41, 43 and 45 are formed by patterning. Thereafter, for example, PSG is deposited on the entire surface to form a passivation film 46.

According to the above-described manufacturing method, a pair of side spacers 38, 5 are provided at both ends of the gate 36 for obtaining the LDD structure on the source region 33 side and the drain region 34 side.
4 is formed, in the step of FIG. 9A, the source region 33 is formed by isotropic etching using the gate 36 as a mask.
By removing the gate oxide film 53 on the side of the drain region 34 and exposing the silicon substrate 21, the gate 36 is exposed.
The gate oxide film 53 below both ends of the source region 33 side and the drain region 34 side can be side-etched. Therefore, in the re-gate thermal oxidation step, both ends of the gate 36 on the source region 33 side and the drain region 34 side are removed. Gate oxide film 35 in predetermined region below
c and 35d can be easily formed thicker than the gate oxide film 35 in other regions (see FIG. 9B).

The thick gate oxide films 35c and 35d of predetermined regions below both ends of the gate 36 on the source region 33 side and the drain region 34 side are used to form the end of the source region 33 on the drain region 34 side and the drain region 34.
The source region 33 can easily have a single source structure and the drain region 34 can have a single drain structure while completely covering the predetermined region at the end of the source region 33 side (see FIG. 10A). That is, the mask alignment of the source region 33 having the single source structure and the drain region 34 having the single drain structure can be easily and accurately performed.

It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many changes or modifications can be made within the scope of the present invention. In the above embodiment,
Although an N-channel MOSFET has been described, the present invention may be applied to a P-channel MOSFET.

[0059]

【The invention's effect】

[0060]

According to the manufacturing method of the first aspect , in the re-gate thermal oxidation step, the gate oxide film in the predetermined region below the end of the gate on the drain region side is easily thicker than the gate insulating film in the other region. Can be formed.
Also, the masking of the drain region is easily and accurately performed by completely covering the predetermined region at the source region side end of the drain region with the thick gate insulating film in the predetermined region below the drain region side end. be able to.

According to the manufacturing method of the second aspect , in the re-gate thermal oxidation step, the gate insulating film in the predetermined region below the end of the gate on the drain region side is easily formed thicker than the gate insulating film in the other region. can do. In addition, the mask alignment of the drain region of the single impurity diffusion structure, which completely covers the predetermined region at the source region side end of the drain region with the thick gate insulating film in the predetermined region below the gate drain region side end. Can be easily and accurately performed.

According to a third aspect of the present invention, in the re-gate thermal oxidation step, the gate insulating film in a predetermined region below both ends of the gate on the source region side and the drain region side can be easily replaced with the gate insulating film in another region. It can be formed thicker. Further, the thick gate insulating film having a predetermined region below both ends of the gate on the source region side and the drain region side completely covers the predetermined region at the drain region side end of the source region and the source region side end of the drain region. Masking of the source region and the drain region of the single impurity diffusion structure to be covered can be easily and accurately performed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing the structure of a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a drain-substrate breakdown voltage and a gate breakdown voltage of a MOSFET.

FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a MOSFET in the order of steps.

FIG. 4 is a schematic cross-sectional view showing a method for manufacturing the MOSFET continued from FIG. 3 in the order of steps;

FIG. 5 is a schematic cross-sectional view showing a method of manufacturing the MOSFET continued from FIG. 4 in the order of steps;

FIG. 6 is a schematic cross-sectional view showing a method for manufacturing the MOSFET continued from FIG. 5 in the order of steps;

FIG. 7 is a diagram showing a simplified configuration of an IC using a MOSFET.

FIG. 8 is a schematic sectional view showing the structure of a MOSFET according to a second embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the MOSFET in the order of steps.

FIG. 10 is a schematic cross-sectional view showing the method of manufacturing the MOSFET continued from FIG. 9 in the order of steps;

FIG. 11 is a diagram showing a cross-sectional structure of the most basic MOSFET.

FIG. 12 is a diagram schematically showing a short channel effect of a MOSFET.

FIG. 13 is a schematic sectional view showing a structure of an LDD MOSFET.

FIG. 14 is a diagram showing a relationship between a drain-substrate breakdown voltage and a gate breakdown voltage of an LDDMOSFET.

FIG. 15 is an equivalent circuit diagram when an LDDMOSFET is used for an I / O unit of an IC.

[Explanation of symbols]

Reference Signs List 20 IC 21 P-type silicon substrate 22 Internal element part 23 I / O part 30 MOSFET 32 Channel region 33 N-type source region 33a N-type diffusion layer 33b N ^- type diffusion layer 34 N-type drain region 35, 53 Gate oxide film 35c Gate 35d Gate oxide film in a predetermined region below the end of the drain region on the side of the gate 35d Gate oxide film in a predetermined region below the end of the gate on the side of the source region 36 Gate 38, 54 Side spacer

Claims (3)

(57) [Claims] 1. An LDDMOS transistor comprising an internal element section
In the integrated circuit used for
MOS type transistor used for input / output unit that performs output
The channel region and the source region across the channel region.
A source region and a drain region on a semiconductor substrate on which a region and a drain region are formed, and on a channel region of the semiconductor substrate.
Formed through the gate insulating film while bridging the
And the length of the channel region is the LDDMOS of the internal element portion.
The length of the gate is longer than the channel length of the FET .
The gate insulating film in the predetermined region in
Completely covers the predetermined area at the source area side end
So that it is provided thicker than the gate insulating film in other areas
The MOS type transistor is replaced with the LDD of the internal element section.
A method for manufacturing in parallel with the MOS transistor, sequentially forming a gate insulating film and a gate on a semiconductor substrate, a gate as a mask, after implanting LDD ions into the semiconductor substrate, the gate and the source of Forming a pair of side spacers on the region side and the drain region side; removing at least the drain spacers on the drain region side and the gate insulating film on the drain region side by isotropic etching to expose the semiconductor substrate; A step of forming a gate insulating film again on the semiconductor substrate exposed in the above step by thermal oxidation, and a step of forming a drain region and a source region in a self-aligned manner by ion implantation into the semiconductor substrate using the gate as a mask A method for manufacturing a MOS transistor, comprising: 2. An LDDMOS type transistor comprising :
In the integrated circuit used for
MOS type transistor used for input / output unit that performs output
I der, source territory on both sides of the channel region and the channel region,
A source region and a drain region on a semiconductor substrate on which a region and a drain region are formed, and on a channel region of the semiconductor substrate.
Formed through the gate insulating film while bridging the
And the length of the channel region is the LDDMOS of the internal element portion.
The source region is longer than the channel length of the FET, and the source region includes a source diffusion layer and a drain of the source diffusion layer.
Provided at the end of the rain region side and thinner than the source diffusion layer
And a diffusion layer having an impurity concentration. The drain region has a single impurity diffusion structure.
Predetermined below the end of the gate on the drain region side.
The gate insulating film in the region to be
Make sure to completely cover the predetermined area on the side edge
MOS thicker than the gate insulating film in the region
LDD type transistors, a process for manufacturing in parallel with LDDMOS transistor of the internal element, sequentially forming a gate insulating film and a gate on a semiconductor substrate, a gate as a mask, the semiconductor substrate A step of forming a pair of side spacers on the source region side and the drain region side of the gate after the ion implantation, removing the side spacers on the drain region side and the gate insulating film on the drain region side by isotropic etching;
A step of exposing the semiconductor substrate, a step of forming a gate insulating film again on the semiconductor substrate exposed in the step by thermal oxidation, and an ion implantation into the semiconductor substrate using the side spacers on the gate and source region side as a mask, M including a step of forming a drain region and a source region in a self-aligned manner.
A method for manufacturing an OS transistor. 3. The LDDMOS transistor is an internal element part.
In the integrated circuit used for
MOS type transistor used for input / output unit that performs output
The channel region and the source region across the channel region.
A source region and a drain region on a semiconductor substrate on which a region and a drain region are formed, and on a channel region of the semiconductor substrate.
Formed through the gate insulating film while bridging the
And the length of the channel region is the LDDMOS of the internal element portion.
It provided longer than the channel length of the FET, both the source and drain regions, a single non
It has a pure substance diffusion structure, and has both ends of the gate on the source region side and the drain region side
The gate insulating film in the predetermined region below the
End of the drain region on the source region side and the source
Cover the predetermined area at the side edge of the source area.
As described above, the gate insulating film is thicker than other regions.
The MOS transistor is connected to the LDDM of the internal element section.
A method for manufacturing in parallel with OS-type transistor, sequentially forming a gate insulating film and a gate on a semiconductor substrate, a gate as a mask, after implanting LDD ions into the semiconductor substrate, the gate and the source of Forming a pair of side spacers on the region side and the drain region side, removing the pair of side spacers and the gate insulating film on the source region side and the drain region side by isotropic etching, exposing the semiconductor substrate, A step of forming a gate insulating film again on the semiconductor substrate exposed in the above step by thermal oxidation, and a step of forming a drain region and a source region in a self-aligned manner by ion implantation into the semiconductor substrate using the gate as a mask A method for manufacturing a MOS transistor, comprising: