JPS627710B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a gate protection device for an insulated gate field effect transistor, and more particularly to a method for manufacturing a protection device suitable for protecting the gate of a DSA transistor.

Even in planar type DSA transistors,
As with general MOS transistors, a gate protection device is required to prevent breakdown of the gate insulating film. In particular, when adopting a gate protection device for an integrated circuit device (IC) that includes planar DSA transistors, it is desirable to implement the IC without requiring any extra steps other than the process of manufacturing the DSA transistor. .

Therefore, the present invention does not require any extra manufacturing process in IC devices including DSA transistors.
An object of the present invention is to provide a method for manufacturing a gate protection device for a DSA transistor.

The present invention will be explained below with reference to the accompanying drawings.

FIG. 1A is a sectional view showing an example of the present invention,
B is its equivalent circuit diagram. In the figure, 10 is a well-known planar type DSA transistor, which serves as a protected transistor. The transistor 10
has a channel region 2 and a source region 3 obtained by double-diffusing P-type and N-type impurities on one main surface of a high resistivity N-type silicon semiconductor substrate 1, and further includes a channel region 2 and a source region 3 obtained by double-diffusing P-type and N-type impurities on one main surface of a high resistivity N-type silicon semiconductor substrate 1, and further includes a channel region 2 and a source region 3 obtained by doubly diffusing P-type and N-type impurities. It has a ring-shaped N-type drain region 4 surrounding the drain region at a predetermined interval. This drain region 4 is formed at the same time as the source region 3 is formed. Since the portion of the P-type region 2 along the substrate surface operates as a channel, which is a so-called inversion layer, a gate insulating film, that is, a silicon oxide film 5 of a predetermined thickness is formed thereon, and a gate electrode is further formed thereon. This is a structure in which G is deposited.

Here, in the double diffusion process of the channel region 2 and the source region 3, for example, the diffusion window for forming the former region 2 is used again as the diffusion window for the source region 3. Therefore, the portion of the P-type region 2 along the substrate surface has an impurity concentration distribution due to lateral diffusion of impurities. Therefore, this portion, that is, the channel portion, has a concentration distribution in which the concentration decreases as the distance from the source region 3 increases. Therefore, the operating channel of the DSA transistor is formed by an extremely short high concentration impurity layer, and since it operates in a short portion of substantially 1 μm or less, high speed and high density are possible.

20 is a gate protection device for the DSA transistor 10, and a pair of P-type regions 6 and 7 are formed in the N-type substrate 1 at the same time as the P-type region 2 of the transistor 10 is formed, and in this case, both regions are on the main surface of the substrate. Partially connect at . To do this, the diffusion holes 14 and 15 of the insulating film 13, which is an oxide film that serves as a mask for impurity diffusion, are formed close to each other so that the lateral diffusion of both is partially connected on the substrate surface between the holes. Make it. At the same time as forming the N-type region of transistor 10, N-type regions 8 and 9 are formed in both regions 6 and 7, respectively. In this case as well, it is preferable to use the aforementioned diffusion holes 14 and 15.

Therefore, the pair of N-type regions 8 and 9 are each P
The structure is such that it is in contact with the mold region 6 and 7 and is surrounded by these regions, and the P-type region 6 and 7
The concentration distribution along the main surface of the substrate utilizes lateral diffusion similar to the channel section of the DSA transistor, so it has a structure that decreases as it moves away from the center, and some of the channel sections are connected to each other. It fits.

In such a configuration, if the N-type region 8 is used as an input terminal together with the gate electrode G of the protected transistor 10, and the other N-type region 9 is connected to the source electrode S of the transistor 10, the equivalent structure shown in FIG. 1B can be obtained. If a circuit is obtained and the voltage applied to the input terminal IN is excessive, a punch-through phenomenon occurs in the NPN structure of the protection device 20, and conduction occurs between the N-type regions 8 and 9, causing the input voltage IN to be reduced to a predetermined value. It is possible to suppress the voltage.

In this case, it is clear that the distance between the pair of N-type regions 8 and 9 is significantly shorter than, for example, in a conventional gate protection MOS structure, so there is an advantage that the protection voltage can be lowered.

FIG. 2A is a sectional view showing another example of the present invention, and B is an equivalent circuit diagram thereof, in which parts equivalent to those in FIG. 1 are designated by the same reference numerals. To explain the different parts in the figure from FIG. 1, an insulating film 11 of a predetermined thickness is formed on the connecting portion of the substrate surface of the P-type regions 6 and 7, that is, on the substrate surface between the openings 14 and 15, and then Furthermore, a gate electrode 12 common to the contact electrode of the N-type region 8 is formed. The other parts are completely the same as in the case of FIG. 1, and therefore their explanation will be omitted.

In such a configuration, a pair of N-type regions 8 and 9
act as a source and drain region, respectively, and a connection portion between the P-type regions 6 and 7 acts as a channel portion.
Therefore, this transistor 20 has a threshold voltage V _TH determined by the thickness of the gate film 11, etc. Therefore, it is possible to appropriately select this V _TH to protect the gate of transistor 10.

As detailed above, according to the present invention, the gate protection device of the DSA transistor can be manufactured in the same process as the process of manufacturing the DSA element.
This is extremely advantageous when the device is integrated into an IC, and since the area occupied by the protection device 20 is smaller than that of the conventional device, it is possible to increase the density.

In addition, in the above example, the N channel
Although an N-type semiconductor substrate is used in the case of the DSA transistor, it goes without saying that a P-type semiconductor substrate may be used, and furthermore, it may be applied to a P-channel DSA transistor. In these cases, when using a substrate of the opposite conductivity type to the source and drain regions, it is possible to use the conventional gate protection device as is, but the DSA type protection device as in the present invention is The advantage of using this device is that the protection voltage can be lowered. Therefore, it goes without saying that the device of the present invention can also be used to protect the gates of general MOS transistors. Moreover, although one N-type region 9 of the protection device 20 is connected to the source electrode of the protected transistor, it may be connected to a reference potential point of the circuit, for example, a ground potential point.

[Brief explanation of the drawing]

FIG. 1A is a sectional view showing one example of the present invention, B is an equivalent circuit diagram thereof, FIG. 2A is a sectional view showing another example of the present invention, and FIG. 2B is an equivalent circuit diagram thereof. Explanation of symbols of main parts, 1...Semiconductor substrate,
2, 6, 7...P type impurity region, 3, 4, 8, 9
... N-type impurity region, 10 ... transistor to be protected, 11 ... insulating film.

Claims (1)

[Claims] 1. Gate protection for an insulated gate field effect transistor having a channel region and a source region obtained by double-diffusing impurities of first and second conductivity types into a semiconductor substrate of a predetermined conductivity type. A method of manufacturing a semiconductor device, the method comprising: forming an insulating film having at least two openings on one main surface of the semiconductor substrate; and introducing an impurity into the substrate through each of the openings; forming first and second impurity regions of a first conductivity type connected to each other directly under the insulating film between the openings at the same time as the channel region; by introducing impurities into the third conductivity type of the second conductivity type.
and a step of forming a fourth impurity region simultaneously with the source region, and a step of connecting the third region to the gate electrode of the field effect transistor and connecting the fourth region to the source electrode of the field effect transistor. A method for manufacturing a semiconductor device for gate protection, comprising the steps of: 2. A method for manufacturing a semiconductor device for gate protection of an insulated gate field effect transistor having a channel region and a source region obtained by double diffusing impurities of a first and second conductivity type into a semiconductor substrate of a predetermined conductivity type. forming an insulating film having at least two openings on one main surface of the semiconductor substrate; and introducing an impurity into the substrate through each of the openings to form an insulating film between the openings. simultaneously forming first and second impurity regions of a first conductivity type connected to each other immediately below the channel region; and introducing impurities into the first and second regions through each of the openings. The third conductivity type
and forming a fourth impurity region simultaneously with the source region, forming an electrode on the insulating film between the openings, and forming the third region and the electrode into the gate electrode of the field effect transistor. and connecting the fourth region to a source electrode of the field effect transistor.