JPH0235778A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the protecting effect by providing a stopper diffused layer adjacent to drain and source diffused layers of a MOS transistor in a peripheral circuit such that a part of the stopper diffused layer intersecting a gate electrode has a dopant concentration lower than that of the other part of the stopper diffused layer not intersecting the gate electrode. CONSTITUTION:An insulating film 102 for isolating elements is formed of a P-type substrate 101. A stopper diffused layer 103 is formed by implanting boron ions before oxidation. After formation of a gate oxide film 104 and a gate electrode 105 of polycrystalline Si, an N-type high concentration diffused layer 106 for providing a drain diffused layer is formed by implantation of As ions. Further, an N-type low concentration diffused layer 108 also for providing the drain diffused layer is formed by implantation of P ions. N-type high concentration diffused layer 107 and low concentration diffused layer 109 constituting a source diffused layer are formed simultaneously therewith. A part of the stopper diffused layer 201 where a gate electrode is formed has a concentration lower than that of the other part of the stopper diffused layer 103 in the region other than the gate electrode. In this manner, static dielectric strength at an intersection between the gate electrode and the stopper diffused layer can be increased.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides at least MO
an internal circuit including an S-type transistor, and a peripheral circuit structure for protecting the internal circuit against external surge input such as excessive static electricity, which also includes at least a MOS transistor; In particular, it relates to a MOS type transistor structure of a peripheral circuit.

[Summary of the Invention] The present invention provides that, of the stopper diffusion layer in contact with the drain diffusion layer of a MOS transistor in a peripheral circuit, the stopper diffusion layer in the portion other than the portion intersecting the gate electrode is By increasing the concentration of at least a portion of the stopper diffusion layer, the protection effect against external surge input such as static electricity is increased.

[Prior Art] Conventionally, as protection against external surge input such as static electricity, between the bonding pad part and the internal circuit,
A protection circuit was constructed by combining various types of resistors such as diffused resistors and POLY-3i resistors, diodes, and transistors.

[Problem to be solved by the invention] In recent years, transistors have been miniaturized, and as a WM of transistors, as a countermeasure against hot carriers, for example, the drain diffusion layer is made of a high concentration diffusion layer of arsenic and a low concentration diffusion layer of phosphorus. L DD (Lightl
The doped drain structure and the double diffusion structure, which utilizes the difference in the diffusion coefficients of arsenic and phosphorus to provide a low concentration region, are being actively adopted starting from transistor channel lengths of 2 μm or less. As transistors become increasingly miniaturized and drain structures with low-concentration regions become available, this combined with the decrease in channel length significantly weakens the breakdown strength of the transistor itself against surge input. Conventional technology no longer provides sufficient protection against surge input.Especially for output terminals where the drain of a transistor is directly connected to a bonding pad, the surge resistance of the transistor itself becomes the surge resistance of the output terminal. However, there is a problem in that the surge resistance of the transistor is greatly affected by the miniaturization of the transistor.Therefore, the present invention is intended to solve this problem, and its purpose is to miniaturize the transistor. The object of the present invention is to provide a semiconductor device that has a sufficient protective effect even when exposed to light.

[Means for Solving the Problems] In the semiconductor device of the present invention, among the stopper diffusion layers in contact with the drain diffusion layer of the MO3 type transistor in the peripheral circuit, the stopper diffusion layer in the portion intersecting with the gate electrode,
It is characterized by increasing the concentration of at least a portion of the stopper diffusion layer in a portion other than the portion intersecting the gate electrode.

[Embodiment] FIG. 1 is a main sectional view of an embodiment of the semiconductor device of the present invention, and FIG. 2 is a main plan view of an embodiment of the semiconductor device of the present invention. The semiconductor device of the present invention will be described below with reference to FIGS. 1 and 2.

Here, an N-channel transistor with double diffusion iv[ will be described.

, 11111 are P-type 31 substrates, and for example, a substrate with a resistivity of 10Ω·α is used. Reference numeral 102 denotes an insulating film for element isolation, which is formed using, for example, the LOOOS method. 106 is a stopper diffusion layer for preventing parasitic channels;
It is formed by implanting 13crn-2 ions into the substrate.

Reference numeral 104 is a gate v film, and reference numeral 105 is a gate electrode, for example, poly S1. 106 is an N-type high concentration diffusion layer constituting the drain diffusion layer, for example, arsenic is 5E1
It is formed by implanting 5crn-2 ions. 10
Similarly, 8 is an N-type low concentration diffusion layer constituting the drain diffusion layer, and is formed by, for example, implanting phosphorus IFi14cy++-2 ions. 107 and 109 are an N-type high concentration diffusion layer and a low concentration diffusion layer forming a source diffusion layer, and are formed at the same time as 106 and 108. Here, the stopper diffusion layer 103 and the drain diffusion layers 106 to 108 are in contact with each other.

In FIG. 2, reference numeral 201 is a stopper diffusion layer where the gate electrode is formed, and according to the spirit of the present invention, the concentration is lower than that of the diffusion layer 103 other than the gate electrode portion.

Now, considering the drain breakdown voltage of a MoS transistor,
When the stopper diffusion layers are formed with the same concentration, the lowest breakdown voltage is at 202 (the intersection of the gate electrode and the stopper diffusion layer) shown in FIG. When static electricity is applied to such a transistor, the static electricity is concentrated and discharged where the withstand voltage is the lowest, so it is concentrated at the portion 202, and a sufficient static electricity withstand voltage cannot be obtained. Actually in this case,
Under the conditions of 200pF and QΩ, the static air pressure is 150V.
Met. Like the MOS transistor of the present invention 103
The concentration of the stopper expansion @ layer other than the gate part was increased (ion implantation dose: 2E14crn-2), and the breakdown voltage of that part (
By lowering the withstand voltage (~10V) from the withstand voltage (15V) of 202, the same voltage (200pF, 0Ω, 300V) can be obtained.
An electrical breakdown voltage of # was obtained.

FIG. 6 is a plan view showing a second embodiment of the invention. The purpose of the present invention is to lower the breakdown voltage of other parts than the breakdown voltage of the part where the gate and stopper diffusion layer intersect.
As shown in the figure, the end of the gate 'r&pole may rest on a stopper diffusion layer provided according to the spirit of the present invention in 103. In addition, on the source side, 50 nm is applied to the gate electrode.
5 stopper diffusion layers may be formed.

FIG. 4 shows a third embodiment of the present invention. The stock τ concentration is lowered not only in the stopper diffusion layer of the gate portion but also in the corner portion 40i of the drain diffusion layer than in other portions. By doing so, there is no drop in breakdown voltage at the corners, and further improvement in electrostatic breakdown voltage can be expected.

In the above description, an N-channel transistor having a double diffusion structure has been described, but it goes without saying that the present invention can also be applied to an LDDI structure, a single structure drain diffusion layer, or a P-channel transistor.

[Effects of the Invention] As described above, according to the semiconductor device of the present invention, the stopper diffusion layer in the portion intersecting with the gate electrode of the stopper diffusion layer in contact with the drain expansion 1&/θ of the MO3 type transistor in the peripheral circuit By making the concentration of at least a portion of the stopper diffusion layer higher than that of the diffusion layer in the portions other than those intersecting the gate electrode, it is possible to increase the protection effect against external surge input such as static electricity.

[Brief explanation of the drawing]

FIG. 1 is a main sectional view showing one embodiment of the present invention. FIG. 2, FIG. 3, and FIG. 4 are main plan views showing one embodiment of the present invention. 101...P-type S1 substrate 102...
...Element isolation film 103, 201, 302, 501, 401...
...... Stopper diffusion layer 104 ...... Gate metal film 105.50
'5...Gate electrode 106.107...
...High concentration diffusion layer 1 [13, 109...Low concentration diffusion layer 202...Gate electrode and stopper diffusion layer) Intersection part 1 paper 2 tomoe

Claims (2)

[Claims] (1) In a semiconductor device formed on a semiconductor substrate and comprising an internal circuit including at least a MOS transistor and a peripheral circuit including at least a MOS transistor, the MOS transistor of the peripheral circuit A semiconductor device characterized in that the concentration of the stopper diffusion layer in other parts of the stopper diffusion layer in contact with the drain diffusion layer is higher than the concentration of the stopper diffusion layer in the part intersecting with the gate electrode. (2) In a semiconductor device formed on a semiconductor substrate and comprising an internal circuit including at least a MOS transistor and a peripheral circuit including at least a MOS transistor, the MOS transistor of the peripheral circuit Among the stopper diffusion layers in contact with the drain diffusion layer, the concentration of the stopper diffusion layer in other parts is higher than that in the part intersecting the gate electrode and the corner of the drain. Semiconductor equipment.