JPH02283070A - Semiconductor integrated circuit device using input protecting circuit - Google Patents

Abstract

PURPOSE:To reduce the size and cost of a chip by forming a current limiting resistor layer and a resistor protecting diode on a sole isolating insular region under an input terminal pad. CONSTITUTION:This semiconductor structure is formed with a current limiting resistor R and a resistor protecting diode D2 in a low concentration N-type isolating insular region 3a formed by dividing an epitaxially grown layer on a P-type semiconductor substrate 1 by P-type isolation regions 4a, 4b. The diode D2 has the region 4a as an anode region and the region 3a as a cathode region. Thus, since the resistor R and the diode D2 are formed in the region 3a and the region 4a for forming it, a chip size can be reduced by densifying the formation of elements of an input protecting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device equipped with an input protection circuit to prevent gate dielectric breakdown of an insulated gate field effect transistor, and in particular, to Concerning semiconductor structures.

[Conventional technology]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit device including an insulated gate field effect transistor is known to have an input protection circuit as shown in FIG. In Fig. 4, M is an insulated gate field effect transistor, and its gate G and ground (G
A gate voltage limiting diode D1 is connected between the gate ND and the gate voltage limiting diode D1, and the gate voltage limiting diode D1 is connected to the input terminal IN via a current limiting resistor R. Furthermore, a resistance protection diode D2 is connected between the input terminal IN and ground.

Note that D3 is a parasitic diode to which a power supply voltage VCC for preventing conduction is applied.

The breakdown voltage of the gate voltage limiting diode DI is set lower than the gate oxide film breakdown voltage of the insulated gate field effect transistor M.

When a surge with positive polarity and a high withstand voltage higher than the gate oxide film breakdown voltage is applied to the input terminal IN, breakdown of the gate voltage limiting diode DI occurs, and the current flows through the current limiting resistor R and the agate voltage limiting diode D2. flows into ground (GND) through the gate G, thereby protecting the gate G from dielectric breakdown. On the other hand, when a negative polarity surge is applied to the input terminal IN, current flows from the ground side to the input terminal IN via the resistance protection diode D2, which prevents destruction of the current limiting resistor R due to excessive current. .

By the way, the current limiting resistor R and the resistance protection diode D2 in the broken line in the fourth diagram in the input protection circuit described above have a semiconductor structure as shown in FIG. In Figure 5, 1 is p
type semiconductor substrate, on which a high concentration n-type buried layer 2a,
2b is formed. 3a and 3b are p-type semiconductor substrates l
This is an isolation island region in which the upper low concentration n-type epitaxial growth layer is defined by p-type isolation regions 4a, 4b, and 4c. An input terminal pad 5 is in conductive contact with a high 1 degree n-type cathode contact region 5a which is diffused and formed on the isolation island region 3a. A grounded anode electrode wiring 6 is provided on the p-type isolation region 4a that partitions the isolation island region 3a and is in conductive contact with the p-type anode contact region 6a. The p-type isolating region 4a and the p-type isolation island region 3a constitute a resistance protection diode D2. On the other hand, a p-type diffused resistance layer 7 as a current limiting resistor R is formed in the isolation island region 3b adjacent to the isolation island region 3a. One end of this p-type diffused resistance layer 7 is connected to the input terminal pad 5 on the isolation island region 3a via a connection wire 7a, and the other end is connected to another isolation island region (not shown) via a connection wire 7b. ) is connected to the gate G of the field effect transistor M.

The p-type diffused resistance layer 7 and the n-type isolation island region 3b constitute a parasitic diode D3, but in order to disable the parasitic diode, the high concentration n-type contact region 8 of the isolation island region 3b is connected to the power supply voltage. V. C is applied. ↓, 9 is a silicon oxide film, and 10 is a surface protection film.

[Problem to be solved by the invention]

However, in the semiconductor structure of the input protection circuit described above, the current limiting resistor R is formed as a p-type diffused resistance layer 7 in the isolation island region 3b, and the resistance protection diode D2 is formed in another isolation island region 3a and Since the protective elements are formed in different isolation island areas, the area occupied by the elements becomes large, leading to an increase in the chip size.

Therefore, an object of the present invention is to provide a semiconductor device equipped with an input protection circuit that achieves miniaturization of the element occupied area by incorporating both the current limiting resistor and the resistance protection diode of the input protection circuit in a single isolation island region. An object of the present invention is to provide an integrated circuit device.

[Means to solve the problem]

In order to solve the above-mentioned problems, the measures taken by the present invention are to form a current limiting resistance layer adjacent to the contact region and of the opposite conductivity type in the isolated island region in which the contact region of the resistance protection diode is formed. However, an input terminal pad is provided on the isolation island region to make conductive contact with the contact region and a part of the current limiting resistance layer.

[Effect]

According to this means, since the current limiting resistance layer and the resistance protection diode are formed in a single isolation island region under the input terminal pad, one isolation island region can be saved compared to the conventional method. , it is possible to reduce chip size and cost.

〔Example〕

Next, one embodiment of the present invention will be described based on the accompanying drawings.

FIG. 1 is a circuit configuration diagram showing an input protection circuit in one embodiment of the present invention. In the figure, M is an insulated gate field effect transistor, Dl is a gate voltage limiting diode connected between its gate G and ground, and R is a gate G and input terminal I.
A current limiting resistor connected between N and D2 is a resistance protection diode connected between the input terminal and ground.

Figure 2 is a plan view of the semiconductor structure related to the input protection circuit.
FIG. 3 is a cross-sectional view taken along line 11-117 in FIG. 2.

In this semiconductor structure, an epitaxial growth layer on a p-type semiconductor substrate 1 is formed into p-type isolation regions 4a, 4.
A current limiting resistor R and a resistance protection diode D2 are built into the low concentration n-type isolation island region 3a divided by b. The resistance protection diode D2 has the p-type isolation region 4a as an anode region and the n-type isolation island region 3a as a cathode region. P-type anode contact region 6a on isolation region 4a
A grounded anode electrode wiring 6 is in conductive contact with the electrode. A highly doped n-type cathode contact region 12 is formed in the isolation island region 3a having a highly doped n-type buried layer 2a at the bottom, and this contact region 12 is connected to the input terminal pad 13.
It is in conductive contact with a part of the overhanging portion 13a. Further, an n-type diffused resistance layer 14 adjacent to the cathode contact region 12 is formed in the isolation island region 3a. A portion of the n-type diffused resistance layer 14 on the contact region 12 side is in conductive contact with the protruding portion 13a of the input terminal pad 13, and a portion on the opposite side is in contact with the connection wiring 7a conductive to G). .

Next, a method for manufacturing the above semiconductor structure will be described. First, a highly doped n-type buried layer 2a is formed on a p-type semiconductor substrate 1, a lightly doped n-type epitaxial layer is grown on top of the buried layer 2a, and a p-type buried layer 2a is formed on the p-type semiconductor substrate 1. Mold isolation regions 4a and 4b are formed to define isolation island regions 3a. Next, after the anode contact region 6a and the n-type diffused resistance layer 14 are simultaneously formed by n-type diffusion, the cathode contact region 12 is formed in the region adjacent to the n-type diffused resistance layer 14 by high-concentration n-type diffusion.

After that, a contact hole is formed in the silicon oxide film 9, and an anode bridge wiring 6. is formed by aluminum evaporation and etching. Input terminal pad 13 and connection wiring 7b are formed at the same time, and a surface protective film IO is deposited thereon. In this manufacturing process, the n-type diffusion of the anode contact region 6a and the n-type diffused resistance layer 14 can be used as the base diffusion of the bipolar part and the source ring and drain diffusion of the p-channel insulated gate field effect transistor in the CMO3 part, and its surface concentration is 10"-10"am-'. Further, the n-type diffusion in the cathode contact region 12 can be used for the emitter expansion of the bipolar part and the source and drain diffusion of the N-channel insulated gate field effect transistor in the CMO 5 part. Therefore, the current limiting resistor R and the resistance protection diode D2 can be fabricated without adding any process steps.

In this way, since the current limiting resistor R and the resistance protection diode D2 are built into the single isolation island region 3a and the isolation region 4a that defines this, the chip A reduction in size is achieved. Conventional input protection circuits require a layout area of approximately 0.2 mm2 per terminal, but according to this embodiment, the layout area per terminal is approximately half that, 0.2 mm2. lnu++' will suffice.

For example, the total area of the input protection circuit in a semiconductor integrated circuit device having 20 input terminals conventionally required 4×2, but in this embodiment, it is reduced to about 2×2, and the reduction effect is 10×2 of the total chip area. It reaches ~30%, which is effective for cost reduction.

〔Effect of the invention〕

As explained above, a semiconductor integrated circuit device equipped with an input protection circuit according to the present invention has a contact region of a resistance protection diode and a current limiting resistor of an opposite conductivity type adjacent thereto in a single isolated island region. The present invention is characterized in that a layer is formed and an input terminal pad is provided in conductive contact with a contact region and a part of the current limiting resistance layer, so that the following effects are achieved.

That is, since the two elements of the input protection circuit are densely integrated within a single isolation island region, the occupied area can be reduced, and the chip size and cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an input protection circuit in one embodiment of the present invention. FIG. 2 is a plan view of a semiconductor structure related to the input protection circuit. FIG. 3 is a cutaway view showing a state cut along the line lI[-[[ in FIG. FIG. 4 is a circuit configuration diagram showing an example of a conventional input protection circuit. FIG. 5 is a sectional view showing the semiconductor structure of the conventional example. M insulated gate field effect transistor, Di agate pressure limiting diode, R current limiting resistor, D2 resistance protection diode, l p-type semiconductor substrate, 2a high concentration n-type buried layer, 3a low concentration n-type isolation island region, 4 a , d b
p-type iso-rayon region, 6 anode electrode wiring, 7b connection wiring, 9 silicon oxide film, 10 surface protection film, 12 high concentration n-type cathode contact region, 13 input terminal pad, 13a overhang, 14
p-type diffused resistance layer. ND Diagram

Claims (1)

[Claims] 1) A gate voltage limiting diode connected between the gate of the insulated gate field effect transistor and ground, a current limiting resistive layer connected between the gate and the input terminal pad, and a conductive layer connected to the input terminal pad. In a semiconductor integrated circuit device equipped with an input protection circuit including an isolation island region to which a contact region that comes into contact belongs and a resistance protection diode configured with an isolation region that partitions the isolation island region, the current limiting resistance layer is connected to the input terminal pad. an input protection circuit, the input protection circuit being adjacent to the contact region in the lower isolation island region, being in partial conductive contact with the input terminal pad, and formed as a layer of a conductivity type opposite to that of the contact region; A semiconductor integrated circuit device equipped with