JPH01243586A - Semiconductor device - Google Patents

Abstract

PURPOSE:To effectively prevent an integrated circuit from being rendered to electrostatic breakdown of an integrated circuit by making a diffusion layer formed in a silicon substrate smaller than that of a well. CONSTITUTION:Element isolation regions 3a, 3b, 3c comprising SiO2 are formed on the surface of a p type silicon single crystal silicon substrate 2 spread away in a predetermined interval, and high concentration diffusion layers 4a, 4b are formed among those isolation regions, between which the central element isolation region 3c is placed. High concentration diffusion layers 4a, 4b are connected to Al wirings 7a, 7b through a contact hole 6. n<-> Type low concentration diffusion layers 8a, 8b and formed around the high concentration diffusion layers 4a, 4b in the silicon substrate 2. Once high voltage electrostatic noise is applied to an input terminal 10, voltage is applied to an electrostatic breakdown preventing protective element 1 through the Al wiring 7a to permit a depletion layer extending into the silicon substrate 2 from the low concentration diffusion layer 8a to reach the low concentration diffusion layer 8b and blow into a power supply 11 through the Al wiring 7b for prevention of electrostatic breakdown of an internal integrated circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to prevent electrostatic damage in MO3 type semiconductor devices.

[Conventional technology]

Regarding the well structure of CMO3 type semiconductor devices, see, for example, Science Forum Co., Ltd., November 2, 1982.
Published on the 8th, "Ultra LSI Device Handbook" P50~
There is a description on page 51.

CMO3 type semiconductor devices have an electrostatic damage prevention method that utilizes a punch-through between wells between the input terminal (or output terminal) and the integrated circuit in order to prevent damage to the integrated circuit due to external electrostatic noise. A device equipped with a protective element for protection is known.

The structure of the above protection element for preventing electrostatic damage is that a pair of wells of the same conductivity type are formed facing each other in an active region surrounded by an element isolation region, and a voltage higher than the power supply voltage is applied to the input terminal (output terminal). When electrostatic noise is applied, punch-through occurs between the wells and current flows, preventing electrostatic damage to the internal integrated circuit.

[Problem to be solved by the invention]

However, the protection element for preventing electrostatic damage of the CMO3 type semiconductor device using punch-through between wells has
It has the following drawbacks.

In other words, the depth of a well formed in a silicon substrate is usually about 2 to 10 μm, and the lateral diffusion of impurities injected into the substrate when forming the well is also large. The volume occupied by the well becomes large, and as a result, high integration of semiconductor devices is hindered.

Furthermore, since the process for forming wells in MO3 type semiconductor devices is limited to CMO3 type semiconductor devices, it cannot be applied to MO3 type semiconductor devices consisting only of p-channel type elements or n-channel type elements that do not form wells. Can not.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can miniaturize a protective element for preventing electrostatic damage.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a protective element for preventing electrostatic discharge damage consisting of a pair of high concentration diffusion layers formed facing each other at a predetermined distance in a silicon substrate and a low concentration diffusion layer formed around them is attached to the silicon substrate. This is a semiconductor device in which a protective element for preventing electrostatic damage is connected between an integrated circuit and an input or output terminal, which are formed with different conductivity types.

[Effect]

According to the above means, since the volume of the diffusion layer formed in the silicon substrate is smaller than the volume of the well, miniaturization of the protection element for preventing electrostatic damage is achieved.

〔Example〕

FIG. 1 is a sectional view of a main part of a silicon substrate showing a protection element for preventing electrostatic damage in a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows the arrangement of this protection element for preventing electrostatic damage. It is a circuit diagram.

The structure of the electrostatic breakdown prevention protection element 1 formed in a part of an MO3 type semiconductor integrated circuit will be described below.

As shown in FIG. 1, the surface of a silicon substrate 20 made of p-type silicon single crystal with a predetermined impurity concentration
An element isolation region 3a consisting of n.

3b and 3c are formed at a predetermined interval, and high concentration diffusion layers 4a and 4b are formed in the active regions on both sides of the central element isolation region 3c, respectively.

The high concentration diffusion layers 4a and 4b are of a conductivity type different from that of the silicon substrate 2, that is, are n'' type diffusion layers, for example,
Impurities such as arsenic (As) are diffused at a high concentration of 1020/cl'' or higher.

The high concentration diffusion layers 4a and 4b are made of phosphosilicate glass (PS
It is connected to AJ wirings 7a and 7b through a contact hole 6 formed in a part of an insulating film 5 made of G) or the like.

On the other hand, inside the silicon substrate 2, a high concentration diffusion layer 4
Around the layers a and 4b, n-type low concentration diffusion layers 3a and 3b in which impurities such as phosphorus (P) are diffused at a low concentration are formed.

The low concentration diffusion layers 3a and 3b are both element isolation regions 3a.
, 3b, 3c, and below the central element isolation region 3C, one low concentration diffusion layer 8a and the other low concentration diffusion layer 8b are separated by a predetermined distance.

In the protection element 1 for preventing electrostatic discharge damage having the above structure, for example, the formation of the low concentration diffusion layers 3a and 3b is performed at the same time as the formation of the channel stopper region in the silicon substrate 2.

The formation of the high concentration diffusion layers 4a and -4b includes an impurity ion implantation process and a heat treatment process for forming the source and drain regions, and also the element isolation region 3a.

3b and 3c are formed using a field oxide film forming process using the LOCO3 method, respectively.

Therefore, the protection element 1 for preventing electrostatic damage can be produced without increasing the manufacturing process of MO3 type semiconductor integrated circuits.

Next, the function of the protection element 10 for preventing electrostatic damage will be explained.

As shown in FIG. 2, the protection element 1 for preventing electrostatic damage has an Al wiring 7a between an internal integrated circuit 9 to be protected from electrostatic damage and an input terminal (or output terminal, the same applies hereinafter) 10. and the other AIl wiring 7b is connected to the power supply 11.
It is connected to the.

Therefore, when electrostatic noise with a voltage higher than the power supply voltage is applied to the input terminal IO, a voltage is applied to the protection element 1 for preventing electrostatic damage via the Al wiring 7a, and from one low concentration diffusion layer 8a to the silicon substrate 2. The inwardly expanded depletion layer reaches the other low concentration diffusion layer 8b (punch through).

Then, the current flowing from the low concentration diffusion layer 8a to the low concentration diffusion layer 8b via the silicon substrate 2 flows into the power supply 11 via the beta wiring 7b, thereby effectively preventing electrostatic damage to the internal integrated circuit 9. Ru.

Note that the voltage at which punch-through occurs is
It is determined by the distance from to the low concentration diffusion layer 8b,
If the punch-through voltage is too high, the internal integrated circuit 9 will be destroyed before the depletion layer reaches the low concentration diffusion layer 8b, so the punch-through voltage must be higher than the power supply voltage and not too high. is required.

Therefore, when manufacturing the protective element 1 for preventing electrostatic damage,
Controlling the distance is important, for example, the low concentration diffusion layer 8a
Consideration must be given to forming the low concentration diffusion layer 8b and the low concentration diffusion layer 8b in the same photolithography process.

As described above, according to this embodiment, the following effects can be obtained.

[1) The protective element 1 for preventing electrostatic damage is formed by a high concentration diffusion layer 4a.
, 4b and the low concentration diffusion layer 3a formed around them.
, and the low concentration diffusion layer 8b, the volume can be miniaturized compared to a conventional protection element for preventing electrostatic discharge damage that is composed of a pair of wells.

(2) According to the above (1), electrostatic damage to the internal integrated circuit can be effectively prevented without hindering the high integration of MOS type semiconductor devices.

(2) Due to (1) above, the present invention can be applied not only to CMOS type semiconductor devices but also to MOS type semiconductor devices consisting only of p-channel type elements or n-channel type elements without forming wells.

As above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say.

For example, in the embodiment, the low concentration diffusion layer was formed below the element isolation region, but as shown in FIG.
It is also possible to have a protective element structure for preventing electrostatic discharge damage in which elements a and 8b are formed inside the active region.

In addition, in the example, an n-type high concentration diffusion layer and an n-type low concentration diffusion layer were formed in a p-type silicon substrate.
A protection element structure for preventing electrostatic discharge damage may be provided in which a p-type high concentration diffusion layer and a p-type low concentration diffusion layer are formed in a silicon substrate or an n-type well.

In the above explanation, the invention made by the present inventor is mainly applied to a MOS type semiconductor device, which is the field of application of the invention, but the invention is not limited to this. forming a layer)
By adding the IJ Sogerahuie process, it becomes applicable to all semiconductor devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, a protective element for preventing electrostatic discharge damage consisting of a pair of high-concentration sales promotion layers formed facing each other at a predetermined distance in a silicon substrate and a low-concentration diffusion layer formed around them is attached to the silicon substrate. By creating a semiconductor device structure in which different conductivity types are formed and connected between the integrated circuit and the input or output terminal, electrostatic damage to the integrated circuit can be effectively prevented without hindering the high integration of semiconductor devices. It becomes possible to prevent this.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a silicon substrate showing a protection element for preventing electrostatic damage in a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the arrangement of this protection element for preventing electrostatic damage. FIG. 3 is a sectional view of a main part of a silicon substrate showing a protection element for preventing electrostatic damage in a semiconductor device according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Protective element for preventing electrostatic damage, 2... Silicon substrate, 3a, 3b, 3c... Element isolation region, 4a, 4b
...High concentration diffusion layer, 5...Insulating film, 6...Contact hole, 7a, 7b...A1 wiring, 3a, 3b.
...Low concentration diffusion layer, 9...Internal integrated circuit, 10...
Input (output) terminal, 11...power supply. Figure 3

Claims (1)

[Claims] 1. A pair of high concentration diffusion layers having a conductivity type different from that of the silicon substrate, which are formed facing each other at a predetermined distance in a silicon substrate, and each of the pair of high concentration diffusion layers. A protective element for preventing electrostatic damage caused by a low concentration diffusion layer formed around the high concentration diffusion layer and having the same conductivity type as the high concentration diffusion layer is connected between the integrated circuit and the input or output terminal. semiconductor device. 2. The semiconductor device according to claim 1, wherein the low concentration diffusion layer is formed inside the active region or below the element isolation region.