JPH09260644A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase surely the breakdown strength of a field effect transistor. SOLUTION: An n-channel MOS transistor and a p-type MOS transistor are formed in a semiconductor substrate 1. On the side of the n-channel MOS transistor, an n-type region 31 is provided in a p-type well region 11 in such a way as to connect to the end part, which is positioned on the far side as seen from an n<+> drain region 13, of an n<+> source region 12 and an n-type region 32 is provided in the region 11 in such a way as to connect to the end part, which is positioned on the far side as seen from the region 12, of the region 13. The regions 31 and 32 are formed in the same process as the process for forming n-type channel stoppers 26 of the p-channel MOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique for increasing the breakdown voltage of a field effect transistor.

[0002]

2. Description of the Related Art As a semiconductor element, a bipolar device, a MOS device, or the like is properly used depending on the application.
MOS devices have features such as a small control current, a high response speed, and a small chip area.

FIG. 4 is a sectional view of a conventional MOS transistor. In the figure, an example of a semiconductor device in which an nMOS transistor and a pMOS transistor are formed on a semiconductor substrate is shown.

The structure of the nMOS transistor is as follows. That, p-well region 11 is formed on the surface portion of the semiconductor substrate 1, while a predetermined interval from each other on the surface portion of the p-well region 11 n ⁺ source region 12 and n ⁺
The drain region 13 is formed. Moreover, to connect to the n ⁺ source region 12 and n ⁺ drain region 13 and each at a position facing the n ⁺ source region 12 and n ⁺ drain region 13 in the surface portion of the p-well region 11 n
LDD (Lightly Doped Drain) region 14 and nLD
The D region 15 is formed. Furthermore, p-well region 1
A p-channel stopper 16 is formed near the outer periphery of the surface portion inside 1.

[0005] p-well region 1 located in a region sandwiched between the n ⁺ surface of the source region 12 and n ⁺ drain region 13 and n ⁺ source region 12 and n ⁺ drain region 13,
A gate oxide film 17 is formed on the surface of 1. A field oxide film 18 is formed on the surface of another semiconductor region. Further, on the upper surface of the gate oxide film 17, a gate electrode 19 is formed in a region extending from the end of the nLDD region 14 to the end of the nLDD region 15 so as to extend over the p well region 11.

The pMOS transistor basically has the above-mentioned n.
It has the same structure as the MOS transistor. That is, the p ⁺ source region 22, the p ⁺ drain region 23, the pLDD regions 24 and 25, and the n channel stopper 26 are formed on the surface of the n well region 21. Further, like the nMOS transistor, a gate oxide film 27 and a gate electrode 29 are provided.

The on / off state of the nMOS transistor is controlled by the voltage applied to the gate electrode 19. For example, if this nMOS transistor is a normally-off type, in order to turn on, a voltage higher than a predetermined value (threshold voltage) is applied to the gate electrode 19.
When a voltage higher than the threshold voltage is applied to the gate electrode 19, the p well region 1 below the gate electrode 19
The conductivity type of the region near the surface of 1 is inverted from p type to n type, an n channel is formed there, and n ⁺ source region 12 and n ⁺
Drain region 13 (nLDD region 14 and nLDD region 1
Charges will flow between and 5). That is, nM
The OS transistor is turned on.

The pMOS transistor basically has the above n structure.
The operation is the same as that of the MOS transistor, and the gate electrode 29
The on / off state is controlled by the voltage applied to. By the way, when the MOS transistor is in the reverse bias state, if the reverse bias voltage becomes high, the MOS transistor breaks down. When the breakdown occurs, the transistor element itself may be broken.
For this reason, various measures have heretofore been made to increase the breakdown voltage of MOS transistors. For example, nLDD regions 14 and 15 (pLDD regions 24 and 25) shown in FIG. 4 are regions provided for increasing the breakdown voltage of MOS transistors. A technique for increasing the breakdown voltage of the nMOS transistor by providing the nLDD regions 14 and 15 will be described below with reference to FIG.

As shown in FIG. 5, when the n ⁺ source region 12 is grounded and a positive voltage V _R is applied to the n ⁺ drain region 13, the drain-source is reversely biased. In this state, the p well region 11 and the n ⁺ drain region 13 are
A depletion layer spreads in the p well region 11 and the n ⁺ drain region 13 from the junction surface of the pn junction formed by.

In the reverse bias state, assuming that the nLDD region 15 is not provided, in general, the breakdown occurs in the vicinity of the surface of the junction surface between the p well region 11 and the n ⁺ drain region 13 (the region surrounded by the broken line A). Is likely to occur. Therefore, in the area surrounded by the broken line A, n
⁺ NLDD having a lower impurity concentration than the drain region 13
A region 15 is provided. In the region where the impurity concentration is low, the depletion layer spreads gently, the electric field concentration is relaxed, and breakdown is less likely to occur.

With the above structure, breakdown is less likely to occur in the area surrounded by the broken line A, so that nM
The breakdown voltage of the OS transistor increases.

[0012]

As described above, the nLD
When the D region 15 is provided, breakdown is less likely to occur in the region surrounded by the broken line A. However, the conventional MOS transistor shown in FIG. 4 is not provided with a structure for preventing breakdown occurring in other regions. For example, in the reverse bias state, except for the area surrounded by the broken line A, the end portion of the n ⁺ drain region 13 located on the far side from the n ⁺ source region 12 (the area surrounded by the broken line B).
There is a high possibility that a breakdown will occur. Actually, depending on the impurity concentration and shape of each semiconductor region, nL
Even if the DD region 14 or 15 is not provided, the breakdown may occur in the region surrounded by the broken line B before the region surrounded by the broken line A.

As described above, in the MOS transistor shown in FIG. 4, nLDD regions 14 and 15 (pLDD region 2) are formed.
4 and 25), the breakdown in the area surrounded by the broken line A is prevented, but the structure that prevents the breakdown occurring in other areas is not provided. Therefore, for example, even if a very large reverse bias voltage is not applied, breakdown may occur in the region surrounded by the broken line B, and a high breakdown voltage can be obtained despite the provision of the LDD region. There was nothing. That is, the conventional method of increasing the breakdown voltage of the MOS transistor has not been sufficient.

An object of the present invention is to surely increase the breakdown voltage of a MOS transistor.

[0015]

According to the present invention, there is provided a semiconductor device comprising:
A field effect transistor, especially M, is formed on the surface of the semiconductor substrate.
This is a configuration in which the source region and the drain region of the OS transistor are formed. Then, a semiconductor region of the same conductivity type as that of the drain region is formed by connecting to the end of the drain region far from the source region and having an impurity concentration lower than that of the drain region.

At the place where the semiconductor region is formed, electric field concentration due to the depletion layer is likely to occur when the field effect transistor is in a reverse bias state. However,
Since the semiconductor region has a lower impurity concentration than the drain region, the depletion layer spreads gently in that region. Therefore, the electric field concentration is alleviated and the breakdown voltage is increased.

On the surface of the semiconductor substrate, a first conductive type first
In the case of the structure in which the field effect transistor and the second field effect transistor of the second conductivity type are formed,
In the field effect transistor of, the semiconductor device of the second field effect type is provided in the peripheral region at the end of the drain region far from the source region, the semiconductor region having the same conductivity type as that of the drain region with an impurity concentration lower than that of the drain region. It is formed in the same process as the channel stopper of the transistor.

According to the above manufacturing method, the semiconductor region for increasing the breakdown voltage can be provided without increasing the number of steps.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION In this embodiment, a semiconductor device in which an nMOS transistor and a pMOS transistor are formed on a semiconductor substrate will be described as an example, similarly to the structure adopted as the conventional technique. The MOS transistor of the present embodiment has the same conductivity type as that of the drain region and an impurity concentration higher than that of the drain region in that region so that breakdown is less likely to occur in the region surrounded by the broken line B shown in FIG. This is a configuration in which a low region is provided. Hereinafter, description will be made with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. In FIG. 1, when the reference numeral used in FIG. 4 is used, it indicates the same area as that described in FIG.
The nMOS transistor of this embodiment is the nM transistor shown in FIG.
The n-regions 31 and 32 are provided for the OS transistor, and the pMOS transistor of the present embodiment is
This is a configuration in which p regions 33 and 34 are provided for the pMOS transistor shown in FIG. That is, the nMOS transistor of the present embodiment has an n-position located in the p-well region 11 on the side farther from the n ⁺ drain region 13.
^An n region 31 is provided so as to be connected to the end of the ⁺ source region 12, and n located on the side far from the n ⁺ source region 12 is located.
⁺ N region 32 connected to the end of drain region 13
Is provided. The impurity concentration of the n regions 31 and 32 is determined by the n ⁺ source region 12 or the n ⁺ drain region 13
The impurity concentration is lower than the above. In addition, p region 3
The positions where 3 and 34 are formed and the impurity concentration are basically the same as those when the n regions 31 and 32 are formed.

By the way, when the MOS transistor is in the reverse bias state, it depends on how the voltage is applied.
Usually, breakdown occurs on the drain side. Therefore, in this embodiment, a semiconductor region (n regions 31 and 32 in the nMOS transistor, p regions 33 and 34 in the pMOS transistor) newly provided to increase the breakdown voltage may be formed only on the drain side. However, if the structure on the source side and the structure on the drain side are the same, the roles of the source region and the drain region can be replaced with each other. By providing, the degree of freedom of layout on the semiconductor substrate is increased.

Next, an example of a manufacturing process of the nMOS transistor and the pMOS transistor having the above-mentioned structure will be described. First, the p well region 11 and the n well region 21 are formed on the surface of the semiconductor substrate 1. Subsequently, after a nitride film (Si ₃ N ₄ film) is uniformly formed on the upper surface of the semiconductor substrate 1, the nitride film is removed except for the regions where the gate oxide films 17 and 27 are formed. Then, an n-type impurity for forming n regions 31 and 32 in a predetermined region of p-well region 11 and an n-type impurity for forming n channel stopper 26 in a predetermined region of n-well region 21 are simultaneously ion-implanted. To do. In addition, p is formed in a predetermined region of the p well region 11.
P-type impurities for forming the channel stopper 16,
P-type impurities for forming p regions 33 and 34 are simultaneously ion-implanted into a prescribed region of n well region 21.

In this state, the field oxide film 18 is formed by thermally oxidizing the upper surface of the semiconductor substrate 1. By this thermal oxidation process, the ion-implanted impurities are diffused in the p-well region 11 and the n-well region 21, respectively, and the p-channel stopper 16 and the n-region 31 are formed.
And 32, n channel stopper 26, and p regions 33 and 34 are formed.

Subsequently, the nitride film is removed, and gate oxide films 17 and 27 are formed in that region. A gate electrode 19 is provided on the gate oxide film 17, and a gate electrode 29 is provided on the gate oxide film 27. Gate electrodes 19 and 29
Is formed of, for example, polysilicon. After this, nLD
D regions 14 and 15 and pLDD regions 24 and 25 are formed.

Next, on the nMOS transistor side,
An n-type impurity for forming the n ⁺ source region 12 and the n ⁺ drain region 13 is implanted, and on the pMOS transistor side, the p ⁺ source region 22 and the p ⁺ drain region 2 are formed.
P-type impurities for forming 3 are implanted. These impurities are diffused into the p-well region 11 and the n-well region 21 by thermal diffusion, and the n ⁺ source region 1
2, n ⁺ drain region 13, p ⁺ source region 22, p ⁺
The drain region 23 is formed. At this time, the ends of the n ⁺ source region 12 and the n ⁺ drain region 13 are connected to the n regions 31 and 32, respectively, and the ends of the p ⁺ source region 22 and the p ⁺ drain region 23 are respectively p regions. Connected to 33 and 34.

Actually, following the above steps, the source electrode, the drain electrode, and the wiring pattern connected to them are formed. As described above, the MOS of the present embodiment
The transistor has a structure in which n regions 31 and 32 and p regions 33 and 34 are provided in the conventional MOS transistor shown in FIG. 4, and these regions are formed as n channel stopper 26 and p channel stopper 16 respectively. It is formed in the same process. That is, p channel stopper 1
6 or n regions 31, 32, and p regions 33 without changing the manufacturing process as compared with the prior art, simply by changing the pattern of the mask used when ion-implanting impurities for forming the n-channel stopper 26. 34 can be formed.

The p-channel stopper 16 or the n-channel stopper 26 has heretofore been widely known as a structure for preventing the influence of a parasitic MOS transistor. Referring to FIG. 2, n regions 31, 32, and p
The effect of providing the regions 33 and 34 will be described. Here, an nMOS transistor will be described as an example.
Further, in FIG. 2, similarly to the state described in FIG. 5, the n ⁺ source region 12 is grounded, the positive voltage V _R is applied to the n ⁺ drain region 13, and the drain-source is in the reverse bias state. There is. When the reverse bias voltage is applied in this manner, the p-well region 1 is formed from the junction surface of the pn junction formed by the p-well region 11 and the n ⁺ drain region 13.
A depletion layer spreads in 1 and n ⁺ drain region 13.

In the conventional structure shown in FIG. 5, breakdown is likely to occur in the area surrounded by the broken line B. However, in this embodiment, the n region 32 having a lower impurity concentration than the n ⁺ source region 12 or the n ⁺ drain region 13 is formed in that region.

Therefore, in the region surrounded by the broken line B, the depletion layer on the n-type semiconductor region side spreads gently in the n region 32. As is well known, in the region where the depletion layer spreads gently, the electric field strength is weak and breakdown is unlikely to occur. Therefore, in the present embodiment, breakdown is unlikely to occur in the area surrounded by the broken line B.

On the other hand, in the region surrounded by the broken line B, the depletion layer on the p-type semiconductor region side expands by enclosing the n ⁺ drain region 13 and the n region 32 by providing the n region 32. For this reason, the depletion layer in that region has a gentle curve (curved surface), which also makes breakdown less likely to occur.

As described above, in the nMOS transistor of this embodiment, since the n region 32 is provided, the electric field at the end of the n ⁺ drain region 13 on the field oxide film 18 side (the region surrounded by the broken line B) is formed. Relaxed concentration, making breakdown less likely to occur. That is, the nMOS of the present embodiment
In the transistor, the nLDD region 15 is provided in the region surrounded by the broken line A (the end of the n ⁺ drain region 13 on the gate electrode 19 side) of the two regions in which the breakdown easily occurs. High breakdown voltage is applied by the n region 3 for the region surrounded by the broken line B (the end of the n ⁺ drain region 13 on the field oxide film 18 side).
By providing 2, high breakdown voltage is achieved. As a result, the breakdown voltage of the nMOS transistor increases.

Even in the pMOS transistor,
By providing the p regions 33 and 34 by the same action, high breakdown voltage is realized. FIG. 3 is a sectional view of a semiconductor device according to another embodiment of the present invention. In FIG.
When the reference numeral used in FIG. 1 is used, it indicates the same area as the area described in FIG. Note that only the nMOS transistor is shown here. In addition, the semiconductor substrate 1 is a p-type and p
The well region 11 is not provided.

In the structure shown in FIG. 3, n ⁻ regions 35 and 36 are provided instead of the n regions 31 and 32 shown in FIG. The n ⁻ regions 35 and 36 are respectively n ⁺
The n ⁺ source region 1 is formed so as to cover the ends of the source region 12 and the n ⁺ drain region 13 on the field oxide film 18 side.
2 and the n ⁺ drain region 13 are diffused deeper and formed. Further, the impurity concentrations of the n ⁻ regions 35 and 36 are such that the n ⁺ source region 12 and the n ⁺ drain region 13 are
Low enough. Alternatively, the impurity concentration of the n ⁻ regions 35 and 36 may be set to the same level as that of the nLDD regions 14 or 15. In any case, if the n ⁻ regions 35 and 36 are formed in independent steps, their impurity concentrations can be set arbitrarily.

The nMOS transistor shown in FIG. 3, n ^-
Since the regions 35 and 36 are provided, the n regions 31 and 3 are provided.
Withstand voltage is increased by the same action as when 2 is provided. Further, unlike the configuration shown in FIG. 1, for example, n ⁻ regions 35 and 36 are not limited to be formed in the same step as n channel stopper 26, so that the impurity concentration thereof can be made sufficiently low. If the impurity concentration of n ⁻ regions 35 and 36 is made sufficiently low, the depletion layer spreads more slowly in that region, and breakdown is less likely to occur.

Although the nMOS transistor has been described with reference to FIG. 3, the same applies to the pMOS transistor. Further, in the above-described embodiment, the MOS transistor has been described as an example, but the present invention can be applied to other field effect transistors.

[0036]

A low concentration region of the same conductivity type as the drain region and having a lower impurity concentration than that of the drain region is provided by connecting to the end of the drain region on the side far from the source region of the field effect transistor. Therefore, breakdown is less likely to occur there, and the breakdown voltage increases. Moreover, since the low concentration region is formed in the same step as the channel stopper of the field effect transistor, the number of manufacturing steps does not increase.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an effect of the present invention.

FIG. 3 is a sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a sectional view of a conventional MOS transistor.

FIG. 5 is a diagram illustrating a problem of a conventional MOS transistor.

[Explanation of symbols]

1 semiconductor substrate 11 p well region 12 n ⁺ source region 13 n ⁺ drain region 14, 15 nLDD region 16 p channel stopper 17, 27 gate oxide film 18 field oxide film 19, 29 gate electrode 21 n well region 22 p ⁺ source region 23 p ⁺ drain region 24, 25 pLDD region 26 n channel stopper 31, 32 n region 33, 34 p region 35, 36 n ⁻ region

Claims (3)

[Claims] 1. In a semiconductor device in which a source region and a drain region of a field effect transistor are formed on a surface portion of a semiconductor substrate, an impurity lower than the drain region is connected to an end of the drain region far from the source region. A semiconductor device characterized in that a semiconductor region of the same conductivity type as that of the drain region is formed in concentration. 2. The semiconductor region of the same conductivity type as that of the source region is formed by connecting to the end of the source region on the side far from the drain region and having an impurity concentration lower than that of the source region. Semiconductor device. 3. A first field effect transistor having a first conductivity type and a second field effect transistor having a second conductivity type on a surface portion of a semiconductor substrate.
Of the first field-effect transistor, the first field-effect transistor having a lower impurity concentration than the drain region in a peripheral region at an end of the drain region far from the source region. A semiconductor device, wherein a semiconductor region having the same conductivity type as the drain region is formed in the same step as a channel stopper of the second field effect transistor.