JPH08250668A - Electrostatic discharge protection device in silicon - on - insulator structure and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an ESD protective element having a high ESD sensitivity by a method, wherein the ESD protective element is formed of a transistor of an SOI structure and a bulk field transistor, an ESD stress is induced to the bulk field transistor and the ESD stress is made to be thermally consume in a bulk silicon layer. SOLUTION: An ESD protective element consists of a substrate, formed by lamination with a buried insulating layer 11 in a bulk silicon layer 10 and an upper silicon layer 15 on the layer 10, a transistor, which is formed on the layer 15 at a first region on the substrate of a SOI structure, and a bulk field transistor formed in a bulk silicon layer 20 at a second region on the substrate. As a result, when an ESD stress is applied to the bulk field transistor, a parasitic bipolar is generated from the bulk silicon layer 20 of the bulk field transistor, and the ESD stress is consumed in the layer 20, whereby as the temperature in the interior of the element rises very low so that the element can have high ESD sensitivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an electrostatic discharge protection element resistant to electrostatic discharge stress and a method of manufacturing the same.

[0002]

2. Description of the Related Art A silicon-on-insulator (Silico) for stacking a buried insulating layer and an upper silicon layer on a bulk silicon layer to form a semiconductor device on the upper silicon layer.
n-On-Insulator (hereinafter referred to as SOI) technology is a technology that more effectively separates semiconductor elements and the like formed on a silicon substrate from each other, and reduces latch-up of transistors to reduce junction capacitance. Such reduction in parasitic resistance enables the integrated circuit to operate at a circuit speed much higher than that of the conventional bulk substrate integrated circuit with the same device size. In addition, SOI technology is in the spotlight due to its improved short-channel effect, high circuit density and easy manufacturing process.

Generally, an electrostatic discharge of a semiconductor device (Electr
ostatic Discharge: hereinafter referred to as ESD) When a pulse is applied, a high current flows into the inside of the device. Such an ESD stress causes a parasitic bipolar operation from the inside of the semiconductor device to thermally exhaust the device.

Bulk substrate technology can maintain excellent ESD protection levels by using NMOS / PMOS output buffers. However, since most of the protection structures used in such bulk technology are not compatible with the devices of SOI structure, ESD sensitivity has become an important factor in terms of reliability with the rapid progress of SOI technology.

Further, in an SOI structure device, such an ESD stress should be consumed by a thin upper silicon layer, but the silicon layer that thermally consumes the ESD stress is relatively thin as compared with a bulk substrate device. So it becomes vulnerable to ESD stress.

[0006]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an ESD protection element that is resistant to ESD stress.

Another object of the present invention is to provide a method of manufacturing an ESD protection device which is particularly suitable for manufacturing the ESD protection device.

[0008]

In order to achieve the above object, the present invention provides a substrate in which a buried insulating layer and an upper silicon layer are stacked on a bulk silicon layer, and the upper portion is formed in a first region of the substrate. There is provided an ESD protection device comprising an SOI structure transistor formed on a silicon layer and a bulk field transistor formed on the bulk silicon layer in a second region of the substrate.

The bulk field region may be formed of a MOS transistor.

The upper silicon layer may be used as a gate of the bulk field transistor. The gate of the bulk field transistor may be connected to the Vss terminal and may also be connected to a pad for an external power source.

In order to achieve the above-mentioned other objects, the present invention provides:
Forming a substrate by sequentially stacking a buried insulating layer and an upper silicon layer on the bulk silicon layer;
A step of manufacturing a transistor having an SOI structure on the upper silicon layer in a region, and a pair of impurity regions in the bulk silicon layer exposed after selectively etching the buried insulating layer in the second region of the substrate. And a method of manufacturing a bulk field transistor by providing the above method.

During the process of manufacturing the bulk field transistor, the upper silicon layer may be completely removed, and the upper silicon layer may be patterned to form a gate.

The bulk field transistor is N
In the case of a P-type device, P-type impurities are ion-implanted into the bulk silicon layer, and the bulk field transistor is
In the case of a type device, it is desirable to ion-implant an N type impurity into the bulk silicon layer.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIGS. 1 to 3, in an SOI output buffer or input buffer structure, an ESD protection device is formed in a drive transistor and a bulk field region of the SOI structure.

As shown in FIG. 2, the SOI driving transistor includes a buried insulating layer 1 on a bulk silicon layer 10.
It is composed of a gate 14 formed on the upper silicon layer 15 which is formed through the layer 1 and a source 13 and a drain 12 formed in the upper silicon layer 15. here,
Reference numeral 16 in FIG. 2 denotes an insulating film for insulating the gate 14, and 17 denotes a source electrode and a drain electrode.

In the bulk field region, as shown in FIG. 3, the buried silicon layer 2 is formed by removing the upper silicon layer 15.
1 is selectively etched, and then a source 23 and a drain 22 are formed on the exposed bulk silicon layer 20 to form a gate-free transistor structure. Reference numeral 27 indicates a source electrode and a drain electrode. At this time, the breakdown voltage of the bulk field transistor is
If the bulk field transistor is an N-type device, a P-type
Type impurities are ion-implanted, conversely N for P type elements
Ion-implant impurities in the form. The gate 14 of the SOI driving transistor may be connected to an input driver or a Vss terminal, and the bulk field transistor and the SOI driving transistor may be connected to each other by a diffusion resistor Rd.

The operation of the ESD protection device shown in FIG. 1 is as follows.

First, in a normal operation, the SOI drive transistor operates to function as a normal output buffer or input buffer. However, when the ESD pulse is applied, the SOI driving transistor is floated and the bulk field transistor is grounded. Initially, a low current flows into the drive transistor of SOI, but when the current gradually increases, the voltage at point A rises and the breakdown voltage of the bulk field transistor is exceeded, and a large current flows to the bulk field transistor. It will flow. In the bulk field transistor, the breakdown region does not occur at the surface 24 of the silicon layer but at the junction portion 25 of the source or drain, but since the concentration of impurities in the bulk silicon layer is high at the junction portion, the breakdown region in the area where the parasitic bipolar operation is performed. The resistance decreases. This results in a reduction in the overall power that thermally dissipates the ESD stress, so the ESD protection device of the present invention may confirm good ESD susceptibility. Here, the pad is a terminal for inputting / outputting data in the semiconductor device.

FIG. 4 is an equivalent circuit diagram of an ESD protection device according to a second embodiment of the present invention, showing an ESD protection device in which a gate of a transistor having a bulk field structure is connected to a Vss terminal.

FIG. 5 is an equivalent circuit diagram of an ESD protection device according to a third embodiment of the present invention, in which a gate of a transistor having a bulk field structure is connected to an external power supply pad.
Indicates an ESD protection device.

FIG. 6 shows the second and third embodiments of the present invention.
FIG. 3 shows a cross-sectional view of a bulk field transistor in an ESD protection device.

Referring to FIG. 6, a bulk field transistor is provided with a gate, a source and a drain by selectively patterning an upper silicon layer of an SOI structure to form a gate 26 of the upper silicon layer. It is formed with a transistor structure.

FIG. 7 is a graph showing the results of the ESD simulation of the conventional ESD protection element and the ESD protection element of the present invention.

Referring to FIG. 7, when an ESD stress is applied, the conventional ESD protection device has a low internal temperature because the internal temperature of the device rapidly increases from a narrow region of the upper silicon layer of the SOI structure.
Has ESD sensitivity. On the contrary, the ESD protection device according to the present invention has a high ESD susceptibility because the internal temperature of the device rises by a very small amount by causing parasitic bipolar from the bulk silicon layer of the bulk field transistor to consume ESD stress.

[0026]

As described above, according to the present invention,
By forming an ESD protection element including a transistor having an SOI structure and a bulk field transistor, an ESD stress is induced in the bulk field transistor and this is thermally consumed in the bulk silicon layer. Therefore, an ESD protection element having high ESD sensitivity can be obtained.

The present invention is not limited to the above embodiments, and it is obvious that many modifications can be made by a person having ordinary skill in the art within the technical idea of the present invention.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an ESD protection device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of an SOI driving transistor in an ESD protection device according to a first exemplary embodiment of the present invention.

FIG. 3 is a sectional view of a bulk field transistor in the ESD protection device according to the first embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of an ESD protection device according to a second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of an ESD protection device according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view of a bulk field transistor in an ESD protection device according to second and third embodiments of the present invention.

FIG. 7 is a graph showing the results of ESD simulations of the conventional ESD protection element and the ESD protection element of the present invention.

Claims (10)

[Claims] 1. A substrate having a buried insulating layer and an upper silicon layer stacked on a bulk silicon layer, and a transistor having a silicon-on-insulator structure formed on the upper silicon layer in a first region of the substrate. And a bulk field transistor formed on the bulk silicon layer in the second region of the substrate. 2. The bulk field transistor
The electrostatic discharge protection device according to claim 1, which is formed of a MOS transistor. 3. The electrostatic discharge protection device according to claim 1, wherein the upper silicon layer is used as a gate of the bulk field transistor. 4. The electrostatic discharge protection device of claim 3, wherein a gate of the bulk field transistor is connected to a Vss terminal. 5. The electrostatic discharge protection device of claim 3, wherein a gate of the bulk field transistor is connected to a pad for an external power source. 6. Forming a substrate by sequentially stacking a buried insulating layer and an upper silicon layer on a bulk silicon layer to form a substrate on the upper silicon layer in a first region of the substrate. A step of manufacturing a transistor having an insulator structure; and, in the second region of the substrate, selectively etching the buried insulating layer and then forming a pair of impurity regions in the exposed bulk silicon layer to form a bulk field transistor. A method of manufacturing an electrostatic discharge protection device, comprising the step of manufacturing. 7. The method according to claim 6, wherein the upper silicon layer is completely removed in the step of manufacturing the bulk field transistor. 8. The method according to claim 6, wherein the gate is formed by patterning the upper silicon layer in the step of manufacturing the bulk field transistor. 9. The bulk field transistor is
7. The method of manufacturing an electrostatic discharge protection device according to claim 6, wherein in the case of an N-type device, P-type impurities are ion-implanted into the bulk silicon layer. 10. The method for manufacturing an electrostatic discharge protection device according to claim 6, wherein when the bulk field transistor is a P-type device, N-type impurities are ion-implanted into the bulk silicon layer.