JP3123489B2 - Electrostatic protection circuit in semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit in a semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to a semiconductor device for preventing electrostatic breakdown of a circuit element formed around an external terminal such as an input / output terminal. The present invention relates to an electrostatic protection circuit in an integrated circuit and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, elements of semiconductor integrated circuits such as LSIs have been miniaturized with the progress of high integration, high density, and high processing speed. Is composed of MOS (metal oxide semisonductor) transistors, the thickness of the gate oxide film tends to be further reduced with miniaturization of elements. When the thickness of the gate oxide film is reduced, the withstand voltage of the gate oxide film against static electricity is reduced, so that it is difficult to protect the static electricity.

[0003] Therefore, heretofore, the following electrostatic protection circuit in a semiconductor integrated circuit has been proposed. 6A and 6B show a configuration example of an electrostatic protection circuit in a conventional semiconductor integrated circuit in which a protection element is formed of an nMOS transistor, where FIG. 6A is a plan view and FIG. 6B is along the line CC of FIG. FIG. 7 is a plan view showing a state where the field oxide film is removed from FIG. As shown in these figures, a rectangular p-type well 2 is formed in a surface portion of a p-type semiconductor substrate 1, and nM is formed in a surface portion of the p-type well 2.
A gate electrode 3 of the OS transistor, a drain region 4 made of an n-type high concentration diffusion layer, and a source region 5 are formed. Although not shown, a gate oxide film is formed below the gate electrode 3. Also, p-type well 2
A p-type high-concentration diffusion layer 6 in the shape of a square is formed in the surface layer portion to surround the nMOS transistor.
In the high-concentration diffusion layer 6, a plurality of p-type well contacts 7 are formed at predetermined intervals. p-type high concentration diffusion layer 6
Are formed to connect the p-type well 2 to a ground terminal (not shown) via the p-type well contact 7 and a metal wiring (not shown).

In order to insulate the drain region 4 and the source region 5 from the p-type high-concentration diffusion layer 6, a field oxide having a similar shape to the p-type high-concentration diffusion layer 6 is provided inside the p-type high-concentration diffusion layer 6. A film 8 is formed. Further, a field oxide film 9 similar in shape to the p-type high-concentration diffusion layer 6 is formed outside the p-type high-concentration diffusion layer 6 to insulate other parts from the electrostatic protection circuit. . The drain region 4 is connected to an input / output terminal (not shown), and the source region 5 and the p-type well contact 7 are connected to a ground terminal (not shown). Note that the potential of the gate electrode 3 is fixed at a predetermined potential.

In the above configuration, when a positive electrostatic pulse is applied to the drain region 4, the n-type drain region 4
Impact ionization occurs at the pn junction end between the pn junction and the p-type well 2 to generate electron-hole pairs. Here, the impact ionization means that carriers are accelerated by a high reverse bias electric field applied to a pn junction and collide with semiconductor atoms to ionize the semiconductor atoms. At this time, since the impurity concentration of the p-type well 2 is higher than the impurity concentration of the p-type semiconductor substrate 1 and has a lower resistance value, holes generated by impact ionization are converted into a substrate current by the p-type well 2 having a lower resistance value. Flows through the p-type high-concentration diffusion layer 6 and the p-type well contact 7 to the ground terminal (not shown). As described above, since the substrate current flows in the p-type well 2, a potential difference is generated between the p-type well 2 and the source region 5.
Is in a forward bias state, and the nMOS transistor easily operates as a npn lateral bipolar transistor. As a result, the voltage (holding voltage) held between the drain region 4 and the source region 5 is lower than the breakdown voltage of the pn junction between the p-type well 2 and the n-type source region 5.

As described above, in this electrostatic protection circuit, the nMOS transistor can easily perform the bipolar operation, so that the electrostatic discharge current can be discharged to the ground terminal (not shown) at a low holding voltage. Since the electrostatic discharge current does not leak from the region surrounded by the p-type high concentration diffusion layer 6, the electrostatic breakdown of the peripheral circuit elements is prevented.

Japanese Unexamined Patent Publication (Kokai) No. 3-231470 discloses an electrostatic protection circuit in a semiconductor integrated circuit having a structure in which an n-type diffusion layer formed in a p-type well by a field oxide film is separated from its surroundings. ing. In the electrostatic protection circuit described in this publication, an n-type diffusion layer and a p-type well contact are formed in the same p-type well as in the above-described electrostatic protection circuit in a conventional semiconductor integrated circuit.
Since the mold well and the n-type diffusion layer easily perform a bipolar operation, electrostatic breakdown of peripheral circuit elements is prevented.

[0008]

By the way, as the size of a device in a semiconductor integrated circuit advances, the p-type well 2 is formed in accordance with a scaling rule of how a design parameter such as a propagation delay time changes when the size of the device is reduced. Has a high impurity concentration and a low resistance value. Therefore, FIG.
If the configuration of the electrostatic protection circuit in the conventional semiconductor integrated circuit shown in FIG. 7 is used as it is in a semiconductor integrated circuit in which the element is miniaturized, a pn junction between the n-type drain region 4 and the p-type well 2 is obtained. Most of the substrate current generated at the end is due to the p-type well 2 having a high impurity concentration and a low resistance value.
Therefore, the potential of the p-type well 2 hardly increases, and the nMOS transistor hardly performs a bipolar operation. pn between the n-type drain region 4 and the p-type well 2
Since the allowable electrostatic discharge current at the junction is determined by the equation (1), if the nMOS transistor becomes difficult to perform the bipolar operation, the voltage (holding voltage) held between the drain region 4 and the source region 5 of the nMOS transistor becomes high. Voltage and the permissible electrostatic discharge current is reduced. Allowable electrostatic discharge current = (Joule heat) / (holding voltage) (1) As a result, there is a disadvantage that the protection function is reduced and the electrostatic resistance is deteriorated.

Further, when the electrostatic protection circuit in the above-described conventional semiconductor integrated circuit is constituted by a plurality of nMOS transistors formed in the same p-type well 2, the p-type well contact 7 is close to the p-type well contact 7. Placed n
Since the MOS transistor has a short path through which the substrate current flows, the resistance value of the p-type well 2 is small, and the potential difference between the p-type well 2 and the source region 5 is small. On the other hand, nM located away from p-type well contact 7
Since the OS transistor has a longer path for the substrate current to flow than the nMOS transistor arranged close to the p-type well contact 7, the resistance of the p-type well 2 is large, and the p-type well 2 and the source region 5 Is large. As described above, since the nMOS transistor having a small resistance value of the p-type well 2 is less likely to perform a bipolar operation, the nMOS transistor having a relatively large resistance value of the p-type well 2 is nM.
This means that the OS transistor is easier to perform the bipolar operation, and the electrostatic discharge current is concentrated on the nMOS transistor that easily performs the bipolar operation, and there is a risk that the nMOS transistor is thermally damaged.

[0010] The danger of thermal destruction of such an nMOS transistor is that in an nMOS transistor in which the surfaces of the drain region 4 and the source region 5 are made of metal silicide, an electrostatic discharge current is generated near the surface of the metal silicide layer having a low resistance. Are concentrated, so that the height is further increased, thereby further deteriorating the electrostatic resistance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is capable of securing a sufficient electrostatic resistance even when the elements of a semiconductor integrated circuit are miniaturized or a plurality of protective elements are formed. An object of the present invention is to provide an electrostatic protection circuit in a circuit and a method for manufacturing the same.

[0012]

According to a first aspect of the present invention, there is provided an electrostatic protection circuit in a semiconductor integrated circuit, comprising: a first conductive type semiconductor substrate; A first conductivity type well formed on a surface layer of the first conductivity type semiconductor substrate so as to surround the first first conductivity type well at a predetermined distance; At least one set of a gate electrode, a drain region, and a source region, which are formed in a surface layer portion of the first first conductivity type well and constitute at least one second conductivity type MOS transistor, and the second first conductivity type A first conductivity type high-concentration diffusion layer formed in a surface layer portion of the mold well; and a plurality of first conductivity type well contacts formed in the first conductivity-type high concentration diffusion layer. Connected to input / output terminals, Serial source region and the plurality of first
The conductive type well contact is connected to a power supply terminal or a ground terminal.

In the invention according to claim 1,
The first conductivity type and the second conductivity type represent n-type or p-type, and when the first conductivity type is n-type, the second conductivity type is p-type.
And if the first conductivity type is p-type, the second conductivity type is n-type. The same applies to the invention described in the following claims.

According to a second aspect of the present invention, there is provided the electrostatic protection circuit in the semiconductor integrated circuit according to the first aspect, wherein the first first conductivity type well of the surface layer portion of the first conductivity type semiconductor substrate is provided. A second conductivity type well is provided between the second first conductivity type well and the second first conductivity type well.

According to a third aspect of the present invention, there is provided the electrostatic protection circuit in the semiconductor integrated circuit according to the second aspect, wherein the lower part of the first well of the first conductivity type and the lower part of the well of the second conductivity type are provided. It has a deep second conductivity type well formed, and the potential of the first first conductivity type well is a floating potential.

According to a fourth aspect of the present invention, there is provided the electrostatic protection circuit in the semiconductor integrated circuit according to any one of the first to third aspects, wherein the drain region, the source region, and the first conductive type high voltage are connected. A refractory metal silicide film is formed on the surface of the concentration diffusion layer.

According to a fifth aspect of the present invention, there is provided a method for manufacturing an electrostatic protection circuit in a semiconductor integrated circuit, comprising the steps of: forming a first well of the first conductivity type on a surface layer of a semiconductor substrate of the first conductivity type; Forming a second first conductivity type well surrounding the first conductivity type well at a predetermined distance;
At least one set of a gate electrode, a drain region and a source region constituting at least one second conductivity type MOS transistor is formed in a surface layer portion of the conductivity type well, and
Forming a first-conductivity-type high-concentration diffusion layer in a surface layer of the second first-conductivity-type well; and forming a plurality of first-conductivity-type well contacts in the first-conductivity-type high-concentration diffusion layer And connecting the drain region to an input / output terminal and connecting the source region and the first conductivity type well contact to a power supply terminal or a ground terminal.

According to a sixth aspect of the present invention, there is provided a method of manufacturing an electrostatic protection circuit in a semiconductor integrated circuit according to the fifth aspect, wherein the first first conductive layer on a surface portion of the first conductive type semiconductor substrate is provided. A step of forming a second conductivity type well between the mold well and the second first conductivity type well.

According to a seventh aspect of the present invention, there is provided a method of manufacturing an electrostatic protection circuit in a semiconductor integrated circuit according to the sixth aspect, wherein a lower portion of the first first conductivity type well and a lower portion of the second conductivity type well are formed. A step of forming a deep second conductivity type well is provided below, and the potential of the first first conductivity type well is a floating potential.

Further, the invention according to claim 8 relates to a method of manufacturing an electrostatic protection circuit in a semiconductor integrated circuit according to any one of claims 4 to 7, wherein the method includes the steps of:
Forming a refractory metal silicide film on the surface of the source region and the first conductivity type high concentration diffusion layer.

[0021]

According to the structure of the present invention, the second protection element is used.
A first first conductivity type well in which a conductivity type MOS transistor is formed and a second first conductivity type well in which a first conductivity type well contact connected to a ground terminal is formed are formed by a first method.
Since the substrate is formed via the surface layer of the conductive semiconductor substrate, a substrate current based on static electricity flows to the first conductive semiconductor substrate having a high resistance value, and the second conductive MOS transistor easily operates in a bipolar manner. Therefore, even if the element of the semiconductor integrated circuit is miniaturized and the impurity concentration of the first first conductivity type well is increased and its resistance value is reduced, sufficient electrostatic resistance can be ensured. Further, even when a plurality of protection elements are formed, sufficient electrostatic resistance can be ensured without depending on the arrangement.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using an embodiment. A. First Embodiment FIGS. 1A and 1B are diagrams showing a configuration of an electrostatic protection circuit in a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. FIG. 2 is a plan view showing a state in which the field oxide film and titanium silicide are removed from FIG. 1A. With reference to these drawings, the configuration of this electrostatic protection circuit will be described together with its manufacturing method. First, after a field oxide film 12 is formed on the surface of an element isolation region of a p-type semiconductor substrate 11, a photoresist (not shown) is applied to the entire surface of the substrate, and the p-type wells 13 and 1 are formed by photolithography.
The photoresist is patterned so as to open an area in which 4 is to be formed. Next, a dose of about 1 × 10 ^{13 to} 3 × 10 ¹³ c of p-type impurities is applied from the surface side of the p-type semiconductor substrate 11.
By ion implantation at m ⁻² , the p-type semiconductor substrate 11
The rectangular p-type well 13 and the p-type well 1
3 is a square-shaped p-type well 14 surrounding a surface layer portion (hereinafter, referred to as a divided portion) 11 a of the p-type semiconductor substrate 11.
To form Next, the nMOS is added to the surface of the p-type well 13.
A gate electrode 15 constituting a transistor is formed, and gate sidewall oxide films 16 are formed on both side surfaces of the gate electrode 15. Although not shown, a gate oxide film is already formed below the gate electrode 15.

Thereafter, an n-type impurity is ion-implanted from the surface side of the p-type semiconductor substrate 11 to thereby form the p-type well 1.
A drain region 17 and a source region 18 made of an n-type high concentration diffusion layer are formed in the surface layer portion of No. 3. Further, before and after this step, a p-type impurity is ion-implanted from the surface side of the p-type semiconductor substrate 11 to form a p-type high concentration diffusion layer 19 in the surface layer of the p-type well 14.

Next, after a titanium thin film, for example, as a high melting point metal thin film is formed on the entire surface of the substrate by a sputtering method, high-temperature annealing and selective etching are performed.
Only the titanium thin film formed on the surfaces of the drain region 17, the source region 18 and the p-type high concentration diffusion layer 19 is silicided to form a titanium silicide 20. Thereafter, although not shown, after forming an insulating film on the entire surface of the substrate, a plurality of p-type well contacts 21 are formed in the p-type high concentration diffusion layer 19 at predetermined intervals. The drain region 17 is connected to an input / output terminal (not shown) via a metal wiring, and the source region 18
The p-type well contact 21 is connected to a ground terminal (not shown) via a metal wiring. The potential of the gate electrode 15 is fixed at a predetermined potential.

In the configuration of the electrostatic protection circuit manufactured by the above manufacturing method, when a positive electrostatic pulse is applied to the drain region 17, a pn junction end between the n-type drain region 17 and the p-type well 13 is formed. Impact ionization occurs in the part, an electron-hole pair is generated, and the hole is
First, after flowing through the p-type well 13 having a high impurity concentration and a low resistance value, as shown by an arrow in FIG. 1B, the divided portion 11 of the p-type semiconductor substrate 11 having a low impurity concentration and a high resistance value
Via a, it flows through the p-type well 14, the p-type high-concentration diffusion layer 19, and the p-type well contact 21, and flows to a ground terminal (not shown).

As described above, when the substrate current flows through the divided portion 11a of the p-type semiconductor substrate 11, the resistance value of the p-type semiconductor substrate 11 is sufficiently high between the source region 18 and the p-type well 13 which are the ground potential. Since a large potential difference occurs, the pn junction between the p-type well 13 and the n-type source region 18 is in a forward-biased state, and the nMOS transistor is more likely to perform a bipolar operation than in the prior art. In this case, not only the p-type well 13 but also the p-type semiconductor substrate 11
Therefore, the easiness of the bipolar operation of the nMOS transistor does not depend on the impurity concentration of the p-type well 13. Therefore, by miniaturizing the elements constituting the semiconductor integrated circuit, the p-type well 13
Even if the impurity concentration becomes high, a predetermined electrostatic resistance can be ensured.

Even if a plurality of nMOS transistors are connected in parallel, even if the nMOS transistor is arranged close to the p-type well contact 21 which has not been easily bipolar-operated conventionally, the p-type well contact 21 Since the dividing portion 11a having a sufficiently higher resistance value than the resistance value of the p-type well 13 is interposed therebetween,
A sufficient potential difference is generated between the source region 18 and the p-type well 13. Since this potential difference is determined by the potential difference generated in the p-type semiconductor substrate 11, the easiness of the bipolar operation of each nMOS transistor does not depend on the position of the nMOS transistor, and the electrostatic discharge current concentrates on a specific nMOS transistor as in the related art. Thus, there is little danger of the nMOS transistor being thermally destroyed. This is more remarkable when titanium silicide 20 is formed on the surfaces of drain region 17, source region 18 and p-type high concentration diffusion layer 19, as shown in FIG. Therefore, the formation of the titanium silicide 20 does not deteriorate the electrostatic resistance.

B. Second Embodiment Next, a second embodiment of the present invention will be described. FIG.
1A is a diagram showing a configuration of an electrostatic protection circuit in a semiconductor integrated circuit according to a second embodiment of the present invention, FIG.
4B is a sectional view taken along the line BB in FIG.
FIG. 3 is a plan view showing a state where a field oxide film and titanium silicide are removed from FIG. With reference to these drawings, the configuration of this electrostatic protection circuit will be described together with its manufacturing method. First, after a field oxide film 32 is formed on the surface of an element isolation region of a p-type semiconductor substrate 31, a photoresist (not shown) is applied to the entire surface of the substrate, and p-type wells 33 and 34 are formed by photolithography. The photoresist is patterned to open an area to be formed. Next, a p-type impurity is dosed from the surface of the p-type semiconductor substrate 31 at a dose of about 1 × 10 ^{13 to} 3 × 10 ^13.
By ion implantation at cm ⁻² , the p-type semiconductor substrate 3
A rectangular p-type well 33 and a square-shaped p-type well 34 surrounding the p-type well 33 with the surface layer of the p-type semiconductor substrate 31 interposed therebetween are formed in the surface layer portion of FIG.

Next, a photoresist (not shown) is applied again on the entire surface of the substrate, and the photoresist is patterned by photolithography to open a region where the n-type well 35 is to be formed. Next, from the surface side of the p-type semiconductor substrate 31, an n-type impurity is dosed by about 1 × 10 ¹³ to
By implanting ions at 3 × 10 ¹³ cm ⁻² , the p-type well 33 and the p-type well 3 in the surface portion of the p-type semiconductor substrate 31 are formed.
, A rectangular n-type well 3 surrounding the p-type well 33
5 is formed. Next, nMO is added to the surface layer of the p-type well 33.
A gate electrode 36 constituting the S transistor and gate sidewall oxide films 37 are formed on both side surfaces of the gate electrode 36, respectively. Although not shown, a gate oxide film is already formed below the gate electrode 36.

Thereafter, an n-type impurity is ion-implanted from the surface side of the p-type semiconductor substrate 31 to thereby form the p-type well 3.
A drain region 38 and a source region 39 made of an n-type high concentration diffusion layer are formed in the surface layer portion of No. 3. Further, before and after this step, p-type impurities are ion-implanted from the surface side of the p-type semiconductor substrate 31 to form a p-type high concentration diffusion layer 40 in the surface layer of the p-type well 34.

Next, after a titanium thin film, for example, as a high melting point metal thin film is formed on the entire surface of the substrate by sputtering, high-temperature annealing and selective etching are performed.
Only the titanium thin film formed on the surfaces of the drain region 38, the source region 39 and the p-type high concentration diffusion layer 40 is silicided to form a titanium silicide 41. Thereafter, although not shown, after forming an insulating film on the entire surface of the substrate, a plurality of p-type well contacts 42 are formed at predetermined intervals in the p-type high concentration diffusion layer 40. The drain region 38 is connected to an input / output terminal (not shown) via a metal wiring, and the source region 39 is connected.
The p-type well contact 42 is connected to a ground terminal (not shown) via a metal wiring. The potential of the gate electrode 36 is fixed at a predetermined potential.

In the configuration of the electrostatic protection circuit manufactured by the above manufacturing method, when a positive electrostatic pulse is applied to the drain region 38, a pn junction end between the n-type drain region 38 and the p-type well 39 is formed. Impact ionization occurs in the part, an electron-hole pair is generated, and the hole is
First, after flowing through a p-type well 33 having a high impurity concentration and a low resistance value, a square-shaped n-type well 35 whose resistance value is higher than the resistance value of the p-type semiconductor substrate 31 is formed. As shown by arrows in FIG. 3B, most of them pass through the p-type semiconductor substrate 31 having a low impurity concentration and a high resistance under the p-type well 33, and pass through the p-type wells 34 and p.
The high-concentration diffusion layer 40 and the p-type well contact 42 flow to the ground terminal (not shown).

As described above, when the substrate current flows through the p-type semiconductor substrate 31 below the p-type well 33, the resistance of the p-type semiconductor substrate 31 between the source region 39, which is the ground potential, and the p-type well 33. Since a sufficient potential difference is generated depending on the value, the p-type well 33 and the p-type
The n-junction is in a forward-biased state, and the nMOS transistor is more likely to perform a bipolar operation than in the past. In this case, since the substrate current flows not only in the p-type well 33 but also in the p-type semiconductor substrate 31, the easiness of the bipolar operation of the nMOS transistor does not depend on the impurity concentration of the p-type well 33. Therefore, a predetermined electrostatic resistance can be secured even if the impurity concentration of the p-type well 33 is increased due to the miniaturization of the elements constituting the semiconductor integrated circuit.

Even if a plurality of nMOS transistors are formed in parallel connection, even if the nMOS transistor is arranged close to the p-type well contact 42 which has not been easily bipolar-operated conventionally, the p-type well contact 42 The n-type well 35 having a sufficiently higher resistance value than the respective resistance values of the p-type well 13 and the p-type semiconductor substrate 31 is interposed therebetween. Flowing through the p-type semiconductor substrate 31, a sufficient potential difference is generated between the source region 39 and the p-type well 33. Since this potential difference is determined by the potential difference generated in the p-type semiconductor substrate 31, the easiness of the bipolar operation of each nMOS transistor does not depend on the position of the nMOS transistor, and the electrostatic discharge current is concentrated on a specific nMOS transistor as in the related art. And the nMOS
There is little risk of the transistor being thermally destroyed. This is more remarkable when titanium silicide 41 is formed on the surfaces of drain region 38, source region 39 and p-type high concentration diffusion layer 40 as shown in FIG. Therefore, the formation of the titanium silicide 41 does not degrade the electrostatic resistance.

C. Third Embodiment Next, a third embodiment will be described. FIG. 5 shows a third embodiment of the present invention in which the protection element is constituted by an nMOS transistor.
FIG. 3 is a cross-sectional view illustrating a configuration of an electrostatic protection circuit in the semiconductor integrated circuit according to the example. In this figure, FIG.
The same reference numerals are given to the portions corresponding to the respective portions, and the description thereof will be omitted. In the electrostatic protection circuit in the semiconductor integrated circuit shown in FIG.
Implanting high-impurity ions at a dose of about 1 × 10 ^{13 to} 3 × 10 ¹³ cm ⁻² to form a p-type well 33
, And a deep n-type well 51 is newly formed below the n-type well 35. The deep n-type well 51 is formed, for example, before forming the p-type well 33. Note that the potential of the p-type well 33 is set to a floating potential, different from the second embodiment.

In the electrostatic protection circuit having the above configuration, when a positive electrostatic pulse is applied to the drain region 38, impact ionization occurs at the pn junction end between the n-type drain region 38 and the p-type well 39. An electron-hole pair is generated, and the hole flows as a substrate current. However, since the deep n-type well 51 whose resistance is higher than the resistance of the p-type semiconductor substrate 31 is formed, the p-type well 33 is formed. The potential of
It becomes easier to raise as compared with the second embodiment. Therefore, the nMOS transistor is more likely to perform a bipolar operation. Since the easiness of the bipolar operation of the nMOS transistor does not depend on the impurity concentration of the p-type well 33 as in the case of the above-described second embodiment, the element constituting the semiconductor integrated circuit is miniaturized. Even if the impurity concentration of the p-type well 33 is increased, a predetermined static resistance can be ensured.

The same applies to the case where a plurality of nMOS transistors are formed in parallel in the surface layer portion of the p-type well 33, and the easiness of the bipolar operation of the nMOS transistor depends on the position of the nMOS transistor. And a titanium silicide 41 on the surface of the drain region 38, the source region 39 and the p-type high concentration diffusion layer 40.
Is formed, a more remarkable function and effect is obtained, and the formation of the titanium silicide 41 does not deteriorate the electrostatic resistance.

According to the configurations of the first to third embodiments described above, when the gate length of the nMOS transistor forming the electrostatic protection circuit is approximately 0.35 μm, the HBM-ES
The electrostatic withstand capability in the D (Human Body Model-Electrostatic Discharge) test was 200 V, while that of the conventional electrostatic protection circuit shown in FIGS.
It turned out that it improved to 0V or more. Where HB
The M-ESD test is a standard method for measuring the electrostatic withstand capability of an electrostatic protection circuit by supplying an amount of static electricity normally assumed to be accumulated in a human body to a semiconductor integrated circuit and discharging the same.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and changes in design and the like can be made without departing from the gist of the present invention. Even if there is, it is included in the present invention. For example, in the above-described embodiment, an example in which a p-type semiconductor substrate is used has been described. However, the present invention is not limited to this. In addition to using an n-type semiconductor substrate, the conductivity type of each well and each layer is reversed from that in the above-described embodiment. In addition, even if the drain region and the n-type well contact are connected to the power supply terminal via the metal wiring, substantially the same operation and effect as described in the above embodiment can be obtained. Further, in the above-described embodiment, the example in which the titanium silicide film is formed as the silicide film is described, but the present invention is not limited to this, and any silicide film of a high melting point metal such as platinum or tungsten may be used. .

[0040]

As described above, according to the first and fifth aspects of the present invention, the second conductivity type M serving as a protection element is provided.
The first first conductivity type well in which the OS transistor is formed and the second first conductivity type well in which the first conductivity type well contact connected to the ground terminal is formed are formed on the surface of the first conductivity type semiconductor substrate. Since it is formed via the portion, the substrate current based on the static electricity flows to the first conductivity type semiconductor substrate having a high resistance value, and the second conductivity type MOS transistor easily operates in a bipolar manner.

According to the second and sixth aspects of the present invention, the first well of the first conductivity type and the second well of the first conductivity type are provided.
Since the second conductivity type well is interposed between the second conductivity type well and the second conductivity type well, the substrate current based on static electricity flows through the first conductivity type semiconductor substrate having a high resistance value.
Transistors are more easily operated in bipolar mode. Further, according to the third and seventh aspects of the present invention, a deep second conductivity type well is formed below the first first conductivity type well and below the second conductivity type well. A substrate current based on static electricity flows through the deep second conductivity type well having a high resistance value and the first conductivity type semiconductor substrate, and the second conductivity type MOS transistor is more likely to perform a bipolar operation. Therefore, even if the element of the semiconductor integrated circuit is miniaturized and the impurity concentration of the first first conductivity type well is increased and its resistance value is reduced, sufficient electrostatic resistance can be ensured. Further, even when a plurality of protection elements are formed, sufficient electrostatic resistance can be ensured without depending on the arrangement. Such an effect is achieved in claims 4 and 8
According to the configuration of the described invention, this is more remarkable.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a configuration of an electrostatic protection circuit in a semiconductor integrated circuit according to a first embodiment of the present invention, wherein FIG. 1A is a plan view and FIG. 1B is along the line AA in FIG. It is sectional drawing.

FIG. 2 is a plan view showing a state where a field oxide film and titanium silicide are removed from FIG.

FIGS. 3A and 3B are diagrams showing a configuration of an electrostatic protection circuit in a semiconductor integrated circuit according to a second embodiment of the present invention, wherein FIG. 3A is a plan view and FIG. 3B is along the line BB in FIG. It is sectional drawing.

FIG. 4 is a plan view showing a state where a field oxide film and titanium silicide are removed from FIG.

FIG. 5 is a sectional view showing a configuration of an electrostatic protection circuit in a semiconductor integrated circuit according to a third embodiment of the present invention.

6A and 6B show a configuration example of an electrostatic protection circuit in a conventional semiconductor integrated circuit, where FIG. 6A is a plan view, and FIG.
It is sectional drawing which follows the C line.

FIG. 7 is a plan view showing a state where a field oxide film is removed from FIG. 6;

[Explanation of symbols]

11, 31 p-type semiconductor substrate (first conductivity type semiconductor substrate) 11a divided portion (first conductivity type semiconductor substrate) 13, 14, 33, 34 p-type well (first conductivity type well) 15, 36 gate electrode 17, 38 drain region 18, 39 source region 19, 40 p-type high concentration diffusion layer (first conductivity type high concentration diffusion layer) 20, 41 titanium silicide (silicide film) 21, 42 p-type well contact (first conductivity type well contact) ) 35 n-type well (second conductivity type well) 51 deep n-type well (deep second conductivity type well)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822

Claims (8)

(57) [Claims] A first conductive type well formed in a surface portion of the first conductive type semiconductor substrate; and a first first conductive type well formed in a surface portion of the first conductive type semiconductor substrate. A second formed to surround at a distance
A first conductivity type well, and at least one set of a gate electrode, a drain region, and a source region which are formed in a surface layer of the first first conductivity type well and constitute at least one second conductivity type MOS transistor. And a first layer formed in a surface layer of the second first conductivity type well.
A conductive type high concentration diffusion layer, and a plurality of first conductivity type well contacts formed in the first conductivity type high concentration diffusion layer; wherein the drain region is connected to an input / output terminal and the source An electrostatic protection circuit in a semiconductor integrated circuit, wherein the region and the plurality of first conductivity type well contacts are connected to a power supply terminal or a ground terminal. 2. A second conductivity type well is provided between the first first conductivity type well and the second first conductivity type well in a surface layer portion of the first conductivity type semiconductor substrate. 2. An electrostatic protection circuit in a semiconductor integrated circuit according to claim 1, wherein: 3. A deep second formed below the first first conductivity type well and below the second conductivity type well.
3. The electrostatic protection circuit according to claim 2, wherein the well has a conductivity type, and the potential of the first first conductivity type well is a floating potential. 4. A high melting point metal silicide film is formed on the surface of the drain region, the source region and the first conductivity type high concentration diffusion layer, respectively. 2. An electrostatic protection circuit in the semiconductor integrated circuit according to claim 1. 5. A first conductive type semiconductor substrate, comprising:
Forming a first conductivity type well and a second first conductivity type well surrounding the first first conductivity type well at a predetermined distance; and a surface portion of the first first conductivity type well. At least one
At least one set of a gate electrode, a drain region, and a source region constituting the second MOS transistors of the second conductivity type are formed, and a high-concentration diffusion layer of the first conductivity type is formed on the surface of the second first conductivity type well. Forming a plurality of first conductivity type well contacts in the first conductivity type high concentration diffusion layer; connecting the drain region to an input / output terminal; Connecting the one conductivity type well contact to a power supply terminal or a ground terminal. 6. A step of forming a second conductivity type well between the first first conductivity type well and the second first conductivity type well in a surface portion of the first conductivity type semiconductor substrate. 6. The method for manufacturing an electrostatic protection circuit in a semiconductor integrated circuit according to claim 5, comprising: 7. A step of forming a deep second conductivity type well below the first first conductivity type well and below the second conductivity type well, wherein the first first conductivity type well is formed. 7. The method according to claim 6, wherein said potential is a floating potential. 8. The method according to claim 4, further comprising the step of forming a silicide film of a refractory metal on surfaces of the drain region, the source region, and the first conductivity type high concentration diffusion layer. 2. A method for manufacturing an electrostatic protection circuit in a semiconductor integrated circuit according to item 1.