JP2003100877A - Input protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input protection circuit which exhibits a high ESD (electrostatic discharge) withstand voltage and by which signals in a broad level range can be inputted. SOLUTION: An n-type well region 12 is formed on the surface of a substrate 10. A p-channel MOS transistor FT11 is formed in the region 12, and an n- channel MOS transistor FT12 is formed on the surface of the substrate 10. The FT12 may be formed in a p-type well region 36. The source of the FT11 and the gate of the FT12 are connected to an input terminal IN and the drain of the FT11 to the drain of the FT12 and the source of the FT12 and the substrate 10 to a ground Vss. In response to the + ESD input to the input terminal IN, the FT11 and the FT12 are brought into conduction. A lateral bipolar transistor BP13 may be formed with the source of the FT12 as an emitter, and the collector of the BP13 may be connected to the drain of the FT12 . The n-channel MOS transistor FT13 may be used as the BP13 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type LSI.
The present invention relates to an input protection circuit that protects an input section of an integrated circuit device such as the above from damage due to ESD (electrostatic discharge) or the like.
In this specification, the term “ESD input” means “surge voltage input due to static electricity or the like”.

[0002]

2. Description of the Related Art Conventionally, as input protection circuits used in CMOS ICs, those shown in FIGS. 4 and 5 are known. 4 and 5, IN is an input terminal for supplying an input signal to the protected circuit CP.

In the circuit of FIG. 4, the input terminal IN has N
Channel MOS type transistor FT₁The drain D of
Connected and transistor FT₁Gate G, Seo
The source S and the substrate electrode are at the ground point (reference potential point) V_SSContact
Has been continued. Diode D ₁Is the transistor FT₁
Of the drain pn junction of FIG.

When the + ESD input is applied to the input terminal IN, the transistor FT ₁ becomes conductive by the punch-through phenomenon and protects the protected circuit CP from the ESD input. Further, when a negative ESD input is applied to the input terminal IN, the diode D ₁ becomes conductive and protects the protected circuit CP.

In the circuit of FIG. 5, in the circuit of FIG. 4, the drain D of the P-channel MOS transistor FT ₂ is connected to the input terminal IN, and the gate G, the source S and the substrate electrode of the transistor FT ₂ are connected to the power supply potential V. It corresponds to one connected to a power supply line to which _DD (for example, +5 [V]) is applied. The diode D ₂ represents the drain PN junction of the transistor FT ₂ .

The protection operation of the transistor FT ₁ is similar to that described above with reference to FIG. -ES to input terminal IN
When the D input is applied, the transistor FT ₂ becomes conductive by the punch-through phenomenon and protects the protected circuit CP. When the + ESD input is applied to the input terminal IN, the diode D ₂ becomes conductive and protects the protected circuit CP.

[0007]

According to the circuits of FIGS. 4 and 5, there is a problem that the signal level that can be input is limited to a low level in a normal use state. That is, the breakdown voltage of the gate insulating film of the transistors FT ₁ and FT ₂ is usually 10
[V] and the input terminal IN is, for example, +12 [V]
When the signal voltage of 1 is supplied, the gate insulating film of the transistor FT ₁ is destroyed. Also, for example, -1 is applied to the input terminal IN.
When a signal voltage of 2 [V] is supplied, the transistor FT ₂
The gate insulating film of is destroyed. Further, when a signal voltage of +12 [V] is supplied to the input terminal IN, the diode D
₂ becomes conductive, and when a signal voltage of −12 [V] is supplied to the input terminal IN, the diode D ₁ becomes conductive. Therefore, in the circuits of FIGS. 4 and 5, a signal of ± 12 [V] is applied to the protected circuit C.
I can't type in P. Besides, the transistor F
Since the gate insulating films of T ₁ and FT ₂ have low withstand voltage, ESD
There is also a problem that the breakdown voltage is low.

An object of the present invention is to provide a novel input protection circuit which has a high ESD withstand voltage and can input a signal in a wide ± level range.

[0009]

A first input protection circuit according to the present invention includes an input terminal for supplying an input signal to a protected circuit, a semiconductor substrate having a first conductivity type, and the first conductivity type. Have a second conductivity type opposite to the semiconductor substrate and PN
A well region formed on one main surface of the semiconductor substrate so as to form a junction, a first MOS transistor formed in the well region and having the first conductivity type as a channel conductivity type, and the semiconductor substrate. A second MOS transistor formed outside the well region on one main surface and having the second conductivity type as a channel conductivity type, the source of the first MOS transistor and the second MOS transistor. The gate of the MOS transistor to the input terminal, the drain of the first MOS transistor to the drain of the second MOS transistor, the source of the second MOS transistor and the semiconductor substrate to the reference potential point, respectively. The first and second MOS transistors are connected to each other in response to a surge voltage input such as static electricity. It is intended.

A second input protection circuit according to the present invention has an input terminal for supplying an input signal to the protected circuit, and a first input protection circuit.
A first well having a conductivity type semiconductor substrate and a second conductivity type opposite to the first conductivity type, the first well being formed on one main surface of the semiconductor substrate so as to form a PN junction with the semiconductor substrate. A region, a second well region having the first conductivity type and formed on one main surface of the semiconductor substrate, and a first well region formed in the first well region and having the first conductivity type as the channel conductivity type.
A first MOS type transistor having a conductivity type; and a second MOS type transistor formed in the second well region and having the second conductivity type as a channel conductivity type, the first MOS type transistor The source of the transistor and the gate of the second MOS type transistor are used as the input terminal, the drain of the first MOS type transistor is used as the drain of the second MOS type transistor, and the second
The source of the MOS type transistor and the second well region are respectively connected to a reference potential point, and the first and second MOS type transistors are made conductive in response to a surge voltage input such as static electricity. . In such a structure, the first and second well regions may be formed adjacent to each other on one main surface of the semiconductor substrate so as to form a PN junction, or may be formed apart from each other.

According to the first or second input protection circuit, assuming that the first and second conductivity types are P-type and N-type, respectively, the first and second MOS type transistors are P-channel and N-channel, respectively. Will have. In the first and second MOS transistors, the gate insulating film can be composed of a field insulating film (oxide film), and in this case, a breakdown voltage of about 250 [V] can be obtained.

When the maximum value of the voltage as an input signal supplied to the input terminal is Vm, the first and second MOS transistors are both configured so that the absolute value of the threshold voltage is larger than Vm. be able to. When the + ESD input is applied to the input terminal, the first and second MOS transistors become conductive when the gate voltage reaches the threshold voltage for setting, and a large current flows. Therefore, the protected circuit is protected from the + ESD input.

When a negative ESD input is applied to the input terminal, the breakdown voltage of the source PN junction of the first MOS transistor is set to V _B, and the PN junction between the well region and the substrate (or between the well regions) is set. Given that the forward voltage drop is Vf, these PN junctions conduct at a voltage of V _B + Vf, and a large current flows. Therefore, the protected circuit is
Protected from SD input.

When a + input voltage Vm is applied to the input terminal in a normal use state, both the first and second MOS type transistors are non-conductive. At this time, it is the PN junction between the N-type well region and the P-type substrate (or between the N-type and P-type well regions) that is biased in the reverse direction. This PN junction is a region having a low impurity concentration. PN between
Since it is a junction, it can have a high breakdown voltage of about 50 [V]. Therefore, Vm is, for example, 1
At 2 [V], substantially no current flows in the PN junction between the well region and the substrate (or between the well regions), and the voltage of + Vm is normally input to the protected circuit.

When a voltage of -Vm is applied to the input terminal,
The source PN junction of the first MOS transistor is reverse biased, and the PN junction between the N-type well region and the P-type substrate (or between the N-type and P-type well region) is forward-biased. Here, it is easy to set the breakdown voltage of the source PN junction biased in the reverse direction to about 12 [V], and the PN biased in the forward direction is used.
The forward voltage drop of the junction is usually about 0.6 [V]. Therefore, if Vm is set to, for example, 12 [V], substantially no current flows in the source PN junction of the first MOS transistor and the PN junction between the well region and the substrate (or between the well regions), and −Vm. Is normally input to the protected circuit.

The second input protection circuit corresponds to the first input protection circuit in which a well region of the first conductivity type is provided in addition to a well region of the second conductivity type, and a second MOS type transistor is provided. This has the advantage that the degree of freedom in setting the characteristics for

In the first or second input protection circuit, a lateral bipolar transistor whose source is the emitter of the second MOS transistor is formed near the second MOS transistor, and the collector of the bipolar transistor is formed. It may be configured to be connected to the drain of the second MOS transistor. By doing this, the second
Since the bipolar transistor is connected in parallel to the MOS type transistor and the bipolar transistor becomes conductive with the conduction of the second MOS type transistor, the current load on the second MOS type transistor can be reduced. As the lateral bipolar transistor, a MOS type transistor having a source and a drain self-aligned with the gate may be used, which improves the dimensional accuracy of the bipolar transistor.

[0018]

1 shows an integrated configuration of an input protection circuit according to an embodiment of the present invention, and FIG. 2 shows an equivalent circuit of the configuration of FIG. 1 and 2,
IN is an input terminal for supplying an input signal to the protected circuit CP.

A semiconductor substrate 1 made of, for example, P-type silicon
0 is a relatively low impurity concentration (for example, 10 ¹⁵ [cm
^-3 ] or less), and an N-type well region 12 is formed on one main surface so as to form a PN junction with the substrate 10. The well region 12 has a relatively low impurity concentration (for example, 4 × 10 ¹⁶ to 1 × 10 ¹⁷ [cm ⁻³ ]), and is formed by a selective ion implantation method or the like.

One main surface of the substrate 10 is covered with a field insulating film 14 made of silicon oxide or the like.
The insulating film 14 is formed by the selective oxidation process,
A thin insulating film 14 a of silicon oxide or the like is formed in each impurity doping hole of the insulating film 14. P ⁺
The type impurity doped regions 16, 18 and 26 are formed by doping the P type determining impurities through the corresponding impurity doping holes. The N ⁺ -type impurity-doped region 22 is exposed to N through the corresponding impurity-doped hole.
It is formed by doping a type determining impurity.

A thin insulating film 14b made of silicon oxide or the like is formed as a gate insulating film in the element hole of the insulating film 14. The insulating film 14b is formed by oxidizing the insulating film 1
It is formed simultaneously with 4a. After forming a polycide layer (a laminated layer of a silicide layer on a polysilicon layer) on the upper surface of the substrate, patterning the polycide layer by photolithography and dry etching treatment forms gate electrode layers 30, 32, and 34 made of the remaining polycide. It is formed. Using the gate electrode layer 34 as a mask, the N ⁺ -type impurity-doped regions 20 and 28 are formed by selectively doping the N-type determining impurity into the substrate surface in the element hole. The impurity-doped regions 20 and 28 are formed in the gate electrode layer 34.
It is formed with high dimensional accuracy in a form self-aligned with.

In the well region 12, a P channel MOS is provided.
Of the P ⁺ type source region 16 and P of the type transistor FT ₁₁
^{The +} type drain region 18 is formed so as to sandwich the gate insulating film made of a part 14A of the insulating film 14. The source region 16 (source S of the FT ₁₁ ) is connected to the input terminal IN. The gate electrode layer 30 of the transistor FT ₁₁ is
It is formed on the gate insulating film 14A so as to extend over the source region 16 and the drain region 18. The gate electrode layer 30 (gate G of _{FT 11)} is connected to ground (reference potential _{point) V SS.} Since the gate insulating film 14A is composed of a field insulating film (oxide film), 250
It has a breakdown voltage of about [V].

PNP lateral bipolar transistor B
P ₁₁ is a parasitic transistor having a source region 16 and a drain region 18 as an emitter and a drain, respectively. The diodes D ₁₁ and D ₁₃ are respectively FT ₁₁
Of the source PN junction and the drain PN junction. The diode D ₁₂ is connected to the P between the well region 12 and the substrate 10.
Represents N-junction. The cathode of the diode D ₁₂ is integral with the base of the transistor BP ₁₂ .

An N-channel MOS type transistor F is provided outside the well region 12 on one main surface of the substrate 10.
The N ⁺ type source region 20 and the N ⁺ type drain region 22 of T ₁₂ are formed so as to sandwich the gate insulating film formed of the part 14B of the insulating film 14. Source region 20 (FT ₁₂
Source S) of the drain region 22 (drain D of FT ₁₂ ) is connected to the ground region V _SS.
(Drain D of FT ₁₁ ). The gate electrode layer 32 of the transistor FT ₁₂ is formed on the gate insulating film 14B so as to extend over the source region 20 and the drain region 22. Since the gate insulating film 14B is composed of a field insulating film (oxide film),
It has a breakdown voltage of about [V]. Gate electrode layer 32 (FT
The gate G) of ₁₂ is connected to the input terminal IN. P ⁺
-Type contact region 26 is of the substrate contact of the transistor _{FT 12,} is connected to the ground point _{V SS.}

The NPN lateral bipolar transistor BP ₁₂ is a parasitic transistor having a source region 20 and a drain region 22 as an emitter and a collector, respectively. Between the base of the transistor BP ₁₂ and the contact region 26, there is a resistance R composed of the resistance component of the substrate 10. The base of the transistor BP ₁₂ is integral with the anode of the diode D ₁₂ . A connection point between the base of the transistor BP ₁₂ and the resistor R is referred to as a node N ₁ .

[0026] in the vicinity of the transistor _{FT 12} may form a N-channel MOS transistor _{FT 13} to the source region 20 of the transistor _{FT 12} and the source S. A gate electrode layer 34 is formed on the gate insulating film 14b, and the gate electrode layer 3 is formed on the surface of the substrate 10.
N ⁺ type source region 20 and N ⁺ type drain region 28 are formed in a self-aligned manner. Drain region 28 (F
The drain D of T ₁₃ is the drain region 18 (FT ₁₁
Connected to the drain D). Gate electrode layer 34 (FT
The gate G of ₁₃₎ is connected to ground _{V SS.}

The NPN lateral bipolar transistor BP ₁₃ is a parasitic transistor having a source region 20 and a drain region 28 as an emitter and a collector, respectively. The base of the transistor BP ₁₃ is integral with the base of the transistor BP ₁₂ .

When the maximum value of the voltage as an input signal supplied to the input terminal IN is Vm, the transistor FT
₁₁ and FT ₁₂ are both set so that the absolute value of the threshold voltage is larger than Vm. Also,
The transistor FT ₁₃ is a bipolar transistor BP
Since used as _13, the channel need only be in the OFF state in a state in which the source and gate as shown connected to ground V _SS.

Next, the operation of the circuits shown in FIGS. 1 and 2 will be described.
When + ESD input is applied to the input terminal IN,
Register FT₁₁, FT₁₂Each has a gate voltage
When the threshold voltage related to the setting is reached, it conducts and
Shed the flow. As an example, when Vm = 12 [V],
Langista FT₁₁, FT₁₂Has a gate voltage of 12
A current flows when the voltage exceeds [V]. Therefore, the protected circuit C
P is protected from the + ESD input. In this case, the tiger
Register BP_ThirteenExists, the transistor BP₁₂
The reverse current of the collector PN junction of flows through the resistor R
Therefore, node N ₁Potential rises and the transistor BP
_ThirteenConducts and current flows.

When a negative ESD input is applied to the input terminal IN, the breakdown voltage of the source PN junction (diode D ₁₁ ) of the transistor FT ₁₁ is set to V _B, and the PN junction between the well region and the substrate (diode D _{12) is set.} the forward voltage drop when the Vf of) these PN junctions, _{V B}
It conducts at a voltage of + Vf and a large current flows. As an example,
When V _B = 12 [V] and Vf = 0.6 [V], the diodes D ₁₁ and D ₁₂ conduct at 12.6 [V].
Therefore, the protected circuit CP is protected from the − ESD input.

When a voltage of + Vm is applied to the input terminal IN in a normal use state, the transistors FT ₁₁ and
Both FT ₁₂ are non-conductive. In addition, the diode D _{1 1} is forward biased and the diode D ₁ is
₁₂ is reverse biased. The breakdown voltage of the diode D ₁₂ is set to about 50 [V] because the impurity concentration of the well region 12 and the substrate 10 is low.
In such a set state, if Vm = 12 [V], the diode D ₁₂ is non-conductive. Therefore, + Vm
Is normally input to the protected circuit CP.

When a voltage of -Vm is applied to the input terminal IN, the diode D ₁₁ is reversely biased and the diode D ₁₂ is forward biased. As an example, if Vm = 12 [V], the breakdown voltage of the diode D ₁₁ is 12 [V], and the forward voltage drop of the diode D ₁₂ is 0.6 [V], then −12 [V] At the input voltage, the diodes D ₁₁ and D ₁₂ are non-conducting. Therefore, the voltage of -Vm is normally input to the protected circuit CP.

In the above-described embodiment, the P-type well region 36 may be provided on one main surface of the substrate 10. The well region 36 may be provided adjacent to the well region 12 so as to form a PN junction, or may be provided separately from the well region 12. The well region 36 has a relatively low impurity concentration (for example, 4 × 10 ¹⁶ to 1 × 10 ¹⁷ [c
m ^{- 3])} those having, formed by selective ion implantation or the like.

A transistor FT is provided in the well region 36.
₁₂ , FT ₁₃ , BP ₁₂ , and BP ₁₃ are formed in the same manner as described above. The bases of the transistors BP ₁₂ and BP ₁₃ are formed by the well region 36. Well area 3
6 is connected to the ground point V _SS via the contact region 26. The resistance R is composed of the resistance component of the well region 36. When the well region 36 is formed adjacent to the well region 12, the diode D ₁₂ is composed of a PN junction between the well regions 12 and 36.

When the well region 36 is provided as described above, the equivalent circuit is the same as that shown in FIG. 2 and the operation is the same as that described above. By providing the well region 36, the transistors FT ₁₂ , FT ₁₃ , BP ₁₂ , B
The degree of freedom in setting the characteristics of P ₁₃ is improved.

FIG. 3 shows a modification of the circuit shown in FIG. 2. The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The input terminal IN has a source S of an N-channel MOS transistor FT ₂₁ and a P-channel MO.
The gate G of the S-type transistor FT ₂₂ is connected.
The gate G of the transistor _{FT 21} is connected to ground _{V SS,} the drain D of the transistor _{FT 2 1} is connected to the drain D of the transistor _{FT 22.} The source S of the transistor _{FT 22} is connected to the ground point _{V SS.}

NPN type bipolar transistor BP ₂₁
Each source S and the drain D of the transistor FT ₂₁ is a parasitic transistor to the emitter and collector. The PNP bipolar transistor BP ₂₂ is
It is a parasitic transistor in which the source S and the drain D of the transistor FT ₂₂ are the emitter and the collector, respectively. A PN junction diode D ₂₂ is formed between the P-type base of the transistor BP _{21 and} the N-type base of the transistor BP ₂₂ . The cathode of the diode D ₂₂ is connected to the ground point V _SS via the resistor R. The connection point between the base of the transistor BP ₂₂ and the resistor R is a node N.
_Set to ₂ .

[0039] in parallel to the transistor _{FT 22} may be connected to the P-channel MOS transistor _{FT 23.} The drain D of the transistor FT ₂₃ is
Is connected to the drain D of _22, the gate G and the source S of the transistor _{FT 23} is connected to ground _{V SS.}
The PNP bipolar transistor BP ₂₃ is a parasitic transistor in which the source S and the drain D of the transistor FT ₂₃ are the emitter and the collector, respectively.

As an integrated configuration of the circuit of FIG. 3, for example, in the integrated configuration of FIG. 1, the conductivity type of the substrate 10 is N type and the conductivity types of the well regions 12 and 36 are P type, respectively.
Type, N type, the source region 16, the drain region 18, and the contact region 26 all have N ⁺ type conductivity, and the source regions 20 and the drain regions 22 and 28 have P ⁺ type conductivity types, respectively. . In this case, assuming that the maximum value of the voltage as the input signal supplied to the input terminal IN is Vm, the transistors FT ₂₁ and FT ₂₂ are both configured so that the absolute value of the threshold voltage is larger than Vm. Further, the transistor FT _23, since used as a bipolar transistor BP _23, channel state where the source and gate as shown and connected to the ground point V _SS is sufficient if the off state. The well region 36
The N-type well region corresponding to can be omitted.

In the configuration described above with reference to FIG. 3, when a negative ESD input is applied to the input terminal IN, the transistors FT ₂₁ and FT _{22 become} conductive when the gate voltage reaches the threshold voltage set, and a large current flows. Shed. As an example, when Vm = 12 [V], the gate voltage of the transistors FT ₂₁ and FT ₂₂ is 12 [V].
An electric current flows when it exceeds. Therefore, the protected circuit CP is
Protected from negative ESD inputs. In this case, the transistor _{BP 23} is present, since the reverse current of the collector PN junction of the transistor _{BP 2 2} flows through the resistor R, the potential of the node _{N 2} is lowered, the transistor _{BP 23}
Conducts and current flows.

[0042] When the ESD input to the input terminal IN + is applied, the breakdown voltage of the source PN junction of the transistor _{FT 21} and _{V B,} the well region - PN between the substrate
Assuming that the forward voltage drop of the junction (diode D ₂₂ ) is Vf, these PN junctions conduct at a voltage of V _B + Vf, and a large current flows. As an example, V _B = 12 [V], V
When f = 0.6 [V], the source PN junction of the transistor FT ₂₁ and the diode D ₂₂ are 12.6 [V].
Conduct with. Therefore, the protected circuit CP is protected from the + ESD input.

[0043] In normal use, the voltage of -Vm is applied to the input terminal IN, the transistor _{FT 21,}
Both FT ₂₂ are non-conductive. Also, the source PN junction of the transistor FT ₂₁ is forward biased and the diode D ₂₂ is reverse biased. The breakdown voltage of diode D ₂₂ is well region 1
2 and the substrate 10 are set to about 50 [V] as described above. In such a setting state, Vm =
If it is 12 [V], the diode D ₂₂ is non-conductive. Therefore, the voltage of -Vm is normally input to the protected circuit CP.

A voltage of + Vm is applied to the input terminal IN.
And the transistor FT₂₁Source PN junction in the opposite direction
Biased and diode D₂₂Is forward
Be assed. As an example, when Vm = 12 [V],
Register FT₂₁Source PN junction breakdown voltage
The pressure is set to 12 [V] and the diode D₂₂Forward voltage drop
If the bottom is 0.6 [V], then with an input voltage of -12 [V]
Is the transistor FT ₂₁Source pn junction and dio
Mode D₂₂Is non-conducting. Therefore, the voltage of + Vm is
It is normally input to the protected circuit CP.

[0045]

As described above, according to the present invention, the first and second MOS type transistors having different channel conductivity types are formed in the well region and the substrate (or another well region), respectively. Transistors are connected in series, and the first and second MOS type transistors are made conductive in accordance with the ESD input applied to the input terminal. Therefore, the gate insulating film and the well region of the first and second MOS type transistors are formed. -By increasing the breakdown voltage of the PN junction between the substrates (or between the well regions), a high ESD breakdown voltage can be obtained, and a signal in a wide level range such as ± 12 [V] can be input.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an integrated configuration of an input protection circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of the configuration of FIG.

FIG. 3 is a circuit diagram showing a modified example of the circuit of FIG.

FIG. 4 is a circuit diagram showing an example of a conventional input protection circuit.

FIG. 5 is a circuit diagram showing another example of a conventional input protection circuit.

[Explanation of symbols]

IN: input terminal, CP: protected circuit, D _{11 to} D ₁₃ ,
D ₂₂ : Diode, BP ₁₁ to BP ₁₃ , BP ₂₁ to
BP ₂₃ : bipolar transistor, FT _{11 to} FT
₁₃ , FT _{21 to} FT ₂₃ : MOS type transistors, 1
0: semiconductor substrate, 12, 36: well region, 14: field insulating film, 14A, 14B, 14b: gate insulating film, 16, 20: source region, 18, 22: drain region, 26: contact region, 28: collector Area, 30
~ 34: Gate electrode layer.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/088 27/092 F term (reference) 5F038 BH02 BH04 BH06 BH07 BH13 EZ20 5F048 AA02 AB03 AC03 CC01 CC06 CC09 CC10 CC10 CC15 CC19

Claims (6)

[Claims] 1. A semiconductor device having an input terminal for supplying an input signal to a protected circuit, a semiconductor substrate having a first conductivity type, and a second conductivity type opposite to the first conductivity type, and the semiconductor substrate and PN. A well region formed on one main surface of the semiconductor substrate so as to form a junction; a first MOS transistor formed in the well region and having the first conductivity type as a channel conductivity type; and the semiconductor substrate A second MOS type transistor formed on the one main surface outside the well region and having the second conductivity type as a channel conductivity type, and the source of the first MOS type transistor and the second MOS transistor.
The gate of the MOS transistor to the input terminal, the drain of the first MOS transistor to the drain of the second MOS transistor, and the second MOS
An input protection circuit configured to connect the source of the MOS transistor and the semiconductor substrate to a reference potential point and to make the first and second MOS transistors conductive in response to a surge voltage input such as static electricity. 2. The second MOS is provided in the vicinity of the second MOS type transistor on one main surface of the semiconductor substrate.
2. The input protection circuit according to claim 1, wherein a lateral bipolar transistor having a source of the type transistor as an emitter is formed, and a collector of the lateral bipolar transistor is connected to a drain of the second MOS type transistor. 3. A third MOS transistor having a source and a drain self-aligned with a gate is provided in the vicinity of the second MOS transistor on one main surface of the semiconductor substrate, and the third MOS transistor is connected to the second MOS transistor. 3. The input protection circuit according to claim 2, wherein the source and drain of the third MOS transistor are used as an emitter and a collector of the lateral bipolar transistor, respectively. 4. An input terminal for supplying an input signal to a protected circuit, a semiconductor substrate having a first conductivity type, a second conductivity type opposite to the first conductivity type, and the semiconductor substrate and PN. A first well region formed on one main surface of the semiconductor substrate so as to form a junction; a second well region having the first conductivity type and formed on one main surface of the semiconductor substrate; A first MOS transistor formed in the first well region and having the first conductivity type as a channel conductivity type; and a second conductivity type as a channel conductivity type formed in the second well region. A second MOS type transistor having a source of the first MOS type transistor and the second MOS type transistor.
The gate of the MOS transistor to the input terminal, the drain of the first MOS transistor to the drain of the second MOS transistor, and the second MOS
An input protection circuit configured to connect the source of the type transistor and the second well region to a reference potential point, respectively, and to make the first and second MOS type transistors conductive in response to a surge voltage input such as static electricity. 5. The second well in the second well region
5. A lateral bipolar transistor having the source of the second MOS transistor as an emitter is formed in the vicinity of the MOS transistor, and the collector of the lateral bipolar transistor is connected to the drain of the second MOS transistor. Input protection circuit described. 6. The second well region in the second well region
A third MOS type transistor having a source and a drain self-aligned with the gate is formed in the vicinity of the second MOS type transistor so that the source is common to the second MOS type transistor. 6. The input protection circuit according to claim 5, wherein the source and the drain are used as an emitter and a collector of the lateral bipolar transistor, respectively.