JPH02210862A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the operation of a parasitic bipolar transistor and to prevent the generation of a latch-up and the like by a method wherein an element, in which a current is made to flow, is formed in the vicinity of a region, which is formed from the surface of a semiconductor substrate toward the interior of the substrate. CONSTITUTION:A p-type layer 5, which is used as a substrate for an insulated gate field-effect transistor (a MOSFET), and a p-type layer 5' to form an element, in which a current is made to flow, are formed by an ion implantation using polysilicon gates 8 as masks and source regions 6 are similarly formed by diffusion using the gates 8 as masks. After these processes, part of a silicon surface is exposed, platinum is deposited and is transformed into a silicide to form a Schottky junction. For the formation of an electrode 9, such as a source electrode, a substrate electrode or the like, Al is used. Here, the Schottky junction is formed of a silicide electrode 11 and an n-type layer 7 and works as the element, in which a current is made to flow. Thereby, the operation of a parasitic bipolar transistor can be prevented.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor device that constitutes an H-bridge circuit that drives a motor or the like. In particular, the present invention relates to a semiconductor integrated circuit in which an H-bridge circuit composed of MOSFETs is integrated on a semiconductor chip.

[Conventional technology 1 "Technical Digest of Electron Devices Meeting Vol. 33, No. 3, Page 766, 1987"
Electron Devices Meeting
, 33, 3, pp. 766 to 768.1987) A conventional high-current power MO8FET of a high-voltage IC, as shown in J. flows to the source through the n-type layer. Generally, in the case of an inductive load, the drain potential may be lower than the source potential. In this case, current flows through the substrate-drain diode and the p-type substrate-drain diode of the MOSFET. The latter current is p
To lower the potential of the base body below the ground potential due to the potential drop of the mold base resistance. There is a risk that the pn junction for isolation will be forward biased and cause latch-up. Furthermore, as shown on page 768 of the above-mentioned document, the large current power MO8FET of other high voltage ICs has a low resistance n
The small signal elements and logic elements were formed in regions separated by a buried p-type layer. Moreover, since the p-type layer is used at ground potential, parasitic parasitics occur in which the collector of the npn transistor shown in the above-mentioned document 1 and Figure 2 is used as the emitter, the p-type layer for isolation is used as the base, and the n-type layer of the substrate is used as the collector. There was a possibility that the bipolar transistor would be activated. This parasitic bipolar transistor operation is not preferable from the viewpoint of the operation of the semiconductor integrated circuit. Furthermore, in many electronic circuits, a plurality of power MO5FETs are used. For example, in an H-bridge circuit used for driving a motor, two power MO8FETs, a pull-up element and a pull-down element, are required as a basic circuit. In the above-mentioned document, these points were not taken into consideration. Problem to be Solved by the Invention 1 As mentioned above, power MO8F is placed on a high resistance p-type substrate.
When an ET is formed, there is a problem in that the isolation pn junction is forward biased and latch-up occurs, which impedes the original operation of the semiconductor element. In addition, when a power MOSFET is formed on a low-resistance n-type substrate, a parasitic bipolar transistor becomes activated, which not only causes the problem of interfering with the original operation of the semiconductor element, but also causes problems in the H-bridge circuit used for motor opening, etc. There was also a problem that a power MO8FET could not be formed as a pull-down element to be used. That is, if a large power MO8 was formed as a pull-down element in the isolation region, parasitic bipolar transistor operation would easily occur, and the n Due to the resistance of the mold buried layer, non-uniformity occurs in the current flowing through the base-drain diode of the power MO8. The object of the present invention has been made to solve the above-mentioned problems, and the first object is to suppress the operation of parasitic bipolar transistors and prevent the occurrence of latch-up and the like. The other purpose is to completely isolate the power MO from other elements.
5 on the same chip to form a semiconductor drive circuit such as an H bridge. Still another object is to provide a highly efficient, low-cost drive circuit using the semiconductor integrated circuit described above. [Means for Solving the Problems 1] In order to achieve the above object, an element that allows current to flow from the source when the drain potential of the MOSFET becomes lower than the source potential is formed near the drain extraction electrode, and Furthermore, in order to achieve the above object, a region separated from others by a p-type layer is formed on the n-type substrate, a power MO8 is formed in the region, and a p-type layer is formed in the region. By forming an n-type region in contact with the p-type layer and electrically short-circuiting the n-type layer, parasitic bipolar transistor operation is suppressed. Further, when the diode between the base and drain of the power MO8 is forward biased, the hole current injected into the p-type layer for one separation and the potential drop due to the resistance of the p-type layer are made as small as possible. To this end, a current injection element is formed near the external terminal of the isolation p-type layer to reduce the forward bias voltage when the diode between the base and drain of the power MO8 is forward biased. Furthermore, in order to reduce the amount of holes that are minority carriers injected, an element in which p-type and n-type are short-circuited, or a Schottky junction is used as an injection element. In addition, in order to form an efficient and low-cost drive circuit, it is necessary to combine the power MO8 formed on the n-type substrate and the p
The power MOs 8 formed in regions separated by a type layer are used as a pull-up element and a pull-down element, respectively, and the p-type layer for isolation is connected to the drain of the pull-down element. As a result of the above, parasitic bipolar transistor operation can be suppressed, and a highly efficient, low-cost drive circuit can be provided. [Function] Forming the current injection element near the drain terminal, which is the first means of the present invention, reduces the amount of current injected from the substrate to the drain, and therefore has the effect of suppressing fluctuations in the substrate potential. be. The second means of the present invention, which is to short-circuit the drain of the pull-down element and the isolation p-type layer, reduces the amount of holes injected into the isolation p-type layer, and reduces the parasitic bipolar transistor operation. It has the effect of suppressing This is the third means of the present invention. When the diode between the base and drain of the power MO8 is forward biased, forming a current injection element that lowers the forward bias voltage near the external terminal of the isolation p-type layer reduces the potential drop due to parasitic resistance. This has the effect of suppressing parasitic bipolar transistor operation. The fourth means of the present invention, which is to short-circuit the p-type layer and the n-type layer or to use a Schottky junction as the current injection element, similarly reduces the amount of holes injected. effective. Also, a power MO8 formed on an n-type substrate. Power MO8 formed in a region separated by a p-type layer,
It is desirable to use them as a pull-up element and a pull-down element, respectively, from the viewpoint of reducing the loss of the pull-up element, and therefore it is possible to provide a drive circuit with high power utilization efficiency.

【Example】

FIG. 1 shows a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. This embodiment is a MOS that can handle a large current.
It is suitable for configuring a semiconductor integrated circuit including FET. The manufacturing method of the present invention will be explained below with reference to FIG. First, a region 3 in which antimony is diffused from the surface of a lightly doped p-type substrate 1 is formed, and then an n-type layer 7 having a resistivity of 1Ω and a thickness of 9 μm is formed by epitaxial growth. Furthermore, a p-type layer 2 for separating the n-type layer and an n-type layer 4 for connecting the buried layer 3 to the surface electrode are formed by diffusion. After forming a polysilicon gate 8 on a silicon oxide film with an IQ of 3 nm, a p-type layer 5 that will become the base of the 1M08FET and a p-type layer 5' that will form an element into which current flows are formed using the polysilicon gate 8 as a mask. Formed by ion implantation. Source region 6 is similarly formed by diffusion using polysilicon gate 8 as a mask. After the above steps, a part of the silicon surface is exposed, and platinum is deposited and silicided to form a Schottky junction. A1 was used for the electrodes of the source, substrate, etc. Here, the silicide electrode 11 and the n-type layer 7 form a Schottky junction,
Works as an element that allows current to flow. In FIG. 1, when the source is grounded and the drain is operated with an inductive load connected, the drain can be lower than the source potential. In this case, an electron current is injected between the silicide electrode 11 and the n-type epitaxial layer 7 to prevent the drain potential from decreasing. Since the internal potential drop of the Schottky junction is lower than that of the pn junction, no large voltage is applied to the diode between the substrate and the drain, so the current flowing from the substrate to the drain is also reduced and latch-up is prevented. FIG. 2 shows the cross-sectional structure of a second embodiment of the present invention. The manufacturing method of this embodiment is almost the same as that of the first embodiment, but as a current injection element, a p-type In layer 5=,
An n-type N12 was formed, and the p-type layer 5= and the n-type layer 12 were connected by an AI electrode 10. As described above, the collector and base of the npn transistor, which has the n-type layer 12 as the collector, the p-type layer 5z as the base, and the n-type layer 7 as the emitter, are short-circuited, so this transistor operates as a diode, and current flows into the base current. An electron current multiplied by the amplification factor flows through the collector-emitter path of this transistor. Therefore, even if the drain potential drops below the source potential due to an inductive load, the source
There is an np between the drains mainly due to the diode operation described above.
The electron current of the n-transistor flows, and the current between the drain and the substrate is reduced. That is, since the change in the potential of the base body is suppressed to a low level, latch amplifier is prevented. FIG. 3 shows a cross-sectional structure of a third embodiment of the present invention. The manufacturing method of this example will be explained below. First, a lightly doped p-type epitaxial layer 14 having a thickness of 17 μm is formed on a heavily doped n-type substrate 13 . Next, after antimony is diffused from the surface of the p-type layer 14 to form an n-type layer 15.15', an n-type layer 16.162 having a resistivity of 1 pcm and a thickness of 9 μm is formed by epitaxial growth. Furthermore, a p-type layer 20 for separating the n-type layer
, an n-type layer 19 for connecting the buried layer 3 to the surface electrode.
19' are each formed by diffusion. After forming the polysilicon gate 21, the p-type layer 17 that forms the base of the 1M08FET and the element into which current flows are formed.
It is formed by ion implantation using polysilicon gate 21 as a mask. Source region 18 is similarly formed by diffusion using polysilicon gate 8 as a mask. After the above steps, a part of the silicon surface is exposed and the AI
is deposited to form an electrode. In the case of this embodiment, p-type layer 1
7 and the n-type layer 16 form a pn junction and function as a current injection element. The drain of the MOSFET is connected to an electrode 23, the highest potential is applied to the electrode 24, and the ground potential is applied to the electrode 22. In this structure, the parasitic resistances R1°R2,
R1', R2', parasitic bipolar transistor Ql
, Q2, etc. exist. As shown in FIG. 5, when the device of this embodiment is used as a pull-down device in a half-bridge circuit that drives an inductive load, the freewheeling diode D2 is
OSFET substrate-drain diode and p-type layer 17
A pn junction diode consisting of an n-type layer 16 is used. In FIG. 5, an equivalent circuit including parasitic elements when M2 is non-conductive can be expressed as shown in FIG. In FIG. 6, when the drain potential becomes lower than the source potential due to an inductive load, the diode current between the substrate and drain of the MOSFET flows through the resistors R1' and R1 and is supplied from the electrode 23 to the load. In this case, M.O.
If the diode current between the substrate and drain of the SFET is large, the parasitic bipolar transistor Q2 becomes conductive due to the potential drop across the resistor R1'. Therefore, it is desirable to supply the current from the p-type layer 17. However, in this case, the parasitic bipolar transistor Q2 becomes conductive. The current amplification factor of bipolar transistor Q1 must be small. Here, assuming that all the current is supplied through Ql, the following equation holds true as a condition for Q2 not to conduct. R2≦0.7/Icp+R1/hpE(Ql)
"" (1) Here, Icp is the collector current of Ql, and h FE (Ql) is the current amplification factor of Ql. In order for equation (1) to hold regardless of the current, (2
) must hold true. hFE(Ql) < R1/R2 (2)
That is, by setting the constants of the elements as shown in the above equation, it is possible to prevent the parasitic bipolar transistor from operating, thereby providing a highly efficient semiconductor device. FIG. 7 shows a cross-sectional structure of a fourth embodiment of the present invention. The manufacturing method of this embodiment is similar to that of the third embodiment, except that an n-type layer 26 similar to the n-type layer 12 shown in FIG. 2 is further formed as a current injection element. The feature of this embodiment is that unlike the third embodiment, the injection current is not performed using a hole current, but is mainly performed using an electron current. Therefore, Q2 shown in FIG. 6 becomes even more difficult to conduct. In this example, a pn junction was used as the current injection element. As explained in the first embodiment, the use of the Schmitt key junction provides further effects. 8 shows the cross-sectional structure of the fifth embodiment of the present invention. The manufacturing method of this embodiment is the same as that of the third embodiment, but in this embodiment, the fourth embodiment In addition to the above elements, an MO8FET is formed directly on the n-type substrate 27. The MOSFET of the n-type substrate 27 is optimal as a half-bridge pull-up element. FIG. 9 shows an H-bridge type motor drive circuit constructed using two semiconductor devices of the fifth embodiment. Flywheel diode D12. D14 is the pull-down element M12. described in the third to fifth embodiments of the present invention. This is a current injection element formed near the drain of M14. By using this configuration, an efficient and low-cost drive circuit can be provided.

【Effect of the invention】

As described above, by using the semiconductor device of the present invention, the operation of the parasitic bipolar transistor can be prevented, and an efficient and low-cost drive circuit can be provided.

[Brief explanation of the drawing]

1 is a cross-sectional structural diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional structural diagram of a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional structural diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 4 is a cross-sectional structural diagram of a semiconductor device according to an embodiment, and FIG. 4 is an equivalent circuit of a parasitic element in a semiconductor device according to a third embodiment of the present invention. FIG. Fig. 6 is a circuit diagram of an equivalent circuit including parasitic elements of a half-bridge circuit that drives an inductive load, Fig. 7 is a cross-sectional structural diagram of a semiconductor device according to a fourth embodiment of the present invention, and Fig. 8 is a circuit diagram of a semiconductor device according to a fourth embodiment of the present invention. FIG. 9 is a cross-sectional structural diagram of a semiconductor device according to a fifth embodiment of the present invention, and FIG. 9 is a circuit diagram of an H-bridge circuit for driving a motor constructed using the semiconductor device of the present invention. Explanation of symbols 1...p-type substrate, 2...p-type diffusion layer, 3...n-type buried layer, 5...p-type diffusion layer, 6...n-type diffusion layer, 7
... n-type epitaxial layer, 8... polysilicon.
Gate, 9... AI electrode, 11... Silicide layer,
12... n-type diffusion layer, 13... n-type substrate, 14...
-p-type layer, 15...n-type buried layer, 17...p-type diffusion layer, 26...n-type diffusion layer, 27...n-type substrate, 28
...p-type epitaxial layer, Fig. 3 4. Eye 1 Prisoner 2nd Eye Figure 5

Claims (1)

[Claims] 1. The channel region of an insulated gate field effect transistor (abbreviated as MOSFET) exists in a plurality of parts, and the drain current mainly flows from the surface to the inside of the semiconductor substrate. A semiconductor device including a MOSFET supplied through a high-concentration region formed inside the semiconductor substrate, characterized in that an element is formed that causes a current to flow into the vicinity of the region formed from the surface toward the inside of the semiconductor substrate. Semiconductor equipment. 2. The semiconductor device according to claim 1, wherein the element into which the current flows includes a Schottky junction formed on the surface of the n-type layer. 3. In the semiconductor device according to claim 1, an n-type layer is formed within the p-type layer as the element into which the current flows;
A semiconductor device comprising a structure in which a p-type layer and an n-type layer are connected at the surface. 4. The channel region of the insulated gate field effect transistor exists in multiple parts, and the drain current is mainly supplied through the region formed from the surface toward the interior of the semiconductor substrate and the high concentration region formed inside the substrate. A semiconductor device including a MOSFET, in which the semiconductor device is formed on an n-type semiconductor substrate, a first p-type layer separating a component semiconductor element from the n-type semiconductor substrate, and a first p-type layer connected to the p-type layer. a second p-type layer formed from a surface
A second n-type layer for extracting current, a third n-type layer formed from the surface connected to the n-type layer, a second p-type layer formed from the surface, and a second n-type layer formed from the surface. 1. A semiconductor device characterized in that the mold layer is electrically connected on the surface thereof, operates as a current outflow region from the semiconductor element, and forms a current inflow region in the vicinity thereof. 5. The semiconductor device according to claim 4, wherein a third p-type layer is formed within the third n-type layer as a region into which the current flows. 6. The semiconductor device according to claim 4, wherein a Schottky junction is formed on the third n-type layer as the region into which the current flows. 7. In the semiconductor device according to claim 4, a third p-type layer is formed in the third n-type layer as a region into which the current flows, and further a fourth n-type layer is formed in the p-type layer. A semiconductor device characterized in that it is used by forming a third p-type layer and a fourth n-type layer and electrically connecting the third p-type layer and the fourth n-type layer. 8. The semiconductor device according to claim 5, wherein the third p
The current amplification factor of a bipolar transistor in which the type layer is the emitter, the first n-type layer is the base, and the first p-type layer is the collector is determined by the sheet resistance of the first n-type layer and the sheet resistance of the first p-type layer. A semiconductor device characterized by having a resistance ratio smaller than that of the resistance. 9. The semiconductor device according to claim 4, wherein the semiconductor element which is a component of the semiconductor device is a MOSFET having a gate electrode with a mesh structure. 10. The semiconductor device according to claim 4, wherein the semiconductor element which is a component of the semiconductor device is a MOSFET having a gate electrode in a stripe structure. 11. In the semiconductor device according to claim 4, the first semiconductor element as a component is composed of a MOSFET formed in a region separated by the first and second p-type layers, and the second semiconductor element as a component is A semiconductor device, wherein the semiconductor element is a MOSFET formed on an n-type substrate. 12. The semiconductor device according to claim 10, wherein the first
A semiconductor device characterized in that a semiconductor element is used as a pull-down element, and a second semiconductor element is used as a pull-up element. 13. A drive circuit characterized by using the semiconductor device according to claims 1 to 12.