JP2676769B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in the field of semiconductor devices.

The present invention relates to a MOS semiconductor device, and more particularly to a semiconductor device having an insulated gate field effect transistor (hereinafter referred to as a MOS transistor) having improved radiation resistance.

〔Overview〕

According to the present invention, in a semiconductor device having an N-channel type MOS transistor, a high-concentration P-type impurity region is provided in contact with the periphery of a transistor region composed of a source region, a gate region and a drain region of the MOS transistor. By doing so, leakage current between the source and drain regions due to radiation irradiation is eliminated, and radiation resistance is improved.

[Conventional technology]

In recent years, semiconductor integrated circuits have been increasingly used in outer space and around nuclear reactors. A semiconductor integrated circuit used in such an environment suffers various radiation damages and changes in characteristics in a short time, and the function of the integrated circuit is significantly deteriorated, or in the worst case, the function is completely lost. It will disappear. Accumulation of positive charges in the silicon oxide film is known as a characteristic variation of the MOS transistor, and the amount thereof increases in proportion to the square or cube of the thickness of the silicon oxide film.

[Problems to be solved by the invention]

Recently, in silicon gate MOS transistors, a thick oxide film called a field oxide film is mainly used as the isolation method between transistors. However, the thickness of the gate oxide film is reduced in order to secure the threshold voltage and reduce the wiring capacitance. Tens of times. Therefore, when the MOS transistor is exposed to the ionizing radiation, the field oxide film is charged and the substrate below the field oxide film is inverted to lose the isolation effect.

At this time, the leak current l ₁ between the MOS transistors and the leak current l ₂ between the source and drain inside the transistor become problems. Regarding the leak current l _1, it is common to form a high concentration isolation diffusion region around the transistor and cut off the inversion layer of the field oxide film. Regarding the leak current l ₂ , a high-concentration P ⁺ type region is provided at both ends of the transistor region passing between the source and the drain in order to block the leak path between the source and the drain. However, when the radiation dose reaches 1 Mrad (Si), the leak current can no longer be completely suppressed. Hereinafter, this point will be described in detail with reference to the drawings.

FIG. 2 (a) is a plan view of a conventional N-channel MOS transistor, and FIGS. 2 (b) and (c) are x ₁ -x ' ₁ and x ₂ -x' _{2 of} FIG. 2 (a), respectively. It is sectional drawing along. Further, FIGS. 7D and 7E are cross-sectional views taken along the line y ₁ -y ′ ₁ and y ₂ −y ′ ₂ of FIG.

The N-channel type MOS transistor of this conventional example is composed of an N ⁺ type source region 4, an N ⁺ type drain region 5, a gate region 3a, a gate oxide film 2 and a gate electrode 3 made of polycrystalline silicon, and the periphery thereof is a field. It is separated by the oxide film 1. As described above, in order to suppress the leak current l ₂ when receiving the radiation, the high-concentration P ⁺ type regions 7 are provided at both ends of the transistor region through the source and the drain.

When such a MOS transistor is exposed to radiation, as described above, the field oxide film 1 is positively charged, and the P-type silicon substrate 6 below the field oxide film 1 is also inverted to N-type. At this time, for example, as shown in FIG.
Although the N ⁺ type inversion region 8 as shown in (c), (d) and (e) is formed, since the high concentration P ⁺ type region 7 exists.
The N ⁺ type inversion region 8 is cut off, and the leak path shown in FIG. 2A is almost completely suppressed.

However, when the amount of radiation increases and reaches about 1 Mrad (Si), the N ⁺ type inversion region 8 shown in FIGS. 2D and 2E is shown.
The leak path due to the formation of
There is a drawback that the leakage current l ₂ increases and the electrical characteristics of the transistor are significantly impaired.

The object of the present invention is to eliminate the disadvantages mentioned above,
An object of the present invention is to provide a semiconductor device having an N-channel MOS transistor capable of sufficiently withstanding a strong radiation of about 1 Mrad (Si).

[Means for solving the problem]

The present invention relates to an N channel type insulated gate field effect transistor having a source region, a gate region and a drain region formed on the surface of a P type semiconductor region, and a P type semiconductor region surrounding the insulated gate field effect transistor. In a semiconductor device having a field insulating film formed on the surface of the field insulating film, a transistor region composed of a source region, a gate region and a drain region is continuously surrounded in a region surrounded by the field insulating film. A high-concentration P-type impurity region which is formed in contact with the transistor region and which is provided along the gate region and intersects with a gate electrode which is drawn out from the transistor region to the outside is provided.

[Action]

The high-concentration P ⁺ type region is all around the transistor region,
It is provided in contact with it.

Therefore, even if a strong N ⁺ -type inversion region is formed under the field oxide film due to strong radiation irradiation, the high-concentration P ⁺ -type region completely blocks the leak path and the leak path to eliminate the leak current. Is possible.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a plan view of an N-channel type MOS transistor showing an embodiment of the present invention. (B) and (c) of FIG. 3 are x ₁ -x ' ₁ and x _2-of FIG.
It is a sectional view taken along the x _'2. Further, FIGS. 6D and 6E are y ₁ -y ′ ₁ and y ₂ − of FIG.
y _'is a cross-sectional view along _2.

The N-channel type MOS transistor of the present embodiment is provided with an N ⁺ type source diffusion region 4, an N ⁺ drain diffusion region 5, a gate region 3a, a gate oxide film 2 and a gate oxide film 2 provided on one main surface of a P type silicon substrate 6. The gate electrode 3 is made of polycrystalline silicon, and the periphery thereof is separated by the high-concentration P ⁺ type region 7a having an impurity concentration of about 1 × 10 ¹⁷ cm ^-3 and the field oxide film 1.

According to this embodiment, when exposed to radiation, positive charges are accumulated in the field oxide film 1, the P-type silicon substrate 6 thereunder is inverted to N-type, and the N ⁺ -type inversion region 8 is formed. Also, the leakage path of the leakage current l ₂ and high concentration
Since it is completely blocked by the P ⁺ type region 7a, the transistor characteristics are not impaired even if the radiation dose is high.

The feature of the present invention is that, as shown in FIGS. 1A to 1D, the high-concentration P ⁺ type region 7a is provided so as to continuously surround the periphery of the transistor region and contact the transistor region, and the gate electrode 3 The high concentration P ⁺ type region 7a intersects with the gate electrode 3 in the portion where is extracted from the transistor region to the outside.

〔The invention's effect〕

As described above, the present invention has an effect that even if the radiation dose is high, the leak path is completely blocked by the high-concentration P ⁺ type region, no leak current is generated, and the radiation resistance is significantly improved.

Further, according to the present invention, the radiation resistance can be improved without giving any special consideration to the method for forming the field oxide film, and a semiconductor device including a highly reliable N-channel MOS transistor can be provided. The effect is great.

[Brief description of the drawings]

FIG. 1A shows an N-channel type MOS according to an embodiment of the present invention.
A plan view of the transistor, FIGS. 1 (b) and (c) are cross-sectional views along x ₁ -x ' ₁ and x ₂ -x' ₂ of FIG. 1 (a), FIG. 1 (d) and FIG. (E) is the first
Y ₁ -y _'1 and y _{2 -y'} sectional view along ₂ of FIG. (A). FIG. 2A is a plan view of a conventional N-channel type MOS transistor, and FIGS. 2B and 2C are second views, respectively.
FIG. 2A is a sectional view taken along line x ₁ -x ′ ₁ and x ₂ -x ′ ₂ of FIG.
₃ is a cross-sectional view taken along line y ₁ -y ′ ₁ and y ₂ -y ′ ₂ . 1 ... field oxide film, 2 ... gate oxide film, 3 ...
Gate electrode, 3a ... Gate region, 4 ... N ⁺ type source region, 5 ... N ⁺ type drain region, 6 ... P-type silicon substrate, 7, 7a ... High-concentration P ⁺ type region, 8 ... N ⁺ type inversion region,
...... Leak path.

Claims (1)

(57) [Claims] 1. An N-channel insulated gate field effect transistor having a source region (4), a gate region (3a) and a drain region (5) formed on the surface of a P-type semiconductor region (6), and A semiconductor device comprising a field insulating film formed on the surface of the P-type semiconductor region (6) surrounding an insulated gate field effect transistor, wherein the source region and the gate are within the region surrounded by the field insulating film. A transistor region composed of a region and a drain region, continuously surrounding and in contact with the transistor region, and intersecting with a gate electrode (3) provided along the gate region and drawn out from the transistor region. A semiconductor device comprising the formed high-concentration P-type impurity region (7a).