JPH0783046B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same,
In particular, the present invention relates to a radiation-resistant MIS type semiconductor integrated circuit device and a manufacturing method thereof.

[Conventional technology]

Generally, the element isolation of a MIS type semiconductor integrated circuit device is formed by thick silicon oxide film 13 partially buried in a selectively formed semiconductor substrate and a high concentration P type channel stopper region thereunder as shown in FIG. Performed by 12. In FIG. 4, 11 is, for example, a P-type semiconductor substrate, 12 is a high-concentration P-type impurity layer, 13 is a thick field oxide film, 14 is a gate oxide film, 15a and 15b are N ⁺ diffusion layers belonging to different elements, 16 Is an interlayer insulating film, and a wiring conductor pattern 17 is formed thereon. In such a structure, the active area
The separation of 15a and 15b is performed by preventing the formation of a channel by inverting the substrate surface under the field oxide film 13 in the state where an appropriate voltage is applied to the wiring conductor 17. This condition is that the insulating films 13 and 14 that normally become the gate insulating film of the parasitic MOS transistor are much thicker than the gate oxide film 14 of the active transistor, and the silicon substrate surface under the field insulating film 13 that becomes the gate insulating film of the parasitic transistor. The impurity concentration of is guaranteed by the higher concentration by the high concentration region 12. For example, the field oxide film 13 is 1 μm and the interlayer insulating film 16 is 1 μm.
If the concentration of the high impurity region 12, which is the μ, P ⁺ type channel stopper region, is about 10 ¹⁷ cm ^-3 , the channel length is 2 μm.
It is estimated that the current flowing through the parasitic MIS transistor having m and a channel width of about 50 μm is 10 ⁻²⁰ A or less even when 5 V is applied to the wiring conductor 17. Therefore, in the normal operating voltage range, the leakage due to the parasitic MOS transistor as shown in FIG. 5 is not a problem. That this, the semiconductor substrate 11 and the N ⁺ -type 15a region in Figure 4 together with 0V, the N ⁺ -type 1
This is a leak current flowing between 15a and 15b when +5 V is applied to the 5b region and the wiring conductor (gate electrode) 17.

[Problems to be solved by the invention]

However, ionizing radiation (γ rays, α
(Electron beam, electron beam, etc.), holes move to the silicon-oxide film interface in the electron-hole pairs generated in the oxide film,
Since many positive holes are trapped near the interface, positive fixed charges are accumulated in the oxide film, and in the case of Nch device, an electric field in the direction of inverting the silicon substrate is generated. As a result, as shown in FIG. 5, the leakage current of the parasitic MOS transistor surely increases as the absorbed dose increases. For example, in the case of the parasitic MOS transistor having the structure described above, the leakage current is 1 × 10 ⁵ rad ( The absorbed dose of Si) increases about 10 orders of magnitude under the same conditions as above. Such an increase in leakage current not only causes deterioration of the characteristics of the active transistor alone, but also seriously affects the operation characteristics of the integrated circuit device. As a countermeasure against this, a method of increasing the concentration of the impurity layer 12 under the field oxide film 13 in FIG. 4 so as to prevent surface inversion is caused, but the impurity layer 12 must be formed before the field oxidation. Field oxidation at high temperature for a long time is not suitable for increasing the concentration of the impurity layer 12. Further, when the impurity layer 12 is formed by the ion implantation method, the higher the dose, the more the surface defects are generated after the field oxidation, so that the diffusion layers 15a and 15b and the impurity layer 12 are formed.
The junction leakage increases. Further, even if the concentration of the impurity layer 12 can be increased, there is a problem that the junction breakdown voltage between the diffusion layers 15a and 15b and the impurity layer 12 is lowered. That is, in the structure as shown in FIG. 4, there are various kinds of restrictions for increasing the concentration of the impurity layer 12, and the upper limit is about 10 ¹⁸ cm ⁻³ .
With such a concentration, the leakage of the parasitic MOS transistor caused by the radiation irradiation cannot be prevented. At most, the leak level can be improved by 1 to 2 digits. That is, the conventional element isolation structure has a drawback that the leakage current significantly increases when it is irradiated with radiation.

The present invention eliminates the above drawbacks, and has a radiation-resistant MIS
Type semiconductor integrated circuit device and its manufacturing method.

[Means for solving problems]

A semiconductor integrated circuit device according to a first aspect of the present invention is a plurality of second-type conductivity type (isolated by element isolation regions formed on a semiconductor substrate of the first-type conductivity type (P-type). N
A semiconductor integrated circuit device having active regions, which are source and drain regions of, for example, an insulated gate field effect transistor (hereinafter referred to as IGFET), which has a dielectric type), the element isolation region is a thick insulating film partially embedded in a substrate. By having a first-conductivity-type high-impurity-concentration impurity region formed separately from the pre-light active region.

The semiconductor integrated circuit device according to the second aspect of the present invention is characterized in that an element isolation region is formed in an impurity region of the second type conductivity type formed in an island shape on a semiconductor substrate having the first type conductivity type. A first member belonging to each of a plurality of elements formed separately
In a semiconductor device having active regions such as source and drain regions of an IGFET having a second conductivity type, a second conductivity type formed in the element isolation region by being separated from the active region by a thick insulating film. And an impurity region having a high impurity concentration.

Further, in the method of manufacturing the MIS type semiconductor integrated circuit device of the third invention of the present invention, a device is formed by selectively forming an oxide film on the semiconductor substrate having the first type conductivity by a selective oxidation method. A step of partitioning an active region and a part of the element isolation region and forming a thin oxide film on the semiconductor substrate in the part of the part; and a region having the thin oxide film for element isolation A step of coating a mask material for ion implantation on the upper surface, and using the mask material as a mask, ion-implanting a second-type conductivity type impurity into an active region where the device is formed, and a second-type conductivity-type diffusion region And a step of removing the mask material and covering a region where the device is formed with a mask material, and using the mask material as a mask, a thin oxide film for element isolation of the first type conductivity type impurity. Ion injection into the area with And configured to include a step of forming a diffusion region of a high impurity concentration of the first type of conductivity type.

Further, according to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor integrated circuit device, comprising: a semiconductor substrate having a first type conductivity type substrate region and an island type second type conductivity type impurity region; A step of selectively forming a thick oxide film on the surface of the region by a selective oxidation method to partition an active region where a device is formed and a region having a thin oxide film for element isolation, and a thin step for element isolation A step of covering a region having an oxide film with a mask material for ion implantation, and using the mask material as a mask, ion-implanting a first type conductivity type impurity into an active region where the device is formed, A step of forming a conductive type diffusion region, a step of removing the mask material and covering a region in which the device is formed with a mask material, and using the mask material as a mask to separate the second type conductivity type impurity into elements. Area with a thin oxide film for Configured and forming a diffusion region of a very high impurity concentration of implanted second type conductivity type.

In the method of manufacturing a semiconductor integrated circuit device according to the fourth aspect of the invention, the step of forming a diffusion region having an extremely high impurity concentration in the element isolation region is performed by another process, such as a drain region of a transistor The present invention can be effectively implemented by performing the same process as the impurity diffusion of the source region.

Radiation such as α-rays has a strong permeability to silicon dioxide and silicon, and if silicon dioxide is thick, more ionization phenomenon occurs and therefore more fixed positive charge is generated. A fixed positive charge is generated in the case of thin silicon dioxide, but less than in the case of a thick silicon dioxide film. Considering this fact and the fact that a higher concentration of impurities can be formed under the thin silicon oxide film as described above, the combination of the thin insulating film of the present invention and the high impurity concentration region below the α-ray It becomes an effective separation area when irradiated with radiation such as. Further, in this case, since the fixed positive charge is a problem, the high impurity concentration region is effective for separating the P type N type regions, such as N type source and drain regions, which belong to different elements. On the other hand, since the high impurity concentration region is separated by the element region by the thick insulating film, there is no problem of reduction in breakdown voltage. Considering only the problem of breakdown voltage, the high impurity concentration region may not be limited to the P type. The thick insulating film partially embedded in the substrate is used for partitioning the element region and the high impurity region, and also has a separating action when the α-ray is irradiated together with the impurity region below it, that is, the conventional channel stopper region. To do.
On the other hand, since the thin insulating film on the high-impurity region of the present invention has the same predetermined threshold voltage regardless of the film thickness of the interlayer insulating layer thereover, or when the high-impurity region is formed by ion implantation or the like. It is also necessary to prevent damage to the semiconductor substrate. Considering the above matters, the concentration of the high impurity concentration region of the present invention is 5 × 10 ¹⁸ to 10 ²⁰ atoms / cm ³ , the thickness of the thin silicon oxide film thereon is 100Å to 1000Å, and the thickness of the thick insulating film on both sides is The film thickness is 0.5 to 1.0 μm, and the concentration of the impurity region below that, that is, the region corresponding to the conventional channel stopper region, is 5 ×.
A preferable range is 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ .

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 (A) is a side view showing the structure of one embodiment of the present invention,
FIG. 1 (B) is a cross-sectional view taken along the line BB 'in FIG. 1 (A). In FIG. 1 (A), illustration of the wiring conductor 17 and the interlayer insulating film 16 of FIG. 1 (B) is omitted.
In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals.

In Figure 1, a semiconductor substrate 11 of P-type, n ⁺ -type source and drain regions 15a, first IGFET100 the N-channel type having a 15a and the gate electrode 21a is formed, also, n ⁺ -type source, An N-channel type second IGFET 200 having the drain regions 15b, 15b and the gate electrode 21b is formed. In these IGFETs, the electrode wiring to the source and drain regions and the lead wiring to the gate electrode are not shown. These IGFETs are separated by the structure shown in FIG. Then, this insulation separation structure surrounds each IGFET as shown in FIG.

As shown in FIG. 1 (B), this partial structure has a width of 2
a thick silicon dioxide film 13b, 13b partially buried in a substrate having a thickness of μm and a thickness of 1 μm, and a P-type region 12 having a concentration of 8 × 10 ¹⁴ atoms / cm ³ and located under the thick silicon dioxide film 12, 12 and
1 × 10 ¹⁹ atom which is provided on the semiconductor substrate between the thick silicon dioxide films and has a higher impurity concentration than the P ⁺ type region 12
It consists of a P ⁺⁺ -type region 18 with s / cm ³ and a thin silicon dioxide film 20 above it with a thickness of approximately 800Å. This P ^{+ +} type region 18 has a width of 2 μm and surrounds each grating (IGFET) as shown in FIG. 1 (A). Here under the thick insulating film 13a
The P ⁺ region 12 or the conventional channel stopper region can be omitted. The concentration of the p ⁺⁺ diffusion layer 18 is an inversion layer even positive charge is accumulated in the oxide film during the irradiation order to be 2-3 orders of magnitude higher than the concentration of the p ⁺ layer 12 under the field oxide film is not formed, the parasitic leakage Is effectively blocked. Also p ⁺⁺ diffusion layer 1
8 and n ⁺ diffusion layer (source, drain) 15a in the active region and
Since it is not in direct contact with 15b, there is no concern about the breakdown voltage.
For example, the concentration of n ⁺ type source and drain regions is 5 × 10 ¹⁹
At atoms / cm ³ , if the p ⁺⁺ region 18 is in direct contact, the breakdown voltage will be 5 V or less, which causes a problem in operation. However, as in this embodiment, the p ^{+ +} region 18 is distant and the p ⁺ region 12 of 1 × 10 ¹⁷ atoms / cm ³ is in contact therewith, so that the breakdown voltage is 20 V and there is no problem in operation.

2 (A) to 2 (C) are cross-sectional views shown in the order of steps for explaining the manufacturing method of the embodiment of the present invention.

First, as shown in FIG. 2 (A), a thick silicon dioxide film (field oxide film) partially buried in the substrate by thermal oxidation using a normal silicon nitride film as a mask on one main surface of the p-type semiconductor substrate. 13a and 13b are formed. Before the thermal oxidation step, a button is introduced into the substrate portion where the films 13a and 13b are formed, so that the p ⁺ region 12 is formed under the films 13a and 13b. Then, on the semiconductor substrate on which the thick silicon dioxide film is not formed, on the element region, that is, the region where the IGFET is formed and the region where the p ^{+ +} type region is formed later,
After removing the silicon nitride film, thermal oxide films 14 and 20 are formed respectively. The films 14 and 20 may be formed in different thicknesses in different steps. Next, a mask material such as aluminum is attached to the surface, and then patterning is performed to cover the region having the thin oxide film 20 for element isolation with the ion implantation mask material 19a.

Then, as shown in FIG. 2B, n-type impurities such as arsenic are implanted into the active region by an ion implantation method to form n diffusion layers 15a and 15b to be the source and drain regions of the IGFET. Of course, in this case, the silicon gate electrode and other portions of the field insulating films 13a and 13b are also masked. After that, the mask material 19a is removed, and the ion implantation mask material 19b is formed after deposition and patterning of aluminum or the like so as to mask the active region where the n ⁺ diffusion layers 15a and 15b are formed.
And a p-type impurity such as boron is implanted into the element isolation region having a thin oxide film by an ion implantation method to obtain a p ⁺⁺ diffusion layer 18 as shown in FIG. 2 (C). After that, when the mask material 19b such as aluminum is removed, FIG. 2 (C)
Is obtained, and an interlayer insulating film and a wiring pattern are formed on it to obtain the structure of this embodiment shown in FIG.

According to this manufacturing method, the p ⁺⁺ diffusion layer (p ⁺⁺ separation layer) is not formed before the field oxidization, and the stacking faults generated during the field oxidization are also affected by the thermal diffusion during the field oxidization at high temperature for a long time. ⁺ There is no need to worry about a decrease in concentration, and when the present invention is used in a complementary MIS type semiconductor integrated circuit device, it may be performed by the same method after forming a well, and the source of the Nch transistor and the Pch transistor may be used. Since it is sufficient to form a diffusion layer for element isolation when forming the drain diffusion layer, it is not necessary to newly add a step of forming the diffusion layer.

In addition, in the above manufacturing method, the formation of the n ⁺ diffusion layer is performed prior to the formation of the p ⁺ diffusion layer, but even if this is reversed, it does not matter and the conventional process is not changed. It is possible to use the invention.

FIG. 3 (A) shows a plan view of another embodiment of the present invention.
FIG. 3B is a sectional view taken along line BB ′ in FIG.

In FIG. 3, the same functions as those in FIG. 1 are designated by the same reference numerals. The connection electrode wiring is omitted as in FIG. Also, the relationship between the interlayer insulating layer and the metal conductor thereon is the same as in FIG. 1 and is therefore omitted. In this embodiment, an island-shaped P-type well 31 is formed on an N ^- type semiconductor substrate, a plurality of N-channel type IGFETs are formed therein, and the isolation region of the present invention is used for insulation separation between the plurality of N-channel type IGFETs. Is provided. That is, the P-type well 31 may be considered as the P-type substrate 11 of FIG. On the other hand, in the N-type well 32, a plurality of P-channel type IGs having P-type source / drain regions 40, 40 and a silicon gate electrode 41 on the gate insulating film 42 are provided.
FET is formed. However, only one of them is shown. This P-channel type IGFET is isolated by a thick silicon dioxide film 13 embedded in the substrate. In this embodiment, when the p ^{+ +} type region 18 for separating the N channel type IGFET is formed by the method as shown in FIG. 2, the source and drain regions 40, 40 of the P channel type IGFET are simultaneously formed.
Can be formed. At this time, the gate electrode 41 and the surrounding field insulating film 13 are used as a mask by a normal silicon gate process. By this method, the P channel type source / drain regions 40, 40 and the p ⁺⁺ type region 18 of the present invention are simultaneously formed at the same concentration and the same depth.
The N-type well 32 can be omitted in this embodiment.

〔The invention's effect〕

As described above, according to the present invention, it is possible to place an extremely high-concentration parasitic MOS leak prevention layer in the element isolation region and manufacture a MIS semiconductor integrated circuit device in which parasitic MOS leak does not occur even when receiving radiation irradiation. It becomes possible to do.

[Brief description of drawings]

1 (A) and 1 (B) are a plan view and a partial structural sectional view of an embodiment of the present invention, and FIGS. 2 (A) to 2 (C) illustrate a manufacturing method of the embodiment of the present invention. 3A to 3B are plan views and cross sectional views showing another embodiment of the present invention, and FIG. 4 is a conventional semiconductor integrated circuit device having an element isolation structure. FIG. 5 is a sectional view showing the absorbed dose dependency of the leakage current of the parasitic MOS of the conventional structure. 11 …… p type semiconductor substrate, 12 …… p ⁺ type impurity layer, 13,13a, 1
3b …… Field oxide film, 14,42 …… Gate oxide film, 15
a, 15b …… n ⁺ diffusion layer, 16 …… interlayer insulation film, 17 …… wiring conductor, 18 …… n ⁺⁺ diffusion layer (separation layer), 19a, 19b …… ion implantation mask material, 30 …… N ^- -type semiconductor substrate, 31 ...... P-type well, 32 ...... N-type well, 40 ...... p ⁺ diffusion layer, 21a, 21b, 41 ...
… Silicon gate electrode.

Claims (5)

[Claims] 1. A plurality of first isolation regions separated by an element isolation region in a second type conductivity type impurity region formed in an island shape on a semiconductor substrate having a first type conductivity. In a semiconductor integrated circuit device having an active region having a second conductivity type, the element isolation region has a second impurity concentration of a second conductivity type having a higher impurity concentration than the impurity region formed separately from the active region. A semiconductor integrated circuit device comprising: a region, a first insulating film on the high-concentration region, and a thick insulating film located between the first insulating film and the active region. 2. The semiconductor integrated circuit device according to claim 1, wherein the conductivity type of the first type is N type and the conductivity type of the second type is P type. 3. A thick oxide film is selectively formed by a selective oxidation method on a semiconductor substrate having a first conductivity type, and thereby a part of an activation region and an element isolation region where a device is formed is formed. Forming a thin insulating film on the semiconductor substrate in the region which constitutes the part and which constitutes the part; a step of coating the thin insulating film with a mask material for ion implantation; Forming a diffusion region of the second conductivity type by ion-implanting a second conductivity impurity as a mask into a predetermined portion of the active region where the device is formed;
A step of removing the mask material and covering an active region where the device is formed with a mask material; and using the mask material as a mask, a region of the thin insulating film for isolation of a first type conductivity type impurity And ion implantation to form a diffusion region of the first conductivity type having a high impurity concentration, the method for manufacturing a semiconductor integrated circuit device. 4. A semiconductor substrate having a first-type conductivity type and island-shaped second-type conductivity-type impurity regions formed on the surface of the island-shaped region of the semiconductor substrate are selectively thickened by a selective oxidation method. A step of forming an oxide film to partition an active region where a device is formed and a part forming a part of an element isolation region, and forming a thin oxide film on a part of the semiconductor substrate forming the part; A step of covering a region having a thin oxide film with a mask material for ion implantation, and ion-implanting a first type conductivity type impurity into a predetermined portion of an active region in which the device is formed by using the mask material as a mask. A step of forming a diffusion region of a first conductivity type, a step of removing the mask material and covering a region where the device is formed with a mask material, and a second conductivity type impurity using the mask material as a mask The thin oxide for element isolation Ions are implanted in a region having a second
And a step of forming a diffusion region of a high conductivity type of a certain conductivity type, the method of manufacturing a semiconductor integrated circuit device. 5. A step of forming a diffusion region having a high impurity concentration of the second conductivity type of the element isolation region is performed in an active portion of the first conductivity type of the semiconductor substrate where the island region is not formed. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the step of forming an impurity region of the second conductivity type in a predetermined portion of the region is performed at the same time.