JPS625654A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an MIS type semiconductor integrated circuit device having radiation resistance by forming a P-type high density impurity region separated from an active region by a thin insulating film buried partly in a substrate on an element separating region. CONSTITUTION:Thick silicon dioxide films 13a, 13b partly buried in a P-type semiconductor substrate are formed on the substrate, and thermal oxide films 14, 20 are formed on a region formed with an IGFET and a P<++> type region. Then, a mask material is bonded to the surface, patterned, and a region having a thin oxide film 20 is coated with a mask material 19a. Then, an N-type impurity is implanted to an active region to form N-type diffused layers 15a, 15b. Then, the material 19a is removed, a mask material 19b is formed to mask the active region formed with N<+> type diffused layers 15a, 15b and when a P-type impurity is implanted to an element separating region having a thin oxide film, a P<++> type diffused layer 18 is obtained. Then, the material 19b is removed, and an interlayer insulating film and a wiring pattern are formed. Thus, a high density leakage preventive layer can be placed on the element separating region to prevent a parasitic MOS leakage even if a radioactive ray is emitted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof;
In particular, the present invention relates to a method for manufacturing an MIS type bovine conductor integrated circuit device having radiation resistance.

[Conventional technology]

Generally, element isolation in a MIS type semiconductor integrated circuit device is performed by forming a thick silicon oxide film 13 partially buried in the semiconductor substrate and a heavily doped P-type channel stopper region thereunder, as shown in FIG. It is carried out by 12. In FIG. 4, llF'i, for example, a P-type semiconductor substrate,
12 is a high-concentration P-type impurity layer, 13 is a thick field oxide film, 14 is a gate oxide film, 15a and 15b are N+ diffusion layers belonging to different elements, 16 is an interlayer insulating film, and wiring is formed on top of it. A conductor pattern 17 is formed. In such a structure, the active regions 15a and 15b are separated to prevent the substrate surface under the field oxide film 13 from being inverted and forming a channel when an appropriate voltage is applied to the wiring conductor 17. This is done by keeping the

This condition is that the insulating films 13 and 14, which are normally the gate insulating films of the parasitic MOS transistors, are much thicker than the gate oxide film 14 of the active transistor.

The impurity concentration on the surface of the silicon substrate under the field insulating film 13, which serves as the gate insulating film of the parasitic transistor, is guaranteed by being reduced to a high concentration υ by the high concentration region 12. For example, the field oxide film 13 is 1 μm thick, fi1
The interlayer film edge film is 16 μm thick, and the concentration of the high impurity region 12, which is a P" type channel stopper region, is ~10'!-"
channel length 2μm, channel width 50μm
The current flowing through the parasitic M/S transistor of about m is estimated to be at a level of IQ-20A or less even if 5μ is applied to the wiring conductor 17. Therefore, in a normal operating voltage range, leakage caused by a parasitic MO8 transistor as shown in FIG. 5 does not pose a problem. That is, in FIG. 4, both the semiconductor substrate 11 and the N+ type 153 region are OV, and the N
+ to the + type 15b region and the wiring conductor (gate electrode) 17
This is the leakage current flowing between 15a and 15b when 5V is applied.

[Problem that the invention seeks to solve]

However, when such a structure is irradiated with ionizing radiation (gamma rays, alpha rays, electron beams, etc.), electrons generated in the oxide film -
Holes in hole pairs move to the silicon-oxide film interface and are captured by hole traps distributed in large numbers near the interface, so positive fixed charges accumulate in the oxide film, and in the case of Nch devices, the silicon substrate A 1H field is generated in the direction that reverses the . As a result, the leakage current of the parasitic MO8) transistor steadily increases as the absorbed dose increases, as shown in Figure 5. For example, in the case of the parasitic MO8) transistor with the structure described above, the leakage current t:t The absorbed dose of I O' rad (Si) increases by about 10 orders of magnitude under the same conditions as above. Such an increase in leakage current does not simply cause deterioration of the individual characteristics of the active transistor, but also seriously affects the operating characteristics of the integrated circuit device.

A possible countermeasure to this problem is to increase the concentration of the impurity layer 12 under the field oxidation M13 in FIG. 4 to make surface inversion less likely to occur, but the impurity #12 must be formed before the field oxidation. Field oxidation at high temperatures and over long periods of time is not suitable for increasing the concentration of the impurity layer 12. Furthermore, when the impurity layer 12 is formed by ion implantation, surface defects occur significantly after field oxidation, such as when the impurity layer 12 is formed at a high dose.
Junction leakage between b and impurity Wi 12 increases. Furthermore, even if the impurity layer 12 can be made highly concentrated, the diffusion layer 15
A problem arises in that the junction breakdown voltage between a, 15b and the impurity layer 12 is reduced. In other words, in the structure shown in FIG. 4, there are various restrictions on increasing the concentration of the impurity layer 12, and in general,
The upper limit is an impurity concentration of tscrrL-'. At this level of concentration, leakage of the parasitic MOS transistor caused by radiation irradiation cannot be prevented. At most, an improvement of one to two orders of magnitude can be expected in terms of leakage level. That is, the conventional element isolation structure has the drawback that leakage current increases significantly when exposed to radiation.

The present invention eliminates the above drawbacks and provides radiation-resistant MI
An object of the present invention is to provide an S-type semiconductor integrated circuit device and a method for manufacturing the same.

[Means for solving problems]

A semiconductor integrated circuit device according to a first aspect of the present invention has a plurality of second conductivity type (P type) formed on a semiconductor substrate having a first conductivity type (P type) and separated by an element isolation region. N
In a semiconductor integrated circuit device that includes an active region that is the source and drain regions of an insulated gate field effect transistor (hereinafter referred to as IGFgT) having a type of (by having an impurity region of high impurity concentration of the first conductivity type formed separately from the pre-cut active region).

Further, in the semiconductor integrated circuit device of the second aspect of the present invention, an element isolation region is provided in an island-like impurity region of a second conductivity type formed on a semiconductor substrate having a first conductivity type. A first element belonging to each of the plurality of elements formed separately.
In a semiconductor device having an active region, which is a source and drain region of an IGF'ET, for example, having a conductivity type of a second type, the element isolation region has a conductivity type of a second type, which is formed separated from the active region by a thick insulating film. It is configured by having an impurity region of a conductive type and having a high impurity concentration.

Further, in the method for manufacturing an MIS type semiconductor integrated circuit device according to the third aspect of the present invention, an oxide film is selectively formed on a semiconductor substrate having a first conductivity type by a selective oxidation method to form a device. A step of dividing a region constituting a part of an active region and an element isolation region, and forming a thin oxide film on a semiconductor substrate in the region constituting the part, and a region having the thin oxide film for element isolation. A step of covering the top with a mask material for ion implantation, and using the mask material as a mask, ions of a second conductivity type impurity are implanted into the active region where the device is formed, and a diffusion region of the second conductivity type is formed. a step of forming;
a step of removing the mask material and covering the region where the device is to be formed with a mask material, and using the mask material as a mask, ion implantation of a first conductivity type impurity into a region having a thin oxide film for element isolation; and a step of forming a diffusion region of high impurity concentration of type 1 conductivity type. An active region in which a device is formed by selectively forming a thick oxide film by a selective oxidation method on the surface of a core island region of a semiconductor substrate having a semiconductor substrate region and an island-like second conductivity type impurity region. and a region provided with a thin oxide film for element isolation; a step of covering the region having the thin oxide film for element isolation with a mask material for ion implantation; A step of ion-implanting a first conductivity type impurity as a mask into the active region where the device is formed to form a first conductivity type diffusion region, and removing the mask material to form the region where the device is formed. A step of covering the substrate with a mask material, and using the mask material as a mask, ions of a second conductivity type impurity are implanted into a region having a thin oxide film for element isolation to form an extremely high impurity concentration of the second conductivity type. and forming a diffusion region.

In the method for manufacturing a semiconductor integrated circuit device according to the fourth aspect of the invention, the step of forming a diffusion region with an extremely high impurity concentration in the element isolation region may be performed by using another method for diffusing impurities of the same conductivity type, such as the drain of a transistor. The present invention can be effectively carried out by performing the impurity diffusion in the region and the source region in the same step.

Radiation such as alpha rays is highly transparent to silicon dioxide and silicon, and the thicker the silicon dioxide, the more ionization phenomena occur, and therefore the more fixed positive charges are generated. Although fixed positive charges are generated in the case of thin silicon dioxide films, they are smaller than in the case of thick silicon dioxide films. Considering this and the fact that a higher impurity concentration can be formed under a thin silicon oxide film as mentioned above, the combination of the thin insulating film of the present invention and the high impurity concentration region below it is α It becomes an effective separation area when radiation such as a line is irradiated. Furthermore, in this case, since fixed positive charges are a problem, the high impurity concentration region is effective for separating P-type and N-type regions, such as N-type source and drain regions, which belong to different elements. On the other hand, since this high impurity concentration region is separated from the element region by a thick insulating film, the problem of a decrease in breakdown voltage is eliminated. If only this problem of breakdown voltage is considered, the high impurity concentration region need not be limited to P type. A thick insulating film partially buried in the substrate is used to partition the element region and the above-mentioned high impurity region.
In addition, together with the impurity region thereunder, that is, the conventional channel stopper region, it also performs a separating action when irradiated with alpha rays. On the other hand, the thin insulating film on the high impurity region of the present invention maintains the same predetermined threshold voltage regardless of the thickness of the interlayer insulating film above it, and when forming the high impurity region by ion implantation, etc. This is also necessary to prevent damage to the semiconductor substrate. Considering the above matters, the concentration of the high impurity concentration region of the present invention is 5×10” to 1 oo.

, 1torns/α3, the thickness of the thin silicon oxide film on it is l OOA ~ 100OA, the thickness of the thick insulating film on both sides ido, 5 ~ 1.0 μm, the impurity region below it (i.e. conventional channels) -y The concentration of the area corresponding to the bar area is 5×1016 to 1×1O! ″d t oms
/cy*” is a preferable range.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(A) is a plan view showing the structure of an embodiment of the present invention, and FIG. 1(B) is a sectional view taken along the line BB' in FIG. 1(A). In addition, in Figure 1 (5), Figure 1 (B)
Wiring conductor 17. Illustration of the interlayer insulating film 16 is omitted. In FIG. 1, parts corresponding to the same parts as in FIG. 4 are designated by the same reference numerals.

In FIG. 1, a P-type semiconductor substrate 11 is provided with an n+ type source, drain regions 15a, 15a, and a gate electrode 2.
N-channel type first IGFETloo with 1a
is formed, and n-type source and drain regions 15b are formed.
, 15b and a gate electrode 21b. In addition, electrode wiring to the source and drain regions in these IGF'ETs.

The drawing of the lead wiring to the gate electrode is omitted. These IGFgTs are separated by a structure as shown in ) in FIG. This insulation isolation structure surrounds each IGFHT as shown in FIG. 1 (N).

Referring to Figure 1 (Bl), this separation structure has two rings in each ring.
thick silicon dioxide films 13b, 13b partially embedded in a substrate with a thickness of 1 μm and 8×10” atoms/
A P+ type region 12.12 having a concentration of α3 and located under a thick silicon dioxide film, and a P + type region 12.12 provided in the semiconductor substrate between this thick silicon dioxide film and having a higher impurity concentration than the P type region 12. IXIO” atoms /
P+1 region 18 with “an” and about 80OA above it
The silicon dioxide film 20 is made of a thin silicon dioxide film 20 having a thickness of . This p++ type region 18 has a width of 2 μm and surrounds each element (IGPET) as shown in the first row. Here, the P+ region 12 under the thick insulating film 13a, that is, the conventional channel stopper region can be omitted. p++
Since the concentration of the diffusion layer 18 can be 92 to 3 orders of magnitude higher than the concentration of the p+ layer 12 under the field oxide film, an inversion layer is not formed even if positive charges accumulate in the oxide film during irradiation, and parasitic leakage is effectively prevented. thwarted. In addition, the p' diffusion layer 18 and the active region n
If the p+ region 18 is not in direct contact with the + diffusion N (source, drain) 15a and 15b, but is in direct contact with it, the withstand voltage will be 5 V or less, causing an operational problem.

However, in this embodiment, the p+ region is 18 apart, and as a result, I x 1017 atoms /
c! Since the P+ region 12 of "rL" is in contact with it, the withstand voltage is 2
Since it is 0V, there is no problem in υ operation.

FIGS. 2(N-(C)t) are cross-sectional views showing the steps in order to explain a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 2 (tA), a thick silicon dioxide film (field oxide film) 13a is partially buried in the substrate by thermal oxidation using an ordinary silicon nitride film as a mask on one main surface of the p-type semiconductor substrate. , 13b. Note that before this thermal oxidation step, the acid film 13a is formed.

By introducing a button in the substrate portion where 13b is formed, a P+ region 12 is formed under the films 13a and 13b. After removing the silicon nitride film, a thermal oxide film 14 is formed on the semiconductor substrate on which the thick silicon dioxide film is not formed, on the element region, that is, the region where the IGFET is to be formed, and on the region where the p+ type region will be formed later. .2
0 respectively. These films 14 and 20 (!-) can be made to have different thicknesses in separate steps. Next, a mask material such as aluminum is attached to the surface, and then patterned and a thin oxide film for element isolation is formed using an ion implantation mask material 19a. Coat the area with membrane 20.

Next, as shown in FIG. 2(B), an n-type impurity such as arsenic is implanted into the active region by ion implantation to form the IGFE.
n diffusion layer 15a, 1 which becomes the source and drain region of T
Form 5b. Of course, in this case, the silicon gate electrode and the field insulating film 13a.

Other parts of 13b are also used as masks. After that, the mask material 19a is removed, and this time the n+ diffusion layer 15a is formed.

An ion implantation mask material 19b is formed after depositing aluminum or the like and patterning so as to mask the active region 15b formed thereon, and a p-type impurity such as boron is implanted into an element isolation layer having a thin oxide film by ion implantation. Fig. 2 fc) K shows a more p++ diffusion layer 1
8 is obtained. After that, a mask material 19b such as aluminum
2C) is obtained, and when a glabella insulating film and a wiring pattern are formed on this, the structure of this embodiment shown in FIG. 1 is obtained.

According to this manufacturing method, p+1 diffusion 4 (p++ separation layer) is not formed before field oxidation, stacking faults occur during field oxidation, and p++ degrees decrease due to thermal diffusion during high temperature and long field oxidation. There is no need to worry, and when the present invention is used in a complementary MIS type semiconductor integrated circuit device, the same method can be used after forming the well.
Further, since it is sufficient to create a diffusion layer for element isolation when forming the source-drain diffusion layer of the Nch) transistor and the Pch) transistor, there is no need to add a new process for forming the diffusion layer.

Furthermore, in the above manufacturing method, the formation of the n0 diffusion layer was performed before the formation of the p10 diffusion layer, but there is no harm in doing the opposite. It is possible to use the invention.

FIG. 3(A) shows a plan view of another embodiment of the present invention.
The drawing direction shows a sectional view taken along line B-B/ in FIG.

In FIG. 3, the same functions as in FIG. 1 are indicated by the same reference numerals. Further, as in FIG. 1, connection electrode wiring is omitted. Furthermore, the relationship between the air volume insulating layer and the metal conductor thereon is also the same as that in FIG. 1, so it is omitted. In this embodiment, an island-shaped P-type well 31 is formed in an N-type semiconductor substrate, a plurality of N-channel type IGFETs are formed therein, and the isolation method of the present invention is used to provide insulation isolation between the plurality of N-channel type IGFETs. An area has been established. That is, the P-type well 31 can be considered as the P-type substrate 11 in FIG. On the other hand, in the N-type well 32, P-type source and drain regions 40 and 40 are provided.
, a plurality of P-channel type IGFETs having silicon gate electrodes 41 on gate insulating films 42 are formed. However, only one of them is illustrated. This P-channel type IGFET is insulated and isolated only by a thick silicon dioxide film 13 buried in the substrate. In this example,
p← type region 18 separating the N-channel type IGFET
When forming by the method shown in Fig. 2, at the same time, P
Source and drain regions 40 of channel type IGFET.
40 can be formed. At this time, a normal silicon gate process is performed using the gate electrode 41 and the surrounding field insulating film 13 as a mask. By this method, the P channel type source and drain regions 40, 40 and the p→ type region 18 of the present invention are simultaneously formed at the same concentration and the same depth. In this embodiment, the N-type well 32t/'
i can also be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to place an extremely highly concentrated parasitic MO8IJ-reduction prevention layer in the element isolation region, and an MIS type semiconductor integrated circuit in which parasitic MO8IJ-reduction does not occur even when exposed to radiation. It becomes possible to manufacture the device.

[Brief explanation of drawings]

1A and 1B are plan views and partial structural cross-sectional views of an embodiment of the present invention, and FIGS. 3(5) and fBl are plan views and sectional views showing other embodiments of the present invention, FIG. 4 is a sectional view of a semiconductor integrated circuit device with a conventional element isolation structure, and FIG. The figure shows the absorption dose dependence of the leakage current of parasitic MO8 in a conventional structure. 11...p-type semiconductor substrate, 12... crushed type impurity layer % 13 # 13 a * l 3 b
...Field oxide film, 14,42...
・Gate oxide film, 15a, 15b... Total diffusion layer, 16... Interlayer insulating film, 17... Wiring conductor, 18... P++ diffusion layer ( separation layer), 1
9a, 19b...Ion implantation mask material, 30.
...N-type semiconductor substrate, 31...P type well, 32...N type well, 40...p
10 diffusion layer, 21a. 21b, 41...Silicon gate electrode. Figure 1

Claims (7)

[Claims] (1) In a semiconductor integrated circuit device comprising a plurality of active regions having a second conductivity type formed on a semiconductor substrate having a first conductivity type and separated by an element isolation region, the element isolation The region includes a thick insulating film, a thin insulating film provided between the thick insulating films, and a region located under the thin insulating film,
A semiconductor integrated circuit device comprising an impurity region separated from the active region and having a higher concentration than the semiconductor substrate. (2) The semiconductor integrated circuit device according to claim (1), wherein the first conductivity type is P type, and the second conductivity type is N type. (3) A plurality of impurity regions of the first type are formed in an island-like impurity region of the second conductivity type on a semiconductor substrate having the first conductivity type, separated by an element isolation region. In a semiconductor integrated circuit device including an active region having a conductivity type, the element isolation region is a high concentration region of a second conductivity type having a higher impurity concentration than the impurity region formed separately from the active region. A semiconductor integrated circuit device comprising: a first insulating film on the high concentration region; a thick insulating film located between the first insulating film and the active region. (4) The semiconductor integrated circuit device according to claim (3), wherein the first conductivity type is N type, and the second conductivity type is P type. (5) A thick oxide film is selectively formed on a semiconductor substrate having the first conductivity type by a selective oxidation method, thereby forming a region constituting an active region where a device is formed and a part of an element isolation region. a step of forming a thin insulating film on the semiconductor substrate in a region constituting a part of the divided region; a step of covering the thin insulating film with a mask material for ion implantation; a step of ion-implanting impurities of two types of conductivity into a predetermined portion of the active region where the device is to be formed to form a diffusion region of the second type of conductivity; and removing the mask material to form the device. A step of covering the active region with a mask material, and using the mask material as a mask, ions of a first conductivity type impurity are implanted into the region having the thin insulating film for element isolation to form a high impurity of the first conductivity type. 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a concentration diffusion region. (6) An island-shaped second
A thick oxide film is selectively formed by a selective oxidation method on the surface of the island-like region of the semiconductor substrate in which an impurity region of a specific conductivity type is formed, forming part of an active region in which a device is formed and an element isolation region. a step of forming a thin oxide film on a portion of the semiconductor substrate constituting the part; and a step of covering the region having the thin oxide film with a mask material for ion implantation; using the mask material as a mask to implant impurities of the first conductivity type into a predetermined portion of the active region where the device is formed to form a diffusion region of the first conductivity type; and removing the mask material. A step of covering the region where the device is to be formed with a mask material, and using the mask material as a mask, ions of a second conductivity type impurity are implanted into the region having the thin oxide film for element isolation. 1. A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming a diffusion region of high conductivity type and high impurity concentration. (7) Forming a diffusion region with a high impurity concentration of type 2 conductivity in the element isolation region in the active region in the portion of type 1 conductivity where the island region of the semiconductor substrate is not formed. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the step of forming an impurity region of the second conductivity type in a predetermined portion is performed at the same time.