JPH04294582A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a parasitic channel caused by a deviation in mask matching at the time of writing data in a mask ROM. CONSTITUTION:An isolated island 22 is formed in the cell section of a mask ROM by forming a buried oxide film layer 21 in a substrate by performing high-energy high-concentration oxygen ion implantation by using an SIMOX technique after a field oxide film 11 is formed. Therefore, active areas 2 are completely insulated from each other.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a mask ROM in which data is written by ion implantation using a mask.

0002

2. Description of the Related Art In the field of manufacturing semiconductor devices, the number of elements per chip is increasing in response to the demand for higher integration. If we try to increase the integration density in response to these demands, the area of the memory cell array will inevitably be reduced, and the alignment precision of the masks used as appropriate in the process of manufacturing semiconductor devices will be limited to the high integration density. It comes to have an impact on the Such a situation is no exception in the case of a mask ROM among MOS memories in which data is written by ion implantation during manufacture.

This type of mask ROM is normally manufactured through the following steps. First, a large number of enhancement type n-channel MOS transistors are formed on a p-type silicon substrate, and then a photoresist is applied to the entire surface of the silicon substrate. Then, using lithography technology, a window is opened in the photoresist in the channel part of the transistor where data is to be programmed, and then an n-type impurity (
For example, phosphorus or arsenic) is ion-implanted at high energy to transform the transistor in that area into a depletion type. Thereafter, predetermined wiring, passivation, etc. are performed, and the process is completed.

Among these steps, a plan view and a cross-sectional view of the silicon substrate in the step of ion implantation are shown in FIGS. 2 and 3.
It is shown in FIG. 3 is a sectional view taken along line A-A in FIG. 2. In the figure, 1 is a field region, 2 is an active region, 3 is a gate electrode region, 4 is a source/drain region, 5 is a program region, 10 is a silicon substrate, 11 is a field oxide film, 12 is a gate oxide film, and 13 is a A polysilicon gate electrode and 14 indicate a resist mask for ion implantation. Note that the window 15 opened in the resist mask 14 is
It is set to a size that can tolerate the worst value of process variations up to this step and mask alignment error.

[0005]

However, when the window 15 of the resist mask 14 is set to such a size, when ion implantation is performed at high energy for programming in the state shown in FIG. There is a risk that impurity ions may be implanted not only into the channel portion 16 (program region 5) of the depletion-type transistor, into which ions should originally be selectively implanted, but also into its surrounding areas, especially under the field oxide film 11. be.

Therefore, the alignment of the mask exceeds the allowable range and deviates significantly in the width direction B of the channel (window 15a).
If ions are implanted under the field oxide film 11, the insulation distance between adjacent transistors will inevitably be insufficient. A parasitic channel P as shown is formed (occurrence of bit-to-bit leakage current), and as a result, there is a possibility that adjacent transistors, which should originally be enhancement type transistors, may become depleted. Such problems become more noticeable as the area of the memory cell array is reduced using conventional processes.

[0007] A simple method to solve such problems may be to improve the accuracy of process variations and mask alignment errors, but this is not very effective in achieving high integration while obtaining a satisfactory yield in the actual manufacturing process. It cannot be said that this is an efficient method.

The present invention has been made in view of these conventional problems, and makes it possible to perform ion implantation for programming while preventing the generation of parasitic channels due to mask misalignment, thereby improving semiconductor devices. An object of the present invention is to provide a method for manufacturing a semiconductor device that can further improve the degree of integration.

[0009]

[Means for Solving the Problems] To achieve the above object, the present invention includes a step of forming element isolation insulating films at predetermined intervals on a first conductivity type semiconductor substrate, and a step of forming a high concentration film inside the substrate. a step of implanting oxygen ions with high energy to separate the active region formed between the element isolation insulating films into islands; a step of forming a gate electrode on the substrate intersecting the active region; The present invention is characterized by comprising a step of forming a second conductivity type impurity diffusion layer in the region, and a step of ion-implanting the second conductivity type impurity under the gate electrode in the program region.

0010

[Operation] According to this manufacturing process, after forming the element isolation insulating film, a buried oxide film layer is formed inside the substrate by high-energy, high-concentration oxygen ion implantation, so that the active region is ) becomes an isolated island completely surrounded by an insulating film (dielectric separation). Therefore, even if there is an alignment error in the mask during ion implantation for programming, the adjacent active regions (isolated islands) are completely electrically isolated, so parasitics may occur between the adjacent active regions. Channels will no longer be formed. Therefore, the bit interval between transistors can be further shortened to the extent that it is no longer necessary to take into account mask alignment errors, so that the degree of integration of the semiconductor device can be further improved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a process-by-step cross-sectional view of a cell of a mask ROM manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present invention. Note that the same reference numerals as in FIG. 3 indicate the same things.

To explain the manufacturing process of this mask ROM, taking as an example the case where it is constructed with an n-channel MOS, first, a p-type silicon substrate 10, which is a first conductive type semiconductor substrate, is oxidized for element isolation using a so-called LOCOS oxidation method. A field oxide film (SiO2) 11 of 300 to 600 nm thick is used as an element isolation insulating film at predetermined intervals (
For example, it is formed at intervals of 0.5 to 1.5 μm). The region sandwiched between field oxide films 11 becomes active region 2 in which memory cell transistors are formed. Note that after field oxidation, the surface of the substrate 10 in the active region 2 is left exposed (see FIG. 1(a)).

[0013] Next, so-called SIMOX (Separ
ation by Implanted Oxygen
) technique to form a high concentration (for example, 101
A buried oxide film layer (SiO2) 21 with a thickness of 50 to 300 nm is formed under the surface of the substrate 10 (so-called SOI (Silicon On Insulator)
structure). As a result, the active region 2 is surrounded by the field oxide film 11 on both sides and the buried oxide film layer 21 on the bottom, and is completely surrounded by an insulating film (
dielectric separation). In this way, the isolation islands 22 formed by separating the active region 2 into island shapes are completely insulated from each other (see FIG. 1(b)).

Thereafter, a thin gate oxide film (SiO2) 12 for gate insulation is formed on the active region 2 (surface of the isolation island 22) on the substrate 10 using wet O2 according to a commonly used process.
2 After forming a polysilicon film with a thickness of 10 to 20 nm by an oxidation method, a polysilicon film with a thickness of 200 to 400 nm is formed on the entire surface of the substrate 10 by a CVD method, and a polysilicon film is formed in a gate electrode region 3 intersecting the active region 2 by lithography and etching. Selectively form the gate electrode 13 (as shown in FIG. 1(c)
) reference).

Next, although not shown, an n-type impurity such as phosphorus or arsenic is added as a second conductivity type impurity to the source/drain region 4 in the active region 2 and without the polysilicon gate electrode 13. The impurities are selectively introduced by thermal diffusion or ion implantation using 13 as a mask to form a source and a drain, which are second conductive impurity diffusion layers.

Next, after coating the entire surface with photoresist, a window 15 is formed in the resist in the program area 5, that is, the channel area 16 of the transistor to be brought into a depletion state for data writing.
A resist mask 14 for program ion implantation is formed by opening the resist mask 14, and using this as a mask, an n-type impurity (for example, phosphorus) 23 for forming a depletion type transistor is added.
Ions are selectively implanted under the electrode 13 to deplete the transistor in that area. At this time, each active region 2 (isolation island 22) is completely separated (
Even if ions are implanted under the field oxide film 11, each active region 2 will not be affected by it. Note that the size of the window 15 opened in the resist mask 14 is set to be somewhat larger than the size of the program area 5 to ensure that sufficient ions are implanted into the program area 5 (as shown in FIG. (d) see).

Thereafter, although not shown, wiring for predetermined bit lines, passivation, etc. are performed to complete the process.

As described above, according to this embodiment, the so-called SIM
Since the isolation island 22 is formed in the cell part of the mask ROM using OX technology to completely isolate the active regions 2 and 2, field oxidation may occur due to mask alignment errors (especially errors in the width direction B of the channel). Even if impurity ions for forming a depletion transistor are implanted under the film 11, a parasitic channel P will not be formed between adjacent active regions 2, and leakage current between bits will be prevented. will be done. Therefore, the bit interval of the transistor can be narrowed by an amount that does not require consideration of mask alignment errors, and as a result, the degree of integration of the memory can be further improved.

[0019]

As is clear from the above explanation, according to the manufacturing method of the present invention, even if there is a mask alignment error in the width direction of the program area, parasitic channels are always generated between adjacent active regions. Since this can be prevented, the degree of integration of the semiconductor device can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a process-by-step cross-sectional view of a cell of a mask ROM manufactured by a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a plan view of a cell in an ion implantation process for explaining the prior art.

FIG. 3 is a sectional view taken along line AA in FIG. 2;

[Explanation of symbols]

2...Active region 4...Source/drain region (second conductivity type impurity diffusion layer)
5...Program area 10...Silicon substrate (first conductivity type semiconductor substrate) 11...Field oxide film (element isolation insulating film) 13...Polysilicon gate electrode (gate electrode) 20...Oxygen ions 21...Buried oxide film layer

Claims (1)

[Claims] 1. A step of forming element isolation insulating films at predetermined intervals on a first conductive type semiconductor substrate, and forming between the element isolation insulating films by implanting high-concentration oxygen ions into the substrate with high energy. forming a gate electrode on the substrate to intersect with the active region; forming a second conductivity type impurity diffusion layer in the active region; ion-implanting a second conductivity type impurity under the gate electrode in the program area;
A method of manufacturing a semiconductor device, comprising: