JPS63117470A - Mos-type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lower a gate-oxidizing temperature of a single-layer gate electrode MOS-type transistor to be used inside a nonvolatile MOS memory device by a method wherein a gate silicon oxide film of the single-layer gate electrode MOS-type transistor and the gate silicon oxide film layer of a two-layer gate electrode MOS-type transistor are formed in their respective different processes. CONSTITUTION:After a field silicon oxide film 2, a first gate silicon oxide film 3 and a first gate polycrystalline silicon film 4 have been formed on one main face of a silicon substrate 1, the first gate polycrystalline silicon film 4 is heat-hardended at a high temperature of 1050-1100 deg.C; a second gate silicon oxide film 7 of about 500 Angstrom is then formed on the first gate polycrystalline silicon film 4; after that, a second gate polycrystalline/silicon film 8 is formed. Then, an impurity 6 of boron or phosphorus or the like is implanted into a channel region by making use of a resist layer 5 as a mask by means of an ion implantation technique.

Description

[Detailed Description of the Invention] The second invention relates to a conductor device and an improvement of its manufacturing method, and is an example of a non-volatile MOS (metal oxide semiconductor) semiconductor device.
There were those shown in Figure A (a) to (d). Each figure is a sectional view of each main part explaining the manufacturing process in the prior art in the order of steps. First, as shown in FIG. 2(a), a field silicon oxide film 2 of approximately 8,000 layers is formed in the element isolation region on one main surface of the silicon substrate 1, and then a field silicon oxide film 2 of approximately 300 layers is formed in the active region. A gate silicon oxide film 3 is generated. Next, a first gate polycrystalline silicon film 4 of approximately 4000 layers, which will become a floating gate, is formed, and the floating gate region (see FIG. 2) is formed.
a) The first gate polycrystalline silicon film 4 is etched using photolithography so that only the left half) remains. Next, in order to determine the threshold voltage of a normal film layer gate electrode MOS transistor used in a decoder of a MOS transistor, etc., an ion implantation technique is applied to the channel region of this single layer gate electrode MOS transistor using a resist 5 as a mask. Using,
Impurity 6 such as boron (B) or phosphorus (P) is implanted.

Next, as shown in FIG. 2(b), after removing the resist 5, using the first gate polycrystalline silicon film 4 as a mask, layer the gate electrode side type transistor region (right half of FIG. 2(b)). The first gate silicon oxide film 3 is etched to expose the silicon substrate 1. Next, the first gate polycrystalline silicon film 4 and the exposed silicon substrate 1 are thermally oxidized to form a second gate silicon oxide film 7. This second gate silicon oxide film 7 has approximately 500 layers on the first gate polycrystalline silicon film 4, and on the silicon substrate! The above will generate about 300 people. Further, this second gate silicon oxide film 7 exists between the first gate polycrystalline silicon film 4 and a second gate polycrystalline silicon film 8, which will be described later, and it is necessary to electrically insulate the two. 1050℃～11
The process must be performed at a relatively high temperature of about 00°C. Next, a second gate polycrystalline silicon film 8 is formed on the second gate silicon oxide film 7, and etched using photolithography to determine the source-drain spacing of the film layer gate electrode MOS type transistor. . At this time, the second gate polycrystalline silicon film 8 is left on the entire surface of the nonvolatile MOS memory region (the left half of FIG. 2(b)).

Next, as shown in FIG. 2C, using the resist 9 as a mask, the second gate polycrystalline silicon @ 8
, the second gate silicon oxide film 7, and the first gate polycrystalline silicon film 4 are sequentially etched in a self-aligned manner.

Next, as shown in FIG. 2(d), after removing the resist 9, the first gate silicon oxide film 3 and the second gate silicon oxide film 7 are removed using the second gate polycrystalline silicon film 8 as a mask.
is etched to expose the silicon substrate 1. Next, after forming an impurity diffusion layer 10 that will become a source/drain and an interlayer insulating film 11 with a thickness of approximately 1 μm, an opening is formed in the interlayer insulating film 11, and an aluminum wiring 12 and a pudgecon (passivation) film 13 are formed. Form.

[Problem that the invention seeks to solve]

A non-volatile MOS memory device with a conventional floating gate is
With the above structure, the impurity 6 injected into the channel part is used in the second step in the subsequent process to determine the threshold voltage of a normal film layer gate electrode MOS type transistor used in a decoder, etc. Since the formation temperature of the gate silicon oxide film 7 is as high as 1050°C to 1100°C, diffusion occurs during the formation of the second gate silicon oxide film 7, and the surface concentration of the channel part decreases significantly, resulting in a moss-type When the source-drain distance of a transistor is narrowed to 2 μ or less, there are drawbacks such as increased short channel effect.

This invention was made in order to solve one or more of the problems of the conventional method, and by adopting a process that can reduce the diffusion of impurities in the channel part of a MOS type semiconductor device, a floating gate with good characteristics can be obtained. An object of the present invention is to provide a nonvolatile MOS memory device having the following characteristics.

(Means for solving the problem) Therefore, in the present invention, after the silicon oxide film existing between the first gate electrode and the 7JJ2 gate electrode of the MOS type semiconductor device is formed, the threshold voltage is applied to the channel part. This object is attempted to be achieved by employing a process of implanting impurities that determine the characteristics of the semiconductor device and forming gate electrodes of a gate silicon oxide film and a gate polycrystalline silicon film.

[Effect]

With the above configuration, it is possible to reduce the diffusion of the impurities during the manufacturing process and improve the characteristics.

〔Example〕

The present invention will be explained below based on examples. FIGS. 1(a) to (d) show sectional views of each main part explaining the manufacturing process order of an embodiment of the present invention, and are the same as those in FIGS. 2(a) to (d) of the sprouting prior art. Equivalent) Components are represented by the same symbols.

In FIG. 1(a), on one main surface of the silicon substrate 1,
After forming the field silicon oxide film 2, the first gate silicon oxide film 3, and the first gate polycrystalline silicon film 4, as shown in the figure, ! By thermally oxidizing the first gate polycrystalline silicon film 4 at a high temperature of 050°C to 1100°C, the second gate silicon oxide ri! Approximately 500 layers of A7 are formed on the first gate polycrystalline silicon film 4, and then a second gate polycrystalline silicon film 8 is formed. It is left on the entire surface of the sexual moss memory area (left half of FIG. 1(a)).

Next, as shown in FIG. 1(b), ion implantation technology was applied to the channel region using resist 5 as a mask, so as to determine the threshold voltage of a typical film layer gate electrode MOS type transistor used in decoders, etc. Boron (B) or phosphorus (
An impurity 6 such as P) is implanted.

Next, as shown in FIG. 1(C), after removing the resist 5, using the second gate polycrystalline silicon film 8 as a mask, one layer is applied to the gate electrode MOS type transistor region (right half of FIG. 2(C)). The stacked silicon oxide film 14 of the first gate silicon oxide film 3 and the second gate silicon oxide film 7 is etched to form a silicon substrate! to expose. Next, more gates?
This becomes the gate silicon oxide film of a polar MOS type transistor. The third gate silicon oxide film 15 was heated to about 300°C at 900°C.
After the formation, a third polycrystalline silicon film 16 that will become a gate electrode is formed. Next, this third polycrystalline silicon WA1
6 is etched using a photolithography technique so as to determine the source-drain distance of the film layer gate electrode MOS type transistor. Next, the third gate polycrystalline silicon film 16
Using this as a mask, the third gate silicon oxide @15 is etched. At this time, the third gate silicon oxide film 15 formed on the second gate polycrystalline silicon film 8 is also etched at the same time.

Next, as shown in FIG. 1(d), similarly to the prior art example, the second gate polycrystalline silicon 1lQ8 , second gate silicon oxide film 7, first gate polycrystalline silicon film 4. Then, the first gate silicon oxide film 3 is etched. Thereafter, after forming an impurity diffusion layer 10 and an interlayer insulating film 11, an opening is provided in the interlayer insulating film 11, and an aluminum wiring 12 and a padding film 13 are formed.

Figure 713 shows the change in threshold voltage with respect to the source-drain distance of the film layer gate electrode MOS transistor formed as described above. The dotted line is for the conventional example, and the solid line is for the conventional example.
A case of an embodiment of this invention will be shown. The horizontal axis is the source-drain distance, and the vertical axis is the threshold voltage.

Further, in the above embodiment, as shown in FIG. 2(C), after removing the third gate silicon oxide film 15, in a self-aligned manner, the spacing between the source and drain of the nonvolatile MOS transistor is determined. Sequentially, a second gate polycrystalline silicon film 8, a second gate silicon oxide film, a first gate polycrystalline silicon film 4, and a first gate silicon oxide film l1i3.
Although the order of etching has been shown, the self-aligned etching of the nonvolatile MOS transistor may be performed while leaving the third gate silicon oxide film 15 intact. In this case, the third gate silicon oxide 115 on the second gate polycrystalline silicon film 8 is first etched in the self-aligned etching. Further, when etching the last first gate silicon oxide M3, the third gate silicon oxide film 15 on the silicon substrate 1 is etched at the same time.

Furthermore, in the above embodiment, after forming a single-layer gate electrode MOS transistor, self-aligned etching of the nonvolatile MOS transistor was performed. A MOS type transistor may also be formed.

(Effects of the Invention) As described above, according to the present invention, the gate oxidation temperature of a film layer gate electrode MOS transistor used in a nonvolatile MOS memory device can be lowered.
Diffusion of implanted impurities in the channel portion is prevented, and a MOS type semiconductor device with good characteristics can now be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of main parts in the order of manufacturing steps of an embodiment of a non-volatile MOS memory device having a floating gate according to the present invention, and FIG. 2 is a sectional view of main parts in the order of manufacturing steps of a conventional example.
FIG. 3 is a diagram showing the relationship between the source spacing and the threshold voltage of the single-gate electrode MOS type transistor of the conventional example and the above-mentioned conventional example, respectively. 1...Silicon substrate

Claims (3)

[Claims] (1) In a semiconductor device including at least a MOS transistor having a double-layer gate electrode and a MOS transistor having a single-layer gate electrode on the same silicon substrate,
A MOS semiconductor device, characterized in that the gate silicon oxide film of the single-layer gate electrode MOS transistor is formed by a different process from that of any gate silicon oxide film layer of the double-layer gate electrode MOS transistor. (2) The gate electrode of the single-layer gate electrode MOS transistor is formed by a different process from any gate electrode of the double-layer gate electrode MOS transistor. Semiconductor equipment. (3) At least a step of forming a first gate silicon oxide film on one principal surface of the silicon substrate by thermally oxidizing the silicon substrate, and a step of forming a first gate electrode of the first polycrystalline silicon film. , thermally oxidizing the first gate electrode to form a second gate silicon oxide film;
A second polycrystalline silicon film is formed on the gate silicon oxide film.
A third gate silicon oxide film is formed by forming a gate electrode, etching the silicon oxide film using the second gate electrode as a mask to expose the silicon substrate, and thermally oxidizing the exposed silicon substrate. A method for manufacturing a MOS type semiconductor device, comprising the steps of: generating a film; and forming a third gate electrode of a third gate polycrystalline silicon film on the third gate silicon oxide film.