JPH03283468A - Manufacture of nonvolatile memory device - Google Patents
Manufacture of nonvolatile memory deviceInfo
- Publication number
- JPH03283468A JPH03283468A JP2081120A JP8112090A JPH03283468A JP H03283468 A JPH03283468 A JP H03283468A JP 2081120 A JP2081120 A JP 2081120A JP 8112090 A JP8112090 A JP 8112090A JP H03283468 A JPH03283468 A JP H03283468A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate
- polycrystalline silicon
- floating gate
- control gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 23
- 230000003647 oxidation Effects 0.000 claims description 16
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 33
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000001020 plasma etching Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 41
- 229910052581 Si3N4 Inorganic materials 0.000 description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 210000004027 cell Anatomy 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、浮遊ゲートと制御ゲートを有する書替え可能
なメモリセルを用いた不揮発性半導体記憶装置の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate.
（従来の技術）
第４図（ａ） 、 （ｂ）は、それぞれ従来のＥＥＴＭ
Ｏ８型のメモリセル構造を示す平面図とそのＡ−Ａ″断
面図を示している。この構造は、素子分離されたｐ型す
コン基板３１のチャンネル領域全面にトンネル電流が流
れ得る薄い第１ゲート絶縁膜３４が形成され、この上に
浮遊ゲート３５が形成され、この上に更に第２ゲート絶
縁膜３６を介して制御ゲート３７が形成されている。３
２．３３はそれぞれソース、ドレインである。(Prior art) Figures 4(a) and 4(b) show the conventional EETM, respectively.
A plan view showing an O8 type memory cell structure and a cross-sectional view thereof taken along line A-A'' are shown. A gate insulating film 34 is formed, a floating gate 35 is formed on this, and a control gate 37 is further formed on this with a second gate insulating film 36 interposed therebetween. 3
2.33 are the source and drain, respectively.
第５図（ａ） 、 （ｂ）を用いて第４図に示したメモ
リセルの製造工程を説明する。まず、ｐ型シリコン基板
３１に通常の工程に従って素子分離絶縁膜（図示せず）
を形成した後熱酸化法によって５０〜２００人のシリコ
ン酸化膜からなるトンネル絶縁膜３４を全面に形成し、
次いで全面に浮遊ゲートを形成するための第１層多結晶
シリコン膜３５を堆積形成する。第１層多結晶シリコン
膜３５は例えばＬＰＣＶＤ法によって５００〜４０００
人の厚さに形成する。またこの第１層多結晶シリコン膜
３５には導電性を付与する為、リンまたは砒素などの不
純物をドーピングする。The manufacturing process of the memory cell shown in FIG. 4 will be explained using FIGS. 5(a) and 5(b). First, an element isolation insulating film (not shown) is formed on a p-type silicon substrate 31 according to a normal process.
After forming, a tunnel insulating film 34 made of 50 to 200 silicon oxide films is formed on the entire surface by a thermal oxidation method.
Next, a first layer polycrystalline silicon film 35 for forming a floating gate is deposited over the entire surface. The first layer polycrystalline silicon film 35 is formed with a thickness of 500 to 4000 by, for example, the LPCVD method.
Form to the thickness of a person. Further, this first layer polycrystalline silicon film 35 is doped with an impurity such as phosphorus or arsenic in order to impart conductivity.
全面に第２ゲート絶縁膜（層間絶縁膜）３６を形成する
。この第２ゲート絶縁膜３６は例えば、シリコン酸化膜
−シリコン窒化膜−シリコン酸化膜の三重層とする。す
なわち、第１層多結晶シリコン膜３５の熱酸化により８
０〜２００人の第１のシリコン酸化膜を形成し、この上
にＣＶＤ法によって８０〜２００人のシリコン窒化膜を
堆積する。そしてこの後窒化膜表面にさらに熱酸化によ
って８０〜２００人の第２のシリコン酸化膜を形成する
。その後全面に制御ゲートを形成するための第２層多結
晶シリコン８３７を５００〜４０００人堆積し、これに
第１層多結晶シリコン膜と同様に不純物をドーピングす
る（第５図（ａ））。A second gate insulating film (interlayer insulating film) 36 is formed over the entire surface. The second gate insulating film 36 is, for example, a triple layer of a silicon oxide film, a silicon nitride film, and a silicon oxide film. That is, by thermal oxidation of the first layer polycrystalline silicon film 35, 8
A first silicon oxide film of 0 to 200 layers is formed, and a silicon nitride film of 80 to 200 layers is deposited thereon by CVD. Thereafter, a second silicon oxide film of 80 to 200 layers is further formed on the surface of the nitride film by thermal oxidation. Thereafter, 500 to 4,000 layers of second layer polycrystalline silicon 837 for forming a control gate are deposited over the entire surface, and impurities are doped thereto in the same manner as the first layer polycrystalline silicon film (FIG. 5(a)).
この後、通常ＰＥＰ工程を経て反応性イオンエツチング
によって第２層多結晶シリコン膜３７、第２ゲート絶縁
膜３６および第１層多結晶シリコン膜３５を順次エツチ
ングして、制御ゲート３７および浮遊ゲート３５を分離
形成する（第５図（ｂ））。次にイオン注入によってソ
ースおよびドレインを自己整合的に形成する。Thereafter, the second polycrystalline silicon film 37, the second gate insulating film 36, and the first polycrystalline silicon film 35 are sequentially etched by reactive ion etching through a normal PEP process, and the control gate 37 and floating gate 35 are etched in sequence. are separated and formed (FIG. 5(b)). Next, the source and drain are formed in a self-aligned manner by ion implantation.
次に（第５図（Ｃ））のように熱酸化法によって後酸化
工程として浮遊ゲート３５、および制御ゲートトの露出
表面を酸化し、酸化膜３８を形成する。Next, as shown in FIG. 5C, the exposed surfaces of the floating gate 35 and the control gate are oxidized as a post-oxidation step by thermal oxidation to form an oxide film 38.
この後酸化工程の目的は、浮遊ゲート３５下端を丸く酸
化させることによって電界の集中を防ぎサーフェスブレ
イクダウン等に基く耐圧を向上させることと、熱酸化法
によって得られる良質な酸化膜によって、後工程で形成
されるＣＶＤ酸化膜やリンドープしたシリケートガラス
（Ｐ Ｓ Ｇ）層等からの不純物の侵入を遮へいするこ
とにある。The purpose of this post-oxidation process is to oxidize the lower end of the floating gate 35 into a round shape to prevent concentration of electric fields and improve breakdown voltage based on surface breakdown, etc., and to improve the breakdown voltage due to surface breakdown etc. by oxidizing the lower end of the floating gate 35. The purpose of this method is to prevent impurities from entering from the CVD oxide film, phosphorus-doped silicate glass (PSG) layer, etc.
しかしながらこのような酸化は第２の絶縁膜３６を介し
て対向する、制御ゲートと浮遊ゲートの端部も同時に酸
化され、端部分での酸化膜厚を厚くしてしまう。However, such oxidation simultaneously oxidizes the ends of the control gate and the floating gate, which are opposite to each other with the second insulating film 36 in between, thereby increasing the thickness of the oxide film at the ends.
（発明が解決しようとする課題）
上述のように、従来の不揮発性半導体記憶装置の製造方
法では耐圧を良くするため、浮遊ゲート下端を酸化する
ことによって電界集中が生じない形状にしている。(Problems to be Solved by the Invention) As described above, in the conventional manufacturing method of a nonvolatile semiconductor memory device, in order to improve breakdown voltage, the lower end of the floating gate is oxidized to create a shape that does not cause electric field concentration.
しかしなから、この酸化工程によって、同時に、第２の
絶縁膜を介して対向する制御ゲートと浮遊ゲート端も酸
化されてしまう。このことによって、両ゲート端部間で
の第２の絶縁膜厚が増加し、制御ゲートと浮遊ゲート間
容量が減少してＦＥＴＭＯ８の注入、放出特性を劣化さ
せる。またメモリセルの微細化と共にその影響は大きく
なる。However, due to this oxidation step, the ends of the control gate and the floating gate, which are opposed to each other with the second insulating film interposed therebetween, are also oxidized at the same time. This increases the thickness of the second insulating film between both gate ends, reduces the capacitance between the control gate and the floating gate, and deteriorates the injection and emission characteristics of the FETMO8. Further, as memory cells become smaller, the influence becomes greater.
本発明は上記の点に鑑みなされたもので、上述のような
制御ゲートと浮遊ゲート間容量の減少を軽減する。不揮
発性半導体記憶装置の製造方法を提供することを目的と
する。The present invention has been made in view of the above points, and alleviates the decrease in capacitance between the control gate and the floating gate as described above. An object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device.
［発明の構成］
（課題を解決するための手段）
本発明に係る不揮発性半導体記憶装置の製造方法は、半
導体基板上に選択エツチングによって制御ゲートおよび
浮遊ゲートを形成した後、このゲートに対して自己整合
的に前記半導体基板表面を選択エツチングする工程を有
することを特徴とする。[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes forming a control gate and a floating gate on a semiconductor substrate by selective etching, and then forming a control gate and a floating gate on the semiconductor substrate by selective etching. The method is characterized by comprising a step of selectively etching the surface of the semiconductor substrate in a self-aligned manner.
（作用）
本発明の不揮発性半導体記憶装置の製造方法によれば半
導体基板をエツチングした後、後酸化を行うが、従来の
ように半導体基板をエツチングしない場合に比較して浮
遊ゲート下端近傍の半導体基板表面の直接酸素雰囲気に
さらされる領域が増え、その領域は容易に酸化され、浮
遊ゲート下端の実効的なトンネル酸化膜が増加し、耐圧
が向上する。(Function) According to the method of manufacturing a non-volatile semiconductor memory device of the present invention, post-oxidation is performed after etching the semiconductor substrate, but compared to the conventional case where the semiconductor substrate is not etched, the semiconductor substrate near the lower end of the floating gate is etched. The area of the substrate surface that is directly exposed to the oxygen atmosphere increases, and this area is easily oxidized, increasing the effective tunnel oxide film at the bottom of the floating gate and improving the breakdown voltage.
従って、従来より短い、後酸化時間でも、従来と同等の
耐圧のトンネル酸化膜が形成できる。Therefore, a tunnel oxide film having the same breakdown voltage as the conventional one can be formed even with a shorter post-oxidation time than the conventional one.
この後酸化時間の短縮によって、浮遊ゲートと制御ゲー
ト間の容量の低下を招く浮遊ゲートと制御ゲート端部で
の酸化が軽減され、注入、放出特性の劣化を防ぐことが
できる。By shortening the post-oxidation time, oxidation at the ends of the floating gate and control gate, which causes a decrease in capacitance between the floating gate and the control gate, can be reduced, and deterioration of injection and emission characteristics can be prevented.
（実施例）
以下本発明の第１の実施例第１図（ａ） 、 （ｂ）を
用いて説明する。(Example) A first example of the present invention will be described below with reference to FIGS. 1(a) and 1(b).
まずｐ型ｓｉ基板１に通常工程に従って素子分離絶縁膜
を形成した後、熱酸化法によって５０〜２００人のシリ
コン酸化膜からなるトンネル絶縁膜４を選択的に形成し
、次いで全面に浮遊ゲートを形成するための第１層多結
晶シリコン膜５を堆積形成する。第１層多結晶シリコン
膜５は例えばＬＰＣＶＤ法によって５００〜４０００人
の厚さに形成する。またこの第１層多結晶シリコン膜５
には導電性を付与する為、リンまたは砒素などの不純物
をドーピングする。First, an element isolation insulating film is formed on a p-type Si substrate 1 according to a normal process, and then a tunnel insulating film 4 made of 50 to 200 silicon oxide films is selectively formed by a thermal oxidation method, and then a floating gate is formed on the entire surface. A first layer polycrystalline silicon film 5 to be formed is deposited. The first layer polycrystalline silicon film 5 is formed to a thickness of 500 to 4000 layers by, for example, the LPCVD method. Also, this first layer polycrystalline silicon film 5
is doped with impurities such as phosphorus or arsenic to impart conductivity.
次にこの状態で反応性イオンエツチング法によって第１
層多結晶シリコン膜５をエツチングして、素子分離領域
上に浮遊ゲート分離用の溝を形成する（図示せず）。Next, in this state, the first layer is etched using a reactive ion etching method.
The layered polycrystalline silicon film 5 is etched to form floating gate isolation trenches on the element isolation regions (not shown).
次に全面に第２ゲート絶縁膜（層間絶縁膜）６を形成す
る。この第２ゲート絶縁膜６は例えば、シリコン酸化膜
−シリコン窒化膜−シリコン酸化膜の三重層とする。す
なわち、第１層多結晶シリコン膜５の熱酸化により８０
〜２００人の第１のシリコン酸化膜を形成し、この上に
ＣＶＤ法によって８０〜２００人のシリコン窒化膜を堆
積する。Next, a second gate insulating film (interlayer insulating film) 6 is formed over the entire surface. The second gate insulating film 6 is, for example, a triple layer of a silicon oxide film, a silicon nitride film, and a silicon oxide film. That is, by thermal oxidation of the first layer polycrystalline silicon film 5,
A first silicon oxide film of ~200 layers is formed, and a silicon nitride film of 80 to 200 layers is deposited thereon by CVD.
そして、この後窒化膜表面にさらに熱酸化によって８０
〜２００人の第２のシリコン酸化膜を形成する。その後
全面に制御ゲートを形成するための第２層多結晶シリコ
ン膜７を５００〜４０００人堆積し、これに第１層多結
晶シリコン膜同様に不純物をドーピングする（第１図（
ａ））。Then, the surface of the nitride film is further thermally oxidized to an 80%
Form a second silicon oxide film of ~200 layers. Thereafter, a second layer polycrystalline silicon film 7 for forming a control gate is deposited by 500 to 4000 people over the entire surface, and this is doped with impurities in the same manner as the first layer polycrystalline silicon film (see Fig. 1).
a)).
この後、通常のＰＥＰ工程を経てレジスト等のマスクパ
ターン７ａを用いた反応性イオンエツチングによって第
２層多結晶シリコン膜７、第２ゲート絶縁膜６および第
１層多結晶シリコン膜５を順次エツチングして、制御ゲ
ート７および浮遊ゲート５を分離形成する。After this, the second layer polycrystalline silicon film 7, the second gate insulating film 6, and the first layer polycrystalline silicon film 5 are sequentially etched by reactive ion etching using a mask pattern 7a such as a resist through a normal PEP process. Then, control gate 7 and floating gate 5 are formed separately.
次にイオン注入によってソース８、ドレイン９を自己整
合的に形成する（第１図（ｂ７））。Next, the source 8 and drain 9 are formed in a self-aligned manner by ion implantation (FIG. 1(b7)).
次に制御ゲート７および浮遊ゲート５の分離形成後に用
いたマスクパターン７ａを引き続き使用して、半導体基
板をエツチングする（第１図（Ｃ））。Next, the semiconductor substrate is etched by continuing to use the mask pattern 7a used after separating the control gate 7 and the floating gate 5 (FIG. 1(C)).
次に熱酸化法によってメモリセル表面を酸化し、酸化膜
を形成する（図１ （ｄ））。Next, the memory cell surface is oxidized by thermal oxidation to form an oxide film (FIG. 1(d)).
又、半導体基板１は直接酸素雰囲気にさらされるので容
易に酸化が進み、浮遊ゲート５端での実効的な酸化膜厚
みが増大する。この実施例によれば従来の同等の耐圧を
維持しなから熱酸化の時間を短縮できるので、第２の絶
縁膜を介して対向する制御ゲートと浮遊ゲート端部の酸
化を軽減できる。Furthermore, since the semiconductor substrate 1 is directly exposed to an oxygen atmosphere, oxidation progresses easily, and the effective thickness of the oxide film at the end of the floating gate 5 increases. According to this embodiment, the time for thermal oxidation can be shortened while maintaining the same breakdown voltage as in the prior art, so oxidation of the end portions of the control gate and the floating gate, which face each other with the second insulating film interposed therebetween, can be reduced.
次に第２図（ａ）〜（ｂ）本発明による第２の実施例を
示す。ｐ型ｓｉ基板１に通常の工程にしたがって素子分
離絶縁膜を形成した後、熱酸化法によって５０〜２００
人のシリコン酸化膜からなるトンネル絶縁膜４を全面に
形成し、次いで全面に浮遊ゲートを形成するための第１
層多結晶シリコン膜５を堆積形成する。第１層多結晶シ
リコン膜５は例えばＬＰＣＶＤ法によって５００〜４０
００人の厚さに形成する。またこの第１層多結晶シリコ
ン膜５には導電性を付与する為、リンまたは砒素などの
不純物をドーピングする。Next, FIGS. 2(a) to 2(b) show a second embodiment according to the present invention. After forming an element isolation insulating film on a p-type Si substrate 1 according to a normal process, a 50 to 200
The first step is to form a tunnel insulating film 4 made of a silicon oxide film over the entire surface, and then to form a floating gate over the entire surface.
A layered polycrystalline silicon film 5 is deposited. The first layer polycrystalline silicon film 5 is formed by, for example, the LPCVD method to
Formed to a thickness of 0.00 people. Further, this first layer polycrystalline silicon film 5 is doped with an impurity such as phosphorus or arsenic in order to impart conductivity.
次にこの状態で反応性イオンエツチング法によって第１
層多結晶シリコン膜５をエツチングして、素子分離領域
上に浮遊ゲート分離用の溝を形成する（図示せず）。次
に全面第２ゲート絶縁膜（層間絶縁膜）６を形成する。Next, in this state, the first layer is etched using a reactive ion etching method.
The layered polycrystalline silicon film 5 is etched to form floating gate isolation trenches on the element isolation regions (not shown). Next, a second gate insulating film (interlayer insulating film) 6 is formed on the entire surface.
この第２ゲート絶縁膜６は例えば、シリコン酸化膜−シ
リコン窒化膜−シリコン酸化膜の三重層とする。すなわ
ち、第１層多結晶シリコン膜５の熱酸化により８０〜２
００人の第１のシリコン酸化膜を形成し、この上にＣＶ
Ｄ法によって８０〜２００人のシリコン窒化膜を堆積す
る。そしてこの後窒化膜表面にさらに熱酸化によって８
０〜２００人の第２のシリコン酸化膜を形成する。その
後全面に制御ゲートを形成するための第２多結晶シリコ
ン膜７を５００〜４０００人堆積し、これに第１層多結
晶シリコン膜と同様に不純物をドーピングする。The second gate insulating film 6 is, for example, a triple layer of a silicon oxide film, a silicon nitride film, and a silicon oxide film. That is, by thermal oxidation of the first layer polycrystalline silicon film 5,
Form a first silicon oxide film of
80 to 200 silicon nitride films are deposited by the D method. After this, the surface of the nitride film is further thermally oxidized to form an 8
A second silicon oxide film of 0 to 200 layers is formed. Thereafter, 500 to 4000 second polycrystalline silicon films 7 for forming control gates are deposited over the entire surface, and doped with impurities in the same manner as the first polycrystalline silicon film.
次に上記第２層多結晶シリコン膜上にＣＶＤ法によって
第２のシリコン窒化膜１３例えば１０００人程度０堆積
する（第２図（ａ））。Next, a second silicon nitride film 13, for example, about 1,000 layers, is deposited on the second layer polycrystalline silicon film by the CVD method (FIG. 2(a)).
この後、通常のＰＥＰ工程を経て反応性イオンエツチン
グによって第２のシリコン窒化膜１３、第２層多結晶シ
リコン膜７、第２ゲート絶縁膜６および第１層多結晶シ
リコン膜５を順次エツチングして、制御ゲート７および
浮遊ゲート５を分離形成する。ここでイオン注入によっ
てソース８．ドレイン９を自己整合的に形成する。Thereafter, the second silicon nitride film 13, second layer polycrystalline silicon film 7, second gate insulating film 6, and first layer polycrystalline silicon film 5 are sequentially etched by reactive ion etching through a normal PEP process. Then, control gate 7 and floating gate 5 are formed separately. Here, source 8. is formed by ion implantation. Drain 9 is formed in a self-aligned manner.
次に全面にＣＶＤ法によって第３のシリコン窒化膜１４
を堆積させる（第２図（ｂ））。次に異方性エツチング
によって前記第３のシリコン窒化膜１４をエツチングし
制御ゲートおよび浮遊ゲートの側壁に第３のシリコン窒
化膜１４層を残置する（第２図（Ｃ））。Next, a third silicon nitride film 14 is deposited on the entire surface by CVD method.
(Fig. 2(b)). Next, the third silicon nitride film 14 is etched by anisotropic etching to leave the third silicon nitride film 14 on the side walls of the control gate and floating gate (FIG. 2(C)).
この時制御ゲート７上部は第２のシリコン窒化膜１３で
おおわれており、制御ゲート７および浮遊ゲート５の側
壁は表面をシリコン窒か膜１４でおおわれる。At this time, the upper part of the control gate 7 is covered with a second silicon nitride film 13, and the surfaces of the side walls of the control gate 7 and floating gate 5 are covered with a silicon nitride film 14.
次に、上記シリコン窒化膜１３をマスクに半導体基板１
のソース、ドレインを例えば５０〜２０００人エツチン
グする（第２図（ｄ））。次に後酸化を行い、基板１表
面に酸化膜１８を形成する（第２図（ｅ））。Next, using the silicon nitride film 13 as a mask, the semiconductor substrate 1 is
For example, the source and drain are etched by 50 to 2000 people (FIG. 2(d)). Next, post-oxidation is performed to form an oxide film 18 on the surface of the substrate 1 (FIG. 2(e)).
ここで、第２ゲート絶縁膜６端部近傍はシリコン窒化膜
１４におおわれているため、ゲート端部酸化はおこらな
いが浮遊ゲート５端部近傍の半導体半導体基板は酸化さ
れ、浮遊ゲート５端部での実効的なトンネル酸化膜４厚
が増加するため耐圧は向上する。Here, since the vicinity of the end of the second gate insulating film 6 is covered with the silicon nitride film 14, the gate end is not oxidized, but the semiconductor substrate near the end of the floating gate 5 is oxidized, and the end of the floating gate 5 is oxidized. Since the effective thickness of the tunnel oxide film 4 increases, the breakdown voltage improves.
また、第３図に示すように、基板１として、ｎ型シリコ
ン基板１を用い、このメモリセルアレイ領域にｐ型ウェ
ル１□を形成し、このｐ型ウェル１□内に上記第１の実
施例と同様にしてメモリセルを形成することもできる。Further, as shown in FIG. 3, an n-type silicon substrate 1 is used as the substrate 1, a p-type well 1□ is formed in this memory cell array region, and the above-described first embodiment is formed in the p-type well 1□. A memory cell can also be formed in a similar manner.
ｐ型ウェル１２は例えば全メモリセルアレイ領域に共通
でもよいし、或いは適当なメモリアレイ・ブロック毎に
別々に形成してもよい。また、第２の実施例と同様にし
てもよい。For example, the p-type well 12 may be common to the entire memory cell array region, or may be formed separately for each appropriate memory array block. Further, it may be similar to the second embodiment.
また実施例では、一つのメモリセル部のみ説明したが、
セルアレイの方式は、ビット線には一つずつメモリセル
を接続し、ワード線方向には複数のメモリセルの制御ゲ
ートを共通にするＮＯＲ型としてもよいし、複数のメモ
リセルをソース、ドレインを隣接するもの同志で共用す
る形で直列接続してＮＡＮＤ型としてもよい。In addition, in the embodiment, only one memory cell section was explained, but
The cell array system may be a NOR type in which one memory cell is connected to the bit line and a common control gate for multiple memory cells in the word line direction, or a NOR type in which multiple memory cells are connected to the source and drain. They may be connected in series so that adjacent ones can be shared by each other to form a NAND type.
また第１層および第２層導電気体膜は、ｐｏｌｙｓ１１
モリブデンシリサイドタングステンシリサイド、その他
金属膜等からなる多層膜でもよい。Moreover, the first layer and the second layer conductive film are made of polys11
A multilayer film made of molybdenum silicide, tungsten silicide, other metal films, etc. may be used.
その池水発明は、その趣旨を逸脱しない範囲で種々変形
して実施することが可能である。The pond water invention can be implemented with various modifications without departing from the spirit thereof.
［発明の効果］
以上の様に本発明によれば、後酸化工程によってゲート
端部が酸化され、浮遊ゲートと制御ゲート間容量が減少
することによっておこる。注入、放出特性の劣化を軽減
することが可能となる。[Effects of the Invention] As described above, according to the present invention, the gate end portion is oxidized in the post-oxidation step, and the capacitance between the floating gate and the control gate is reduced. It becomes possible to reduce deterioration of injection and emission characteristics.
第１図は本発明による第１の実施例を説明するための工
程断面図、
第２図は本発明による第２の実施例を説明するための工
程断面図、
第３図は本発明による第３の実施例を説明するための工
程断面図、
第４図、第５図は従来のＦ Ｅ ＴＭＯＳの構造を説明
するための説明図である。
１・・・ｐ型シリコン基板、２・・・素子分離絶縁膜、
３・・・第１ゲート絶縁膜、４・・・トンネル絶縁膜、
５・・・第１層多結晶シリコン膜、６・・・第２ゲート
絶縁膜（層間絶縁膜）、７・・・第２層多結晶シリコン
膜、８，９・・・ｎ″″型拡散拡散層８・・・後酸化膜
、１３゜１４・・・シリコン窒化膜。FIG. 1 is a process sectional view for explaining a first embodiment according to the present invention, FIG. 2 is a process sectional view for explaining a second embodiment according to the present invention, and FIG. 3 is a process sectional view for explaining a second embodiment according to the present invention. 4 and 5 are explanatory diagrams for explaining the structure of a conventional FETMOS. 1...p-type silicon substrate, 2...element isolation insulating film,
3... First gate insulating film, 4... Tunnel insulating film,
5... First layer polycrystalline silicon film, 6... Second gate insulating film (interlayer insulating film), 7... Second layer polycrystalline silicon film, 8, 9... n'''' type diffusion Diffusion layer 8...post oxide film, 13°14...silicon nitride film.
Claims (2)
１の導体膜、第２の絶縁膜、第２の導体膜、をこの順で
積層して形成する工程と、前記第１、第２の絶縁膜及び
導体膜をエッチングし、積層パターンを形成する工程と
、次いでこれらの膜をマスクにして前記基板表面をエッ
チングする工程と、その後、酸化を行う工程とを含む不
揮発性メモリ装置の製造方法。(1) A step of laminating and forming a first insulating film, a first conductive film, a second insulating film, and a second conductive film in this order on a part of the element region of the semiconductor substrate; 1. A nonvolatile method that includes the steps of etching a second insulating film and a conductive film to form a laminated pattern, then etching the surface of the substrate using these films as a mask, and then performing oxidation. A method for manufacturing a memory device.
化膜を形成した後、方向性エッチングにより前記積層パ
ターンの側壁に窒化膜を残存せしめ、その後、酸化を行
う工程を含む請求項１記載の不揮発性メモリ装置の製造
方法。(2) After the step of forming the laminated pattern, the nitride film is formed on the entire surface, the nitride film is left on the side wall of the laminated pattern by directional etching, and then oxidation is performed. A method of manufacturing a non-volatile memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2081120A JPH03283468A (en) | 1990-03-30 | 1990-03-30 | Manufacture of nonvolatile memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2081120A JPH03283468A (en) | 1990-03-30 | 1990-03-30 | Manufacture of nonvolatile memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03283468A true JPH03283468A (en) | 1991-12-13 |
Family
ID=13737524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2081120A Pending JPH03283468A (en) | 1990-03-30 | 1990-03-30 | Manufacture of nonvolatile memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03283468A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629554A (en) * | 1992-03-31 | 1994-02-04 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| KR100414562B1 (en) * | 2001-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Method of manufacturing a nonvolatile memory cell |
| KR100423576B1 (en) * | 1997-06-30 | 2004-10-02 | 주식회사 하이닉스반도체 | Fabricating method of flash memory device for reducing undercut and noise |
| KR100444841B1 (en) * | 1997-12-29 | 2004-10-14 | 주식회사 하이닉스반도체 | Flash memory cell fabrication method for forming smoothly floating gate on source/drain region |
| JP2008193107A (en) * | 2008-02-18 | 2008-08-21 | Toshiba Corp | Manufacturing method of semiconductor device |
-
1990
- 1990-03-30 JP JP2081120A patent/JPH03283468A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629554A (en) * | 1992-03-31 | 1994-02-04 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| KR100423576B1 (en) * | 1997-06-30 | 2004-10-02 | 주식회사 하이닉스반도체 | Fabricating method of flash memory device for reducing undercut and noise |
| KR100444841B1 (en) * | 1997-12-29 | 2004-10-14 | 주식회사 하이닉스반도체 | Flash memory cell fabrication method for forming smoothly floating gate on source/drain region |
| KR100414562B1 (en) * | 2001-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Method of manufacturing a nonvolatile memory cell |
| JP2008193107A (en) * | 2008-02-18 | 2008-08-21 | Toshiba Corp | Manufacturing method of semiconductor device |
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