JPH0685273A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase a coupling capacitance between a floating gate electrode and a control gate electrode and, further improve a metal wiring coverage at a contact part. CONSTITUTION:A source region 4 and a drain region 6 are formed in a P-type silicon substrate 2. A floating gate electrode 10 is formed on a channel region with a gate oxide film 8 therebetween. The upper surface of the floating gate electrode 10 is inclined so as to be high on the source region side and low on the drain region side. A control gate electrode 14 is formed on the floating gate electrode 10 with a silicon oxide film 12 therebetween. As the facing surfaces of the floating gate electrode 10 and the control gate electrode 14 are inclined, a large coupling capacitance can be obtained. Further, as the electrodes 10 and 14 are inclined so as to be high on the source region side and low on the drain region side, the angle of the inclination near the edge part of a contact hole 17 exceeds 90 degrees, so that the coverage of a metal wiring 18 can be improved and the metal wiring can be protected from an open-circuit, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type non-volatile semiconductor memory device, and more particularly to a semiconductor substrate having a source region and a drain region facing each other, and a floating gate on a channel region between both regions via a gate oxide film. The present invention relates to a nonvolatile semiconductor memory device in which an electrode is formed and a control gate electrode is stacked on the floating gate electrode with an insulating film interposed therebetween, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a MOS type non-volatile semiconductor memory device having a floating gate electrode and a control gate electrode, the facing area between the control gate electrode and the floating gate electrode is reduced as the elements are integrated, and the area between the electrodes is reduced. Since the capacity value becomes smaller,
There arises a problem that the electric characteristics of the memory cell deteriorate. Therefore, various improvements have been made in order to increase the coupling capacitance between both electrodes to achieve high integration. For example, a groove is formed on the side surface of the floating gate electrode, and a control gate electrode is also formed on the side surface and the inner surface of the groove through an insulating film (JP-A-3-
No. 34577), a recess is formed in the upper surface of the floating gate electrode, and at least a part of the control gate is embedded therein (see Japanese Patent Application Laid-Open No. 3-34578), or a hole is formed inside the floating gate. It is formed, and a control gate electrode is opposed to the inner surface and the outer surface thereof with an insulating film interposed therebetween (see Japanese Patent Laid-Open No. 34581/1993).

[0003]

The control gate electrode is formed on the upper surface of the floating gate electrode via an insulating film, but the upper surface of the floating gate electrode is substantially parallel to the semiconductor substrate surface. Therefore, there is a limit to increase the coupling capacitance between the floating gate electrode and the control gate electrode. Further, the source region is formed in a band shape parallel to the word line direction so that it is shared by a plurality of memory cells, and no contact is provided in the source region in each memory cell. On the other hand, in the drain region, the drain region is shared for each memory cell or a pair of memory cells adjacent to each other in the direction orthogonal to the word line, and the wiring is connected through the contact hole for each shared drain region. . The edge of the contact hole is almost 90 at the contact portion.
This may cause a problem in the coverage of the metal wiring.

A first object of the present invention is to increase the coupling capacitance between the floating gate electrode and the control gate electrode to achieve high integration. A second object of the present invention is to improve the coverage of metal wiring at the contact in the drain region.

[0005]

In the present invention, the upper surface of the floating gate electrode is formed so as to be inclined with respect to the semiconductor substrate surface. In a preferred aspect of the present invention, the control gate electrode is continuously formed as a common word line for a plurality of memory cells, and the source region is formed as a common continuous diffusion region for a plurality of memory cells parallel to the word line. In the memory cells arranged in the direction orthogonal to the word line direction, the memory cells sandwiching the source region share the same source region, and the memory cells sandwiching the drain region share the same drain region. Therefore, the upper surface of the floating gate electrode is inclined so that it is higher on the source side and lower on the drain side, and wiring is connected to the drain region through a contact hole.

In order to tilt the upper surface of the floating gate electrode with respect to the semiconductor substrate surface, the manufacturing method of the present invention includes the following steps (A) to (E). (A) a step of depositing a first polycrystalline silicon film for a floating gate electrode on a silicon substrate through a gate oxide film, (B) a floating gate electrode forming region and a source forming region between the floating gate electrode forming regions Forming a resist pattern for covering the first polycrystalline silicon film by using the resist pattern as a mask to form an inclined surface on the surface of the first polycrystalline silicon film, (C) the resist A step of forming an insulating film after removing the pattern, and further depositing a second polycrystalline silicon film for a control gate electrode thereon, (E) the second polycrystalline silicon film by photolithography and etching;
A step of patterning the insulating film and the first polycrystalline silicon film to form a laminated gate electrode.

[0007]

Since the upper surface of the floating gate electrode is inclined, when the control gate electrode is formed on the floating gate electrode via the insulating film,
The facing area between the floating gate electrode and the control gate electrode is larger than the floating gate electrode surface parallel to the substrate, and the facing area between the two electrodes per unit area on the plane is larger, and the coupling capacitance is larger accordingly. . When the inclined surface of the floating gate electrode is inclined so that it is high in the source region and low in the drain region, if a contact is provided in the drain region, the angle of the edge of the contact hole becomes larger than 90 degrees, and the metal coverage is increased. Get better.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment. The P-type silicon substrate 2 has a source region 4 formed of a band-shaped N-type diffusion region extending in the direction perpendicular to the paper surface and an N-type diffusion region between the source regions 4 and 4 and separated in the memory cell in the direction perpendicular to the paper surface. The drain region 6 is formed. The source region 6 is common to a plurality of memory cells in the direction perpendicular to the paper surface, and
It is also shared by a pair of memory cells adjacent to each other in the direction orthogonal to the direction. The drain region 6 is separated for each memory cell in the direction perpendicular to the paper surface, and is shared by two memory cells adjacent to each other in the direction orthogonal to the direction perpendicular to the paper surface. On the substrate 2, a thickness of 100 to 700 is formed on the channel region between the source region 4 and the drain region 6.
A floating gate electrode 10 made of a polycrystalline silicon film whose resistance is lowered by phosphorus diffusion is formed through the gate oxide film 8 of Å.

The upper surface of the floating gate electrode 10 has a slope that is high on the source region side and low on the drain region side,
This inclination angle is, for example, 45 degrees with respect to the substrate surface. A silicon oxide film 12 having a thickness of 100 to 500 Å is formed on the floating gate electrode 10, and a control gate electrode made of a polycrystalline silicon film having a resistance of 1000 to 7,000 Å reduced by phosphorus diffusion. 14 is formed.
The floating gate electrode 10 is separated for each memory cell, but the control gate electrode 14 is formed in a continuous strip shape for the memory cells arranged in the direction perpendicular to the paper surface. An interlayer insulating film 16 is formed on the control gate electrode 14, and a metal wiring 18 is formed on each drain region 6 through a contact hole of the interlayer insulating film 16 to form the drain region 6.
Connected with. Reference numeral 20 is a cover insulating film.

Since the upper surface of the floating gate electrode 10 is inclined so that the source region side is high and the drain region side is low, the inclination angle is larger than 90 degrees at the edge portion of the contact hole 17, and therefore the coverage of the metal wiring 18 is provided. This prevents the metal wiring from breaking.

A method of manufacturing one embodiment will be described with reference to FIG. (A) The gate insulating film 8 is formed on the P-type silicon substrate 2. The gate insulating film 8 has a thickness of 10 by thermal oxidation, for example.
It is a silicon oxide film formed at 0 to 700Å. Polycrystalline silicon film 1 for floating gate electrode on gate insulating film 8
0 has a thickness of 1 by, for example, a CVD method (chemical vapor deposition method).
000-7000Å and then about 900
In the phosphoryl oxide (POCl ₃ ) atmosphere at ℃, phosphorus is diffused into the polycrystalline silicon film 10 to make it conductive.

(B) A resist pattern 22 is formed so as to cover the floating gate electrode formation region and the source formation region between the floating gate electrode formation regions. The resist pattern 22 is a pattern having a strip-shaped opening in the direction perpendicular to the paper surface and a strip-shaped opening in the lateral direction for separating the floating gate electrode into individual memory cells orthogonal to the direction. Using the resist pattern 22 as a mask, the polycrystalline silicon film 10 is subjected to taper etching to form an inclined surface on the surface of the polycrystalline silicon film 10. The taper etching of the polysilicon film 10 is performed at a tilt angle of, for example, 45 by performing low temperature dry etching using HBr as an etching gas, for example.
A taper etching having an angle such as a degree is performed.

(C) After removing the resist pattern 22, the insulating film 12 is formed on the polycrystalline silicon film 10 having an inclined surface.
Is formed as a silicon oxide film having a thickness of 100 to 500 Å by, for example, a thermal oxidation method. A polycrystalline silicon film 14 for a control gate electrode is deposited on the insulating film 12 to a thickness of 1000 to 7000Å by, for example, a CVD method. Then about 90
Phosphorus is diffused into the polycrystalline silicon film 14 in a phosphoryl oxide atmosphere at 0 ° C. to make it conductive.

(D) A resist film is formed on the polycrystalline silicon film 14, and a resist pattern 24 is formed by photolithography. The resist pattern 24 is formed in the pattern of the control gate electrode, and is formed in a strip shape extending in the direction perpendicular to the paper surface in the figure. Using the resist pattern 24 as a mask, the polycrystalline silicon film 14, the insulating film 12, and the polycrystalline silicon film 1
0 is sequentially etched to form a laminated gate electrode.

(E) After that, the resist 24 is removed.
N-type impurities such as phosphorus and arsenic are implanted into the surface portion of the substrate 2 using the obtained gate electrode having the laminated structure as a mask to form a source region and a drain region. After that, an interlayer insulating film is formed, a contact hole is formed, a metal wiring is formed, and a cover insulating film is formed.

[0016]

According to the present invention, since the facing surface between the floating gate electrode and the control gate electrode is inclined with respect to the substrate surface, the coupling capacitance between both electrodes is increased, which contributes to high integration. Further, by inclining the upper surface of the floating gate electrode so that the source side is higher and the drain side is lower, the coverage of the metal wiring in the contact portion formed in the drain region is improved and reliability is increased.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment.

FIG. 2 is a process cross-sectional view showing a process up to an intermediate process of manufacturing of one example.

[Explanation of symbols]

 2 silicon substrate 4 source region 8 gate oxide film 10 floating gate electrode 12 insulating film 14 control gate electrode 18 metal wiring

Claims (3)

[Claims] 1. A semiconductor substrate is provided with a source region and a drain region facing each other, a floating gate electrode is formed on a channel region between both regions via a gate oxide film, and an insulating film is formed on the floating gate electrode. A non-volatile semiconductor memory device in which a control gate electrode is laminated via a non-volatile semiconductor memory device, wherein an upper surface of the floating gate electrode is inclined with respect to the semiconductor substrate surface. 2. The control gate electrode is continuously formed as a common word line for a plurality of memory cells,
In the memory cells in which the source region is formed as a continuous diffusion region common to a plurality of memory cells in parallel to the word line and arranged in a direction orthogonal to the word line direction, the memory cells sandwiching the source region are formed. Share the same source region, the memory cells sandwiching the drain region share the same drain region, and the upper surface of the floating gate electrode is inclined so that it is higher on the source side and lower on the drain side. The non-volatile semiconductor memory device according to claim 1, wherein wiring is connected to the region through a contact hole. 3. A method of manufacturing a semiconductor memory device including the following steps (A) to (E). (A) a step of depositing a first polycrystalline silicon film for a floating gate electrode on a silicon substrate via a gate oxide film, (B) a floating gate electrode forming region and a source forming region between the floating gate electrode forming regions Form a resist pattern to cover
Using the resist pattern as a mask, taper etching the first polycrystalline silicon film to form an inclined surface on the surface of the first polycrystalline silicon film. (C) After removing the resist pattern, an insulating film is formed. A step of forming and further depositing a second polycrystalline silicon film for the control gate electrode thereon, (E) the second polycrystalline silicon film, the insulating film and the first polycrystalline silicon by photolithography and etching Patterning the film to form a stacked gate electrode.