JP3421136B2 - Method of manufacturing nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a floating gate electrode and a stack gate electrode having a control gate electrode via an insulating film ( semiconductor integrated circuit having a memory portion and a peripheral circuit built in one chip). Device is also included) .

[0002]

2. Description of the Related Art A stack gate electrode in an EPROM (erasable programmable ROM) or an EEPROM (electrically erasable programmable ROM) has a floating gate electrode made of a polysilicon film and an insulating film formed on the floating gate electrode. A control gate electrode made of the formed polysilicon film is provided. According to a method of manufacturing a semiconductor integrated circuit device including a memory element having a stack gate electrode together with a transistor of a peripheral circuit, a polysilicon film of a control gate electrode and a polysilicon film of a gate electrode of a peripheral transistor are formed in separate steps. By process and forming them in the same step 2
Two are being done by layer polysilicon process.

A method by a three-layer polysilicon process is shown in FIG. (A) In the memory area, a stack gate electrode having a two-layer polysilicon structure is formed. The stack gate electrode is, for example, P
A floating gate electrode 6 separated for each memory element is formed on a gate insulating film 4 on a silicon substrate 2, and an insulating film (for example, a three-layer structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed thereon). ONO
A continuous strip-shaped control gate electrode 10 is formed in a plurality of memory elements via a film 8. After that, N-type impurities are injected into the substrate 2 and diffused to form a source
The drain region 12 is formed. At this time, by performing the impurity diffusion process by wet oxidation at 900 to 950 ° C., the edges of the floating gate electrode 6 and the control gate electrode 10 of the stack gate electrode are rounded, and the oxide film 14 covering the stack gate electrode is simultaneously formed. It is formed. Oxide film 1 on the substrate surface in the peripheral transistor area
3 is formed.

(B) Next, boron is implanted into the peripheral transistor region for controlling the threshold voltage. Then, after removing the oxide film 13 in the peripheral transistor region, a gate oxide film 16 is formed. Next, a third-layer polysilicon film which will be the gate electrode of the peripheral transistor is deposited and patterned by photolithography and etching to form the gate electrode 18. At this time, in the memory region, the sidewall 20 of polysilicon remains on the side surface of the stack gate electrode.

(C) In order to remove the polysilicon side wall 20, a resist pattern 22 having an opening in the memory region is formed by photolithography, and isotropic polysilicon etching is performed. (D) After removing the resist pattern 22, N-type impurity ion implantation is performed on the substrate to form low-concentration source / drain regions 24 in the peripheral transistor region. After that, a high temperature oxide film is deposited and etched back to form a sidewall spacer 26 on the side surface of the gate electrode 18. High concentration source / drain region 28
In order to form, the N-type impurities are ion-implanted at a high concentration into the substrate using the sidewall spacers 26 as a mask.
Performs diffusion processing of implanted ions to set the peripheral transistor to L
Make a DD structure. When forming the sidewall spacer 26, the sidewall 27 of a high temperature oxide film is also formed on the side surface of the stack gate electrode.

In a two layer polysilicon process, FIG.
As shown in (A), a polysilicon film for a floating gate electrode is deposited on the substrate 2 via the gate oxide film 4, and an ONO film or the like of an interlayer insulating film is formed thereon. Then, patterning is performed by photolithography and etching to form the floating gate electrode 6 and the insulating film 8. Next, the second-layer polysilicon film 30 serving both as a control gate electrode and a peripheral transistor gate electrode
Is deposited, and the polysilicon film 30 is patterned by photolithography and etching as shown in (B) to form the control gate electrode 10 in the memory region and the gate electrode in the peripheral transistor region.

[0007]

The following problems are raised in the three-layer polysilicon process of FIG.
First, a step of removing the polysilicon sidewall 20 in the memory region is required. Further, if the polysilicon side wall 20 remains even slightly, it causes a charge loss of the memory, which causes a defective charge retention characteristic. As the area of the memory cells is reduced and the space between the memory cells is also reduced, it becomes more difficult to completely remove the polysilicon sidewall 20. In particular, it is not easy to remove the polysilicon side wall that goes around the overhang portion of the stack gate electrode.

The second problem is the LD of the peripheral transistor.
The high temperature oxide film for forming the side wall spacers 26 for forming the D structure is optimized according to the electrical characteristics of the peripheral transistor, so that the film thickness is 1500.
It is about 2500 Å. On the other hand, since the stack gate electrode has a step difference of 6000 to 7,000 Å, the film thickness of the high temperature oxide film is too thin to form the sidewall 27 having a sufficient height in the memory region. The side wall 27 in the memory region is necessary to improve the charge retention characteristics of the memory, but after the high temperature oxide film is etched back, the side wall 27 remains only below the side surface of the stack gate electrode. The entire lateral sides of the electrode cannot be covered. Further, during overetching by high temperature oxide film etching, the oxide film 14 itself covering the stack gate electrode is also etched at the upper ends of the sidewalls 27 due to the influence of lateral etching. As a result, the side wall 27 is formed of an interlayer insulating film such as a BPSG film between the polysilicon film and the metal wiring, an interlayer insulating film between the metal wirings, and mobile ions such as alkali ions and hydrogen ions that penetrate through the passivation film. Cannot effectively block against.

A first object of the present invention is to provide an effective insulating film sidewall on the side surface of the stack gate electrode and prevent the polysilicon from remaining on the side surface of the stack gate electrode in the manufacturing method by the three-layer polysilicon process. That is , the step of removing the polysilicon sidewall is unnecessary .

In the case of the manufacturing method by the two-layer polysilicon process, after forming the floating gate electrode and the interlayer insulating film on the floating gate electrode, the upper polysilicon film 3 serving as both the control gate electrode and the peripheral transistor gate electrode is formed.
When 0 is deposited and patterned by etching, polysilicon sidewalls 32 (also called stringers) remain on the side surfaces of the floating gate electrode 6. When patterning is performed by anisotropic etching in order to finish the etching profile of the polysilicon film perpendicular to the substrate with the miniaturization of the element, such stringers 32 are likely to occur. This stringer 32 causes a problem such as a short circuit between the floating gate electrode 6 and one adjacent thereto.

As a process before depositing the upper polysilicon film 30, the oxide film on the substrate is usually removed and a gate oxide film is formed for peripheral transistors. The oxide film removing process is performed by wet etching. Done.
At this time, as shown in FIG. 3A, the gate oxide film 4 in the memory region is also etched to form a gap 34. A polysilicon film deposited by the CVD method may enter the gap 34, and a residue 36 may remain in the gap 34 as shown in FIG. In order to remove the stringer 32, the memory area is exposed by photolithography and isotropic polysilicon etching is performed. However, as shown in FIG. 3B, the polysilicon left under the eaves of the floating gate electrode 6 remains in the gap 34. It is extremely difficult to completely remove even the silicon stringer 36.

[0012] Therefore, a second object of the present invention, when manufacturing the EPROM or EEPROM in 2-layer polysilicon process is to avoid leaving polysilicon side and the lower portion of the floating gate electrode 6 .

[0013]

Produced according to the present invention, in order to solve the problems]
A semiconductor memory device has a floating gate electrode separated for each memory element via a gate oxide film on a semiconductor substrate, and an insulating film on the floating gate electrode, and patterned in a strip shape so as to be continuous for a plurality of memory elements. In a non-volatile semiconductor memory device having a stack gate electrode including a control gate electrode, a side wall-shaped insulating film that is thicker at a lower portion and thinner at an upper portion is formed on a lateral side surface of the control gate electrode in the stack gate electrode. It is what The sidewall insulating film is a silicon oxide film or a silicon nitride film. The sidewall insulating film is
In a preferred embodiment, it is formed at least at the height of the upper surface of the floating gate electrode, and in a more preferred embodiment, it is formed to the height of the upper surface of the control gate electrode.

The method of the present invention for manufacturing the above semiconductor memory device by the three-layer polysilicon process includes the following steps (A) to (E) in that order . (A) a step of forming a stack gate electrode having a two-layer polysilicon structure in a memory region on a semiconductor substrate via a gate oxide film,
(B) a step of depositing an insulating film by a CVD method, (C) a step of anisotropically etching the insulating film to form a side wall of the insulating film on a side surface of the stack gate electrode,
(D) A step of forming a gate oxide film of the peripheral transistor, (E) A step of depositing and patterning a polysilicon film to form a gate electrode of the peripheral transistor in the peripheral transistor region.

The method of the present invention for manufacturing the above semiconductor memory device by the two-layer polysilicon process includes the following steps (A) to ( E ) in that order . (A) A floating gate electrode made of a polysilicon film is provided in a memory region on a semiconductor substrate via a gate oxide film, and the floating gate electrode is provided thereon.
Forming a laminated body with the first insulating film made of the formed ONO film , ( B ) depositing the second insulating film by the CVD method, and ( C ) anisotropically etching the second insulating film. Giving,
Step of forming a side wall of the second insulating film on the side surface of the floating gate electrode, step of forming a gate oxide film of ( D ) peripheral transistor, ( E ) depositing and patterning a polysilicon film to form a control gate in the memory region Forming an electrode and forming a gate electrode of the peripheral transistor in the peripheral transistor region. Here, the step (A) is
Includes two methods. One is the memo on the semiconductor substrate
Polysilicon film is deposited on the gate region through the gate oxide film
Then, pattern and stack the stack gate electrode in the memory area.
After forming the floating gate electrode,
Provided on the gate electrode and between the control gate electrode
Is a step of forming a first insulating film. The other one
Is a semiconductor substrate, as in the embodiment of FIG.
Polysilicon film in the upper memory area through the gate oxide film
Is deposited, a first insulating film is formed on the
In the step of patterning the silicon film and the first insulating film
It

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example in which the present invention is applied to a method for manufacturing an EPROM by a three-layer polysilicon process will be described with reference to FIGS. (A) A silicon oxide film 3 for element isolation is formed on a P-type silicon substrate 2 by an element isolation method such as a known LOCOS method, and after a necessary threshold voltage control implantation is completed, gate oxidation is performed on the substrate 2. The film 4 is formed. A lower layer polysilicon film for the floating gate electrode is deposited thereon, and the lower layer polysilicon film is patterned so as to separate the floating gate electrode perpendicularly to the word line direction (the direction perpendicular to the paper surface in the figure). . Then, an ONO film having a three-layer structure of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed thereon as an interlayer insulating film. After that, after depositing an upper layer polysilicon film on the entire surface, a resist pattern for the stack gate electrode is formed by photolithography, and anisotropic etching is performed using the resist pattern as a mask to form the stack gate electrode of the memory. The stack gate electrode is composed of a floating gate electrode 6 made of polysilicon, an ONO film 8 on the floating gate electrode 6, and a control gate electrode 10 made of polysilicon in the uppermost layer. The control gate electrode 10 is a strip-shaped pattern extending in the word line direction (the direction perpendicular to the paper surface) and is continuous for a plurality of memory elements.

(B) A resist pattern 40 having an opening in the memory region is formed by photolithography, and N-type impurities such as arsenic are ion-implanted into the source region and the drain region of the memory. 42 is the implanted impurities. (C) After removing the resist, a high temperature oxide film is deposited to a thickness sufficiently formed on the side surface of the stack gate electrode of the memory, and then the high temperature oxide film is subjected to an etch back process to oxidize the side surface of the stack gate electrode of the memory. Membrane sidewall 44
To form. The oxide film side wall 44 is thick at the bottom and thin at the top.

(D) By performing a heat treatment for rounding the edges of the floating gate electrode 6 and the control gate electrode 10 of the stack gate electrode and an oxidation treatment that also activates the impurities 42 implanted in the source / drain regions, The floating gate electrode 6 of the stack gate electrode and the control gate electrode 10 are covered with a thermal oxide film 46, and a sacrificial oxide film 48 is formed in the peripheral transistor region. The oxidizing conditions at this time are, for example, wet oxidation or dry oxidation at 900 to 950 ° C. Boron ions 50 are ion-implanted into the peripheral transistor region using the sacrificial oxide film 48 as a through oxide film for controlling the threshold voltage.

(E) After removing the oxide film 48 by wet etching, the gate oxide film 52 is formed in the peripheral transistor region.
Is formed, and a polysilicon film 54 which will be the gate electrode of the peripheral transistor is deposited on it. (F) A resist pattern for the gate electrode of the peripheral transistor is formed by photolithography, and anisotropic polysilicon etching is performed using the resist pattern as a mask to form the gate electrode 56 of the peripheral transistor. At this time, the insulating film sidewall 44 is already formed on the side surface of the stack gate electrode in the memory region, and the surface of the insulating film sidewall 44 is an inclined surface, so that the polysilicon film 54 is formed in the memory region. Will never remain.

(G) After that, a source / drain region having an LDD structure is formed for the peripheral transistor by a known method. Reference numeral 58 is a low-concentration impurity region of the source / drain forming the LDD structure, and 62 is a high-concentration impurity region.
Reference numeral 60 is a high temperature oxide film sidewall spacer for forming the source / drain regions of the LDD structure. The sidewall spacer 62 is formed by depositing a high temperature oxide film on the entire surface and etching it back. However, since the insulating film sidewall 44 has already been formed in the memory region, the high temperature oxide film side is formed in the memory region. No wall spacer is formed.

As described above, in the embodiments of FIGS. 4 and 5, the oxide film side wall 44 is already formed on the side surface of the stack gate in the memory region before depositing the polysilicon film for the gate electrode of the peripheral transistor. Therefore, the polysilicon film for the peripheral transistor does not remain as a sidewall in the memory region. Therefore, the process for removing the polysilicon side wall in the memory region as in the past is not necessary. Further, since the oxide film side wall 44 in the memory region remains so as to cover the entire side surface of the stack gate electrode in the memory region even after the LDD side wall spacer of the peripheral transistor is formed, it acts as a block when mobile ions enter from the outside. However, resistance to charge loss is improved, and memory retention characteristics are improved.

A semiconductor memory device is completed by depositing an interlayer insulating film from the state of FIG. 5G, forming a contact hole in the interlayer insulating film at the connection position, forming a metal wiring, and forming a passivation film .

An embodiment in which the present invention is applied to an EPROM or an EEPROM of a two-layer polysilicon process will be described with reference to FIG. (A) After element isolation is performed by the LOCOS method or the like, the gate oxide film 4 is formed on the P-type silicon substrate 2 after the necessary implantation for controlling the threshold voltage is completed. EEPRO
In the case of M, a tunnel oxide film is formed thereafter. (B) From the lower polysilicon film and the ONO film on it
Comprising an insulating film is formed, a resist is formed by photolithography, etched by using the resist pattern as a mask, the insulation thereon the floating gate electrode 6 film 8
To form.

(C) After removing the resist, a high temperature oxide film is deposited and etched back to form the lower polysilicon film 6
An oxide film side wall 70 is formed on the side surface of the. (D)
Then, after forming a gate oxide film in the peripheral transistor region, an upper polysilicon film is deposited. The upper polysilicon film becomes the control gate electrode in the memory area,
It is used as a gate electrode in the peripheral transistor region. The upper polysilicon film is patterned by photolithography and etching, and control is performed in the memory area.
The gate electrode 10 is formed, and the gate electrode is formed in the peripheral region. When patterning this upper polysilicon film,
An oxide film sidewall 70 is formed on the side surface of the lower polysilicon film.
Is already formed, no polysilicon film remains on the side surface of the floating gate electrode 6.

A wet etching step for removing the sacrificial oxide film covering the substrate in the peripheral transistor region is performed between the steps (C) and (D) of FIG. 6, but the etching also results in the oxide film sidewall. 70 remains.

Although the silicon oxide films are illustrated as the sidewalls 44 and 70 in the embodiments of FIGS. 4 and 5 and the embodiment of FIG. 6, they may be replaced with silicon nitride films. The silicon nitride film is a denser insulating film than the silicon oxide film, and has a function of effectively shielding the invasion of mobile ions from the outside. Further, the conductivity types of the substrate and the source / drain regions may be reversed from those in the embodiment.

[0027]

In the semiconductor memory device manufactured according to the present invention, since the side wall of the insulator is formed on the side surface of the stack gate electrode, at least the side surface of the floating gate electrode, the retention characteristic of the memory is improved. In the manufacturing method of the present invention, the insulating film sidewall is already formed on the side surface of the floating gate of the memory or the side surfaces of the floating gate and the control gate before the step of depositing the polysilicon film for the gate electrode for the peripheral circuit. The silicon film does not remain around the floating gate electrode, and problems such as short circuit are eliminated and the manufacturing yield is improved. Since the step of removing the polysilicon side wall in the memory area as in the past is not necessary, the manufacturing period can be shortened and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a conventional three-layer polysilicon process.

FIG. 2 is a process sectional view showing a conventional two-layer polysilicon process.

FIG. 3 is a process sectional view showing a problem in the conventional process of FIG.

FIG. 4 is a process sectional view showing a first half of a process of an embodiment in which the present invention is applied to a three-layer polysilicon process.

FIG. 5 is a process sectional view showing a latter half of the processes of the same example in which the present invention is applied to a three-layer polysilicon process.

FIG. 6 is a process sectional view showing an embodiment in which the present invention is applied to a two-layer polysilicon process.

[Explanation of symbols]

2 Silicon substrate 4 Gate oxide film in memory area 6 Floating gate electrode 8 insulating film 10 Control gate electrode 44,70 Oxide film sidewall

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-1-119070 (JP, A) JP-A-4-302174 (JP, A) JP-A-4-323877 (JP, A) JP-A-2- 10875 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/10 481 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A method of manufacturing a non-volatile semiconductor memory device, which includes the following steps in that order . (A) a step of forming a stack gate electrode having a two-layer polysilicon structure in a memory region on a semiconductor substrate via a gate oxide film, (B) a step of depositing an insulating film by a CVD method, (C) ) A step of anisotropically etching the insulating film to form a side wall of the insulating film on the side surface of the stack gate electrode, (D) a step of forming a gate oxide film of a peripheral transistor, and (E) a polysilicon film. Depositing and patterning to form a peripheral transistor gate electrode in the peripheral transistor region. 2. A method of manufacturing a non-volatile semiconductor memory device, which includes the following steps in that order . (A) A floating gate electrode made of a polysilicon film is formed in the memory region on the semiconductor substrate via a gate oxide film.
Product with the first insulating film made of an ONO film provided on
A step of forming a layered body , ( B ) a step of depositing a second insulating film by a CVD method, ( C ) anisotropic etching of the second insulating film, and a second insulating film on the side surface of the floating gate electrode. Forming sidewalls by ( D ) forming gate oxide film of peripheral transistor, ( E ) depositing and patterning a polysilicon film to form a control gate electrode in a memory region, and forming a peripheral transistor in the peripheral transistor region. Forming the gate electrode of.