JP2938290B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for suppressing the reduction of an element isolation region due to etching to enhance insulation between elements.

[0002]

2. Description of the Related Art Generally, in the manufacture of a semiconductor memory device, a peripheral transistor region is provided at a peripheral portion of a memory cell region for forming a memory cell. In the memory cell region and the peripheral transistor region, the electrodes are conventionally formed as follows.

FIGS. 4 and 5 show a part of a manufacturing process of an E ² PROM. As shown in FIG. 4A, a gate oxide film 14 and an element isolation film 10 are provided on the upper surface of the p-type silicon substrate 2.
The memory cell region M1 is a region for forming a memory cell, and the peripheral transistor region T1 is a region for forming a transistor.

On the gate oxide film 14 in the memory cell region M1, polysilicon as a material of a floating gate is selectively deposited as a first polysilicon layer 16.
Further, on the entire surface of the device including the first polysilicon layer 16, an ONO film 18 is formed as an inter-gate insulating film.

Since the ONO film 18 is a structure of a memory cell, the ONO film 18 in the peripheral transistor region T1 is removed by etching (FIG. 4B). Thereafter, polysilicon, which is a material of the control gate, is deposited on the entire surface of the structure to form a second polysilicon layer 20 (FIG. 5A).

A resist is applied on the second polysilicon layer 20 and patterned into a shape of a gate electrode. Etching is performed using the resist as a mask, and the floating gate 22 of the first polysilicon layer 16 and the ONO
A gate structure 28 composed of the inter-gate insulating film 24 of the film 18 and the control gate 26 of the second polysilicon layer 20 is obtained (FIG. 5B). The peripheral transistor region T1 is also etched at the same time to form the control gate 30 made of the second polysilicon layer 20.

[0007]

However, the conventional method for manufacturing a semiconductor memory device as described above has the following problems. 5A, the first polysilicon layer 16, the ONO film 18, and the second polysilicon layer 20 are removed by etching, and a gate structure 28 is formed in the memory cell region M1.
Is formed, the etching of the peripheral transistor region T1 also proceeds. Since the etching is performed under conditions suitable for forming the gate structure 28, the etching proceeds excessively in the peripheral transistor region T1 where the second polysilicon layer 20 is merely applied, and the element isolation film 10 is reduced. For this reason,
In the transistor formed in the peripheral transistor region T1, the insulation between the elements was reduced.

In order to cope with the above problem, there is also a method of forming the element isolation film 10 thicker in advance in anticipation of the reduction of the element isolation film 10. However, in this case, the heat treatment must be performed for a long time, and a large thermal stress is applied to the substrate.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor memory device which solves the above-mentioned problems, suppresses a decrease in an element isolation film due to etching, and can enhance insulation between elements. And

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming a gate oxide film and an inter-element insulating film by a first layer provided on a substrate;
After uniformly forming the layer, the second layer is left in the memory cell region.
Remove the floating gate
A second step of forming an insulating material after the second step
After uniformly forming the third layer of the memory cell area
The pattern is removed so as to leave the third layer, and between the gates
After the third step of forming the insulating film and the third step, the fourth layer is formed uniformly, and then the memory cell region and the peripheral layer are formed .
Pattern removal to leave the fourth layer in the transistor region
Leaving a fourth step of forming a control gate ,
In the third step, the inter-element insulating film itself is provided.
In order to prevent the film thickness of the
Also, it is characterized in that the third layer is removed by patterning.
Sign.

[0011] The method according to claim 2, 3
The layer is an ONO film.

[0012]

[0013]

[0014]

[0015]

[0016]

According to the manufacturing method of the first aspect, the first method is to
When patterning three layers to form an inter-gate insulating film
The fact that the third layer is also left on the inter-element insulating film
Features. As a result, in the fourth step, the device
The edge film is prevented from being removed, and the memory cell area and the peripheral
The insulating property of the element formed in the transistor region is improved.

[0017] In the manufacturing method of the second aspect, the third layer may be an ON state.
It is characterized by being an O film. Therefore, ONO
The invention can also be applied to an element using a film.

[0018]

[0019]

[0020]

[0021]

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor memory device according to one embodiment of the present invention will be described with reference to the drawings. An E ² PROM is formed in a memory cell area as a first element area, and a peripheral transistor area as a second element area is provided in a peripheral portion of the memory cell area.

First, as shown in FIG. 1A, a p-type silicon substrate 2 is oxidized to form a silicon oxide film 4 on the upper surface.
In order to perform element isolation by the LOCOS (Local Oxidation of Silicon) method, the silicon oxide film 4 is formed by CVD (Chemic
al Vapor Deposition) to cover with a silicon nitride film (not shown). The silicon nitride film is removed by etching using a resist pattern except for a portion corresponding to an element formation region. In this state, oxidation is performed in an atmosphere of water vapor (H ₂ O) to form an element isolation film 10 which is an inter-element insulating film in a portion not covered with the silicon nitride film. The remaining silicon nitride film and the silicon oxide film 4 under the silicon nitride film are sequentially removed to expose the silicon surface and form an element formation region 12 (FIG. 1B).

From the state of FIG. 1B, boron ions are implanted into the p-type silicon substrate 2 to adjust the channel concentration (channel ion implantation). After that, the surface of the element forming region 12 is heat-treated to form a gate oxide film as a first insulating film.
14 are formed (FIG. 1C).

Next, in order to form a memory cell in the memory cell region M1, first, polysilicon is deposited on the entire surface of the structure shown in FIG. 1C by the CVD method. Using the resist (not shown) as a mask, the polysilicon is etched to remove the polysilicon in the peripheral transistor region T1. Thereby, as shown in FIG. 1C, polysilicon as a material of the floating gate is selectively deposited on the surface of the memory cell region M1. The polysilicon selectively deposited in this manner is replaced with a first polysilicon layer as an intermediate layer.
16 The first polysilicon layer 16 is ion-implanted with phosphorus to form an n ⁺ polysilicon layer.

Further, the surface of the structure shown in FIG. 1C is oxidized to form an oxide film, a nitride film is deposited thereon by a CVD method, and the surface of the nitride film is oxidized to form an oxide film—nitride film—. ONO which is a second insulating film having a three-layer structure of an oxide film
A film 18 is formed (FIG. 2A). The ONO film 18 is formed on the entire surface of the device and functions as an inter-gate insulating film. Thereafter, the ONO film 18 in the peripheral transistor region T1 is removed by etching using a resist pattern. Thus, only the memory cell region M1 and the element isolation film 10 are covered with the ONO film 18 (FIG. 2B).

Further, polysilicon as a control gate material is deposited on the entire surface of the structure shown in FIG. 2B by a CVD method, and a second polysilicon layer 20 as a conductive layer is provided (FIG. 3A). A resist (not shown) is applied on the second polysilicon layer 20, and is patterned into a shape of a gate electrode of a memory cell and a transistor. The resist is used as a mask to etch the memory cell region M1 and the peripheral transistor region T1. A gate structure 28 composed of the control gate 26 is obtained. The control gate 30 of the second polysilicon layer 20 is formed in the peripheral transistor region T1. In the part of the element isolation film 10, the ONO film 18 is removed by etching. Since the etching process does not reach the element isolation film 10, the element isolation film 10 does not decrease (FIG. 3B).

From this state, after forming a source and a drain in the element forming region 12, an interlayer film is provided, an Al wiring is formed, and a memory element and a peripheral transistor are obtained by covering with an passivation film.

In this embodiment, E ² P
Although the ROM is formed, other memory elements such as a trap memory and a ferroelectric memory may be formed.

[0030]

According to the manufacturing method of the first aspect, the insulating material is used.
The third layer to form an inter-gate insulating film
The third layer on the inter-element insulating film
It is characterized by. Thereby, in the fourth step, the element
To prevent the inter-layer insulation film from being removed,
Enhance the insulation of devices formed in the side transistor region
You. Therefore, elements in the memory cell area and peripheral transistors
The elements in the star region can be reliably insulated.

[0031] In the manufacturing method of the second aspect, the third layer may be an ON state.
It is characterized by being an O film. Therefore, ONO
A similar effect can be obtained in a device using a film.
You.

[0032]

[0033]

[0034]

[0035]

[Brief description of the drawings]

FIG. 1 is a diagram showing a method of manufacturing a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is another diagram showing the method of manufacturing the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is still another view showing the method of manufacturing the semiconductor memory device according to one embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing a semiconductor memory device according to a conventional method.

FIG. 5 is another diagram showing the method of manufacturing the semiconductor memory device by the conventional method.

[Explanation of symbols]

 2. Silicon substrate 10 Element isolation film 14 Gate oxide film 16 First polysilicon layer 18 ONO film M1 Memory cell area T1 ... Peripheral transistor area 20 ... Second polysilicon layer 22 ... Floating gate 24 ... Inter-gate insulating film 26,30 ... Control gate

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 29/792 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/8247 H01L 21/8234 H01L 27/088 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] A memory cell separated by an inter-element insulating film.
A method of manufacturing a semiconductor device having a gate region and a peripheral transistor region, comprising: a first step of forming a gate oxide film and an inter-element insulating film by a first layer provided on a substrate; After forming the second layer uniformly, the memory
Pattern removal to leave the second layer in the cell area
After the second step of forming a floating gate, after the second step, a third layer made of an insulating material is uniformly formed, and the pattern is formed so as to leave the third layer in the memory cell region.
And Ningu removed, a third step of forming a gate insulating film, after the third step, after the fourth layer is uniformly formed, the memory
Leaving the fourth layer in the cell region and the peripheral transistor region
Pattern to remove the control gate
A fourth step of forming , wherein in the third step, the thickness of the inter-element insulating film itself is reduced.
In order to prevent the decrease, the above-mentioned
Characterized by patterning removal while leaving the third layer
A method for manufacturing a semiconductor device. 2. A method for manufacturing a semiconductor device according to claim 1, wherein
Te, wherein the third layer, which is characterized in that an ONO film.