JPH0563206A - Manufacture of nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To make a photolithography process unnecessary and to limit each thickness of the second and third insulating films at will, by leaving a second electrode material film in a peripheral transistor region, and forming the second insulating film in a memory cell region and the third insulating film in the peripheral transistor region by individual processes. CONSTITUTION:The second polycrystal silicon film 6 patterned so as to cover a peripheral circuit part 21 when a memory cell part 20 is formed is used as it is as a mask, when impurities are implanted into the source and drain regions 8 and 9 of the memory cell part 20. This makes it unnecessary to have an exclusive photolithography process for implanting the impurities into the source and drain regions 8 and 9 of the memory cell part 20. Besides, the second oxygen film 5A and third oxide film 12 are formed in the memory cell part 20 and in the peripheral circuit part 21 respectively by separate processes. And this makes it possible to control the thicknesses of both films 5A and 12 to their respective desired values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly to a method for manufacturing a nonvolatile semiconductor memory device having a two-layer gate electrode structure.

[0002]

2. Description of the Related Art FIGS. 15 to 21 are sectional views showing a method of manufacturing a conventional nonvolatile semiconductor memory device in the order of steps. First, as shown in FIG. 15, a field oxide film 2 and a first oxide film 3 are formed on a surface of a silicon substrate 1 by a known method, and a first polycrystalline silicon film (floating film) is formed in a memory cell portion 20. After the gate) 4 is patterned, the first oxide film 3 of the peripheral circuit portion 21 is removed.

Then, as shown in FIG. 16, second oxide films 5A and 5B are formed by a known method, and then a second polycrystalline silicon film 6 is formed on the entire surface. Then, the patterning mask 7 is formed over the entire area of the peripheral circuit portion 21 and the memory cell portion 2.
It is formed so as to cover the gate portion of 0.

After that, as shown in FIG. 17, the gate portion of the memory cell portion 20 is formed by etching the polycrystalline silicon film 6, the oxide film 5A and the polycrystalline silicon film 4 using the mask 7 as a mask. Then, after removing the patterning mask 7, the patterning mask 23 is removed.
It is formed so as to cover the entire area of the memory cell section 20 and the gate section of the peripheral circuit section 21.

Subsequently, as shown in FIG. 18, the gate portion of the peripheral circuit portion 21 is formed by patterning the polycrystalline silicon film 6 leaving the portion covered by the mask 23. Next, after removing the patterning mask 23, the patterning mask 24 is selectively formed so that the portions of the memory cell section 20 that will be the source / drain regions are exposed. Then, using the mask 24 and the polycrystalline silicon films 4 and 6 as masks, impurities are introduced into the regions where the cell source region 8 and the cell drain region 9 are to be formed in the memory cell portion 20 on the surface of the substrate 1.

Thereafter, as shown in FIG.
Then, thermal diffusion is performed to form the cell source region 8 and the cell drain region 9 in the memory cell section 20. Next, the patterning mask 25 is selectively formed so as to cover the memory cell section 20. Using the patterning mask 25 and the polycrystalline silicon film 6 as masks, the peripheral source region 15 and the peripheral drain region 1 of the peripheral circuit portion 21 are formed.
Impurities are introduced into the region where 6 is to be formed.

Further, as shown in FIG. 20, after removing the patterning mask 25, thermal diffusion is performed to form the peripheral source region 15 and the peripheral drain region 16.

Finally, as shown in FIG. 21, after depositing an interlayer insulating film 27 on the entire surface, a contact hole 18 is formed in the interlayer insulating film 27. Then, when the metal wiring 19 is formed so as to be embedded in the contact hole 18, as shown in FIG.
A semiconductor memory device having the structure shown in is obtained.

Now, the necessity of separately forming the source / drain regions of the memory cell section 20 and the peripheral transistor circuit section 21 will be described. In recent years, non-volatile semiconductor memory devices typified by EPROMs have been increasing in capacity, that is, highly integrated circuits. As a result, the gate lengths of memory cells and peripheral transistors are being miniaturized. As the gate length becomes smaller, the withstand voltage between the source and drain of the transistor cannot be maintained. As a measure against this, in the peripheral transistor circuit portion 21, it is necessary to form the source / drain regions 15 and 16 shallowly.

However, it is disadvantageous to form the source / drain regions 8 and 9 of the memory cell portion 20 shallow in terms of writing efficiency. Therefore, the source of the memory cell
The drain region is deep, while the source and
The need arises to make the drain region shallow. When the gate length is comparatively long, even if the memory cell and the source / drain region of the peripheral transistor are formed at the same time, a sufficient withstand voltage between the source and drain of the peripheral transistor could be secured. Since the length is shortened, there occurs a situation in which the withstand voltage between the source and drain of the peripheral transistor cannot be ensured as described above. In order to solve this, it is necessary to separately form the source / drain regions of the memory cell and the peripheral transistor.

[0011]

However, the conventional method of manufacturing a semiconductor memory device has the following drawbacks.

First, in the conventional manufacturing method, after patterning the gate portion of the memory cell portion 20 and the gate portion of the peripheral circuit portion 21, the cell source region 8 is formed by different PR (photolithography) steps. And cell drain region 9, peripheral source region 15 and peripheral drain region 16
Therefore, it is necessary to separately provide a PR process for forming the source / drain regions of the memory cell section 20, which causes problems such as an increase in manufacturing period and an increase in cost.

Secondly, in the conventional manufacturing method, the gate oxide film 5A of the memory cell portion 20 and the gate oxide film 5B of the peripheral circuit portion 21 are formed at the same time (at the same temperature and at the same time). However, there was a problem that the film thickness could not be controlled.

The present invention has been made in view of the above problems, and the source / drain region of the peripheral circuit portion and the memory can be formed without separately providing a PR process for forming the source / drain region of the memory cell portion. The source / drain regions of the cell portion can be formed under different conditions, and the oxide film on the floating gate of the memory cell portion and the gate oxide film of the transistor of the peripheral circuit portion can be controlled to have desired thicknesses. An object is to provide a method for manufacturing a non-volatile semiconductor memory device.

[0015]

A method for manufacturing a non-volatile semiconductor memory device according to the present invention is a non-volatile semiconductor memory having a two-layer gate electrode structure in which a memory cell transistor and a peripheral circuit transistor are formed on the same substrate. In the method of manufacturing a device, a step of forming an element isolation insulating film on a surface of a silicon substrate and forming a first insulating film in a memory cell region, and a step of patterning a first electrode material film in the memory cell region. A step of forming a second insulating film, a step of forming a second electrode material film on the entire surface, and masking the entire peripheral transistor region and the gate electrode formation planned region of the memory cell region. Second electrode material film and second
Selectively etching the insulating film to form a memory cell gate electrode, and using the memory cell gate electrode as a mask to selectively introduce impurities into the substrate surface to form a source / drain region of the memory cell region. Forming process,
Patterning a first interlayer insulating film in the memory cell region, removing the second electrode material film and the second insulating film in the peripheral transistor region, and forming a third insulating film in the peripheral transistor region. A step of forming a third electrode material film in the peripheral transistor region and patterning it to form a peripheral gate electrode, and a step of forming source / drain regions of the peripheral transistor region. To do.

[0016]

In the present invention, when the memory cell gate electrode is formed, the entire area of the peripheral transistor region is also masked to etch the first and second electrode material films and the like. Therefore, after this step, The second electrode material film remains in the peripheral transistor region. Therefore, when the source / drain regions are formed in the memory cell region by introducing impurities in the next step, this second electrode material film can be used as a mask for impurities in the peripheral transistor region. Therefore, the photolithography process for forming the source / drain regions of the memory cell region is unnecessary.

Further, since the second insulating film on the floating electrode in the memory cell region and the third insulating film (gate insulating film) in the peripheral transistor region are formed in separate steps, the film thicknesses thereof are different from each other. It can be controlled arbitrarily.

[0018]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

1 to 8 are sectional views showing a method of manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1, for example, a field oxide film 2 having a thickness of, for example, 8000Å and a thickness of, for example, 200Å are formed on the surface of a P-type silicon substrate 1 by a known method.
After forming the first oxide film 3 of
First polycrystalline silicon film 4 doped with N-type impurities
Is patterned with a thickness of 2000Å, for example. Then, the first oxide film 3 formed on the peripheral circuit portion 21 is removed.

Next, as shown in FIG. 2, the surface of the first polycrystalline silicon film 4 is oxidized at a high temperature of, for example, 1150 ° C.,
The second oxide film 5 with a thickness of 200Å on a silicon substrate, for example
Form A and 5B. Further, a second polycrystalline silicon film 6 having a thickness of, for example, 3000 Å doped with N-type impurities is grown on the second oxide films 5A and 5B, and a patterning mask 7 such as a resist is used for the transistor of the memory cell section 20. It is selectively formed so as to cover the entire gate portion and the entire peripheral circuit portion 21.

Subsequently, as shown in FIG. 3, the polycrystalline silicon films 4 and 6 and the oxide film 5A of the memory cell portion 20 are selectively etched using the patterning mask 7 as a mask,
A gate electrode part is formed. Then, after removing the patterning mask 7, the substrate surface is doped with N-type impurities such as arsenic using the gate electrode portion as a mask.
By applying heat treatment at 900 ° C., the memory cell unit 20
Then, a cell source region 8 and a cell drain region 9 are formed.

Subsequently, as shown in FIG. 4, a first interlayer insulating film 10 made of, for example, a TEOSBPSG film having a thickness of 5000 Å is deposited on the entire surface, and a sufficient heat treatment is applied to the first interlayer insulating film 10. After flattening the surface of, the patterning mask 11 such as a resist is patterned so as to cover the memory cell section 20.

Next, as shown in FIG. 5, using the patterning mask 11 as a mask, the first interlayer insulating film 10 of the peripheral circuit portion 21, the second polycrystalline silicon film 6, and the second oxide film are formed. 5B and 5B are selectively etched and removed.

Then, after the patterning mask 11 is removed, as shown in FIG. 6, a region of the peripheral circuit portion 21 which will be a gate portion is exposed to a third atmosphere having a thickness of 200 Å in a steam atmosphere at 900 ° C., for example. The oxide film 12 is formed. Next, for example, a third polycrystalline silicon film 13 having a thickness of 3000 Å doped with N-type impurities is grown on the entire surface, and a patterning mask 14 made of a resist or the like is formed on a portion which will be a gate electrode of the peripheral circuit portion 21. Selectively formed.

Next, as shown in FIG. 7, the third polycrystalline silicon film 13 is etched using the patterning mask 14 as a mask, and the remaining polycrystalline silicon film 13 is used to form the gates of the transistors in the peripheral circuit portion 21. Form electrodes. Then, after removing the patterning mask 14, impurities are introduced into the substrate surface by using the polycrystalline silicon film 13 (gate electrode portion) as a mask and heat treatment is performed, so that the source / drain regions 15 and 16 are formed in the peripheral circuit portion 21.
To form.

Finally, as shown in FIG.
After depositing a second interlayer insulating film 17 of 5000 Å TEOSBPSG film or the like on the entire surface and performing sufficient heat treatment to flatten the surface of the second interlayer film 17, the interlayer insulating film 1
A contact hole 18 is opened in 7 and a metal wiring 19 is patterned by using, for example, aluminum or the like. As a result, the semiconductor memory device having the structure shown in FIG. 8 is manufactured.

Conventionally, a separate PR process was required to form the source / drain regions 8 and 9 of the memory cell portion 20, whereas in the present embodiment, these source / drain regions 8 and 9 are formed. A dedicated PR process for forming is unnecessary. That is, in this embodiment, the memory cell unit 2
When the impurity is introduced into the source / drain regions 8 and 9 of 0, the second polycrystalline silicon film 6 patterned so as to cover the peripheral circuit portion 21 when forming the gate of the memory cell portion 20 is left as it is. It can be used as a mask, and it is not necessary to provide a dedicated PR process for introducing impurities into the source / drain regions 8 and 9 of the memory cell section 20. Further, the second oxide film 5A and the third oxide film 12 having desired film thicknesses can be formed in the memory cell unit 20 and the peripheral circuit unit 21, respectively.

Next, a second embodiment of the present invention will be described.

9 to 14 are sectional views showing the method of the second embodiment of the present invention step by step. First, as shown in FIG. 9, the second polycrystalline silicon film 6 is patterned in the entire area of the gate portion of the memory cell portion 20 and the peripheral circuit portion 21 to form the source / drain regions 8 and 9 of the memory cell portion 20. The process up to this point is similar to that of the first embodiment.
Corresponding to.

Next, as shown in FIG. 10, for example, 900
The side surface oxide film 22 is removed in a dry oxygen atmosphere at ℃ for example 180Å
Of TEOSB with a thickness of, for example, 5000 Å
A first interlayer insulating film 10 made of a PSG film or the like is deposited on the entire surface, and a sufficient heat treatment is applied to flatten the surface of the first interlayer insulating film 10. Then, a nitride film 23 having a thickness of, for example, 500 Å is deposited on the entire surface, and then a patterning mask 11 made of a resist or the like is selectively formed so as to expose only the peripheral circuit portion 21.

Next, as shown in FIG. 11, using the patterning mask 11 as a mask, the nitride film 2 of the peripheral circuit portion 21 is formed.
3, the interlayer insulating film 10, the side surface oxide film 22 and the polycrystalline silicon film 6 are selectively etched and removed. Next, after removing the patterning mask 11, the second oxide film 5B of the peripheral circuit portion 21 is removed. Then, the peripheral circuit section 21
After forming the third oxide film 12 having a thickness of, for example, 180 Å, the third polycrystalline silicon film 13 is formed at a thickness of, for example, 3000 Å
Then, the patterning mask 14 such as a resist is selectively formed so as to cover the gate portion of the peripheral circuit portion 21.

Subsequently, as shown in FIG. 12, the polycrystalline silicon film 13 is etched using the patterning mask 14 as a mask to form the gate of the peripheral circuit portion 21. Then, after removing the patterning mask 14, using the polycrystalline silicon film 13 (gate electrode) as a mask, the substrate surface is doped with an N-type impurity such as phosphorus at a low concentration of, for example, 3 × 10 ¹³ cm ^-2 , A peripheral source region 24 having a low impurity concentration and a peripheral drain region 25 having a low impurity concentration are formed in the peripheral circuit portion 21. After that, an interlayer insulating film 26 having a good shape with a thickness of 2000 Å is deposited on the entire surface by, for example, low pressure chemical vapor deposition.

Subsequently, as shown in FIG. 13, the interlayer insulating film 26 having good shape is etched back, and the insulating film 13 is used as a sidewall only on the sidewall of the third polycrystalline silicon film 13 of the peripheral circuit portion 21. leave. Next, an N-type impurity such as arsenic is doped at a high concentration, for example, 5 × 10 ¹⁵ cm ⁻² , and the peripheral source region 15 is formed in the peripheral circuit portion 21.
And the peripheral drain region 16 is formed.

Finally, as shown in FIG. 14, a second interlayer insulating film 17 made of, for example, a TEOSBPSG film having a thickness of 5000 Å is deposited on the entire surface, and a sufficient heat treatment is applied to this second interlayer insulating film. The surface of 17 is flattened. Thereafter, a contact hole 18 is provided in the interlayer insulating film 17, and a metal wiring 19 made of, for example, aluminum is patterned to manufacture the semiconductor memory device of this embodiment.

The feature of this second embodiment is that the side wall of the floating gate 4 of the memory cell portion 20 is covered with the side surface oxide film 22.
And the presence of the nitride film 23 on the first interlayer insulating film of the memory cell section 21 and the source / drain regions 15 and 16 of the peripheral circuit section 21 having a lower impurity concentration than the gate sidewall. The existence of drain regions 24 and 25.

In this way, the memory cell portion can prevent invading ions such as sodium ions from the outside of the semiconductor chip, so that the effect of improving the memory retention characteristic of information by one digit can be obtained.

In addition, the withstand voltage between the source and drain of the transistor in the peripheral circuit portion was 12 V in the related art,
In order to improve V, the gate length of the transistor in the peripheral circuit part can be reduced from 1.4 μm to 1.0 μm, and as a result, the chip size can be reduced.

[0039]

As described above, according to the present invention, the second electrode material film is patterned and left in the peripheral transistor region in the etching step for forming the gate in the memory cell region. When the impurity is introduced into the drain region, this second electrode material film can be used as it is as a mask. Therefore, it is not necessary to provide a dedicated PR process for forming the source / drain regions of the memory cell region as in the conventional case, and the source / drain of the peripheral transistor region and the source / drain region of the memory cell region are separately provided. It is possible to form under the conditions of. Further, since the insulating film on the floating gate in the memory cell region and the gate insulating film in the peripheral transistor region are formed in separate steps, there is an effect that each can be controlled to a desired thickness.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first step of a method for manufacturing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a second step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a third step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a fourth step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a fifth step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.

FIG. 6 is a sectional view showing a sixth step of the method for manufacturing the nonvolatile semiconductor memory device according to the first example of the present invention.

FIG. 7 is a cross-sectional view showing a seventh step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.

FIG. 8 is a sectional view showing an eighth step of the method for manufacturing the nonvolatile semiconductor memory device according to the first example of the present invention.

FIG. 9 is a cross-sectional view showing a first step of a method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a second step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a third step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a fourth step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the second embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a fifth step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the second embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a sixth step of the method for manufacturing the nonvolatile semiconductor memory device in accordance with the second embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a first step of a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 16 is a cross-sectional view showing a second step of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 17 is a cross-sectional view showing a third step of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 18 is a cross-sectional view showing a fourth step of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 19 is a cross-sectional view showing a fifth step of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 20 is a cross-sectional view showing a sixth step of the conventional method for manufacturing a nonvolatile semiconductor memory device.

FIG. 21 is a cross-sectional view showing a seventh step of the conventional method for manufacturing a nonvolatile semiconductor memory device.

[Explanation of symbols]

 1; Silicon substrate 2; Field oxide film 3; First oxide film 4; First polycrystalline silicon film 5A, 5B; Second oxide film 6; Second polycrystalline silicon film 7, 11, 14; Patterning Mask 8; Cell source region 9; Cell drain region 10; First interlayer insulating film 12; Third oxide film 13; Third polycrystalline silicon film 15; Peripheral source region 16; Peripheral source / drain region 17; 2 interlayer insulating film 18; contact hole 19; metal wiring 20; memory cell part 21; peripheral circuit part 22; side oxide film 23; nitride film 24; peripheral source region 25 with low impurity concentration; peripheral drain region with low impurity concentration 26: Interlayer insulating film having good shape 27: Interlayer insulating film

Claims (2)

[Claims] 1. A method of manufacturing a nonvolatile semiconductor memory device having a two-layer gate electrode structure, in which a memory cell transistor and a peripheral circuit transistor are formed on the same substrate, wherein an element isolation insulating film is formed on a surface of a silicon substrate. Forming a first insulating film in the memory cell region, patterning a first electrode material film in the memory cell region, second
Forming an insulating film, forming a second electrode material film on the entire surface, masking the entire peripheral transistor region and the gate electrode formation planned region of the memory cell region, and the first and second electrodes A step of selectively etching the material film and the second insulating film to form a memory cell gate electrode; and using the memory cell gate electrode as a mask to selectively introduce impurities into the substrate surface, Forming a source / drain region, forming a pattern of a first interlayer insulating film in the memory cell region, and removing the second electrode material film and the second insulating film in the peripheral transistor region. Forming a third insulating film in the peripheral transistor region, forming a third electrode material film in the peripheral transistor region and patterning it to form a peripheral gate electrode, Method of manufacturing a nonvolatile semiconductor memory device characterized by a step of forming the source and drain regions of the side transistor region. 2. The step of forming the source / drain regions of the peripheral transistor region forms the low-concentration source / drain regions by selectively introducing impurities at a low concentration into the substrate surface using the peripheral gate electrode as a mask. And a step of forming a sidewall insulating film on the sidewall of the peripheral gate electrode, and a high-concentration source by selectively introducing impurities at a high concentration into the substrate surface using the peripheral gate electrode and the sidewall insulating film as a mask. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising the step of forming a drain region.