WO2016121564A1 - Semiconductor integrated circuit device manufacturing method - Google Patents

Semiconductor integrated circuit device manufacturing method Download PDF

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Publication number
WO2016121564A1
WO2016121564A1 PCT/JP2016/051352 JP2016051352W WO2016121564A1 WO 2016121564 A1 WO2016121564 A1 WO 2016121564A1 JP 2016051352 W JP2016051352 W JP 2016051352W WO 2016121564 A1 WO2016121564 A1 WO 2016121564A1
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Prior art keywords
circuit region
logic gate
memory
layer
memory circuit
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PCT/JP2016/051352
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French (fr)
Japanese (ja)
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福夫 大和田
谷口　泰弘
泰彦 川嶋
信司 吉田
奥山　幸祐
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株式会社フローディア
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Publication of WO2016121564A1 publication Critical patent/WO2016121564A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a method for manufacturing a semiconductor integrated circuit device.
  • a semiconductor integrated circuit device besides a plurality of memory transistors arranged in a matrix, for example, a CPU (Central Processing Unit), an ASIC (Application-Specific Integrated Circuit), a sense amplifier, a column decoder, Various peripheral circuits such as a row decoder and an input / output circuit can be provided.
  • a manufacturing method of this type of semiconductor integrated circuit device a manufacturing method as shown in Patent Document 1 is known.
  • the memory gate of the memory transistor is first formed, and then the logic gate of the peripheral circuit can be manufactured.
  • FIG. 8 is a schematic diagram for explaining a manufacturing process required after the memory gate 105 and the logic gates 110 and 111 are formed in order in the conventional manufacturing method.
  • the semiconductor substrate S is provided with a memory circuit region ER1 in which a memory transistor is formed and a peripheral circuit region ER2 in which a peripheral circuit is formed, and the memory circuit region ER1 and the peripheral circuit region ER2
  • An element isolation layer IL1 is formed at the boundary, and an element isolation layer IL2 is also formed in the peripheral circuit region ER2.
  • a memory well MW is formed in the semiconductor substrate S.
  • the charge storage layer EC is already formed on the surface of the memory well MW via the memory gate insulating layer 102.
  • the upper insulating layer 104 and the memory gate 105 are sequentially stacked.
  • the memory well MW is located in a region other than the formation region in which the memory gate insulating layer 102, the charge storage layer EC, the upper insulating layer 104, and the memory gate 105 are sequentially stacked on the memory well MW.
  • a memory circuit region insulating layer 102a made of an insulating member is formed thereon. Note that an insulating film 107 is formed around the memory gate 105.
  • logic gates 110 and 111 can be formed on the logic gate insulating layers 101 and 103 in the peripheral circuit region ER2, respectively.
  • a layered logic gate formation layer (not shown) extends from the memory circuit region ER1 in which the memory gate 105 is formed to the logic gate insulating layers 101 and 103 in the peripheral circuit region ER2. 8), the logic gate formation layer is patterned with a resist (not shown) to form the logic gates 110 and 111 as shown in FIG. 8 on the logic gate insulating layers 101 and 103 in the peripheral circuit region ER2. .
  • the insulating film 107 around the memory gate 105 and the side wall-like logic gate formation layer 109 remain along the side wall of the charge storage layer EC. Therefore, as shown in FIG. 8, in the conventional manufacturing method, a resist 115 is formed so as to cover the logic gates 110 and 111 formed in the peripheral circuit region ER2, and a side wall-like logic gate forming layer remaining in the memory circuit region ER1 is formed. 109 was removed by dry etching.
  • the logic gate forming layer 109 is attached to the side wall of the insulating film 107 and the charge storage layer EC around the memory gate, the remaining logic gate is formed.
  • the amount of the layer 109 is extremely small and the remaining logic gate formation layer 109 is removed by dry etching, for example, the change in the plasma emission intensity generated by the etching of the logic gate formation layer 109 is small, and the change in the plasma emission intensity is reduced. Therefore, it is difficult to use an automatic end point detection method that determines the end of etching based on this.
  • the etching since the patterning of the logic gates 110 and 111 is generally performed by anisotropic etching, the etching only proceeds in a direction perpendicular to the semiconductor substrate S, and the logic gate forming layer 109 remains as large as the height of the memory gate 105. There was a problem to do.
  • the underlying memory circuit region insulating layer 102a must be overetched to some extent, for example, the memory circuit region When the thickness of the insulating layer 102a is thin, there is a problem that even the memory circuit region insulating layer 102a is removed and the silicon substrate may be shaved.
  • a layered resist (not shown) is formed on the antireflection film 161 formed on the logic gate forming layer 160 formed in a layered shape, and the resist is patterned using a photomask.
  • the light used for patterning the resist is not irregularly reflected by the logic gate formation layer 160 by the antireflection film 161 formed on the logic gate formation layer 160.
  • a resist having a shape corresponding to the patterning of the photomask can be formed with high accuracy.
  • resists 163 and 164 can remain only in the position where the logic gate is to be formed in the peripheral circuit region ER2.
  • the antireflection film 161 is removed by an etching amount corresponding to the film thickness of the antireflection film 161 formed on the logic gate formation layer 160 in the peripheral circuit region ER2.
  • the antireflection film 161 can remain only in the region covered with the resists 163 and 164 in the peripheral circuit region ER, as shown in FIG.
  • the antireflection film 161 in the memory circuit region ER1, since the logic gate formation layer 160 is raised according to the protruding shape of the memory gate 105, a step difference is formed. Therefore, when the antireflection film 161 is formed on the logic gate formation layer 160, The antireflection film 161 tends to accumulate around the step portion of the logic gate forming layer 160. Therefore, as shown in FIG. 9B, even if the antireflection film 161 exposed to the outside in the peripheral circuit region ER2 can be removed, the antireflection film 161 remains in the step portion of the logic gate formation layer 160 in the memory circuit region ER1. There was a case.
  • the logic gate forming layer 160 when the logic gate forming layer 160 is removed by the patterned resists 163 and 164, as shown in FIG. Although the logic gates 110 and 111 can be formed in the peripheral circuit region ER2, the logic gate forming layer 171 remains due to the antireflection film 161 remaining in the memory circuit region ER1.
  • the conventional manufacturing method has a problem that when the logic gates 163 and 164 are formed, the logic gate formation layer 171 remains in the memory circuit region ER1.
  • An object of the present invention is to propose a method of manufacturing a semiconductor integrated circuit device capable of suppressing over-etching on a layer.
  • a semiconductor integrated circuit device manufacturing method includes a memory gate structure in which a memory gate insulating layer, a charge storage layer, an upper insulating layer, and a memory gate are stacked in this order on a memory well. And a peripheral circuit region in which a logic gate is formed on a logic well through a logic gate insulating layer, and a method for manufacturing a semiconductor integrated circuit device other than the region where the memory gate structure is formed A layered logic gate forming layer extending between the memory circuit region in which a memory circuit region insulating layer is formed on the memory well and the peripheral circuit region in which the logic gate insulating layer is formed on the logic well.
  • a logic gate forming layer Forming a logic gate forming layer; and processing the logic gate forming layer in the peripheral circuit region into a memory circuit region Logic gate formation for removing the logic gate forming layer on the memory circuit region insulating layer and around the memory gate structure by removing the logic gate forming layer in the memory circuit region exposed to the outside and exposed to the outside A layer removal step, forming a peripheral circuit region processing resist patterned by exposure, the memory gate structure in the memory circuit region and the memory circuit region insulating layer, and a logic gate formation planned position in the peripheral circuit region Logic gate formation for covering the peripheral circuit region processing resist and removing the logic gate formation layer to leave the logic gate formation layer at the logic gate formation planned position in the peripheral circuit region to form the logic gate Process and peripheral circuit region processing resist Characterized in that it comprises a removal step of removed by.
  • the logic gate forming layer by leaving the logic gate forming layer as it is around the memory gate, a reactive gas generated by etching is easily generated when the logic gate forming layer is etched (removed).
  • the logic gate forming layer can be removed by using an automatic end point detection method for determining the etching amount with reference to a change in gas, and the logic gate forming layer in the memory circuit region can be more accurately removed.
  • overetching of the memory circuit region insulating layer can be suppressed when the logic gate forming layer in the memory circuit region is removed.
  • the logic gate formation layer in the memory circuit area since the logic gate formation layer in the memory circuit area has already been removed when forming the logic gate, the logic gate formation layer remains in the memory circuit area when the logic gate is formed. Can be prevented.
  • FIG. 2A is a schematic diagram showing a manufacturing process (1) of a semiconductor integrated circuit device
  • FIG. 2B is a schematic diagram showing a manufacturing process (2) of the semiconductor integrated circuit device
  • FIG. 2C is a semiconductor integrated circuit device.
  • 3A is a schematic view showing a manufacturing process (4) of the semiconductor integrated circuit device
  • FIG. 3B is a schematic view showing a manufacturing process (5) of the semiconductor integrated circuit device
  • FIG. 3C is a semiconductor integrated circuit device.
  • 4A is a schematic diagram showing a manufacturing process (7) of the semiconductor integrated circuit device
  • FIG. 4B is a schematic diagram showing a manufacturing process (8) of the semiconductor integrated circuit device
  • FIG. 4C is a semiconductor integrated circuit device. It is the schematic which shows the manufacturing process (9).
  • 5A is a schematic view showing a manufacturing process (10) of the semiconductor integrated circuit device
  • FIG. 5B is a schematic view showing a manufacturing process (11) of the semiconductor integrated circuit device
  • FIG. 5C is a semiconductor integrated circuit device. It is the schematic which shows the manufacturing process (12).
  • 6A is a schematic view showing a manufacturing process (13) of the semiconductor integrated circuit device
  • FIG. 6B is a schematic view showing a manufacturing process (14) of the semiconductor integrated circuit device
  • FIG. 6C is a semiconductor integrated circuit device. It is the schematic which shows the manufacturing process (15).
  • FIG. 7A is a schematic diagram showing a manufacturing process (16) of the semiconductor integrated circuit device
  • FIG. 7B is a schematic diagram showing a manufacturing process (17) of the semiconductor integrated circuit device. It is the schematic where it uses for description of the logic gate formation layer which remained in the memory circuit area
  • FIG. 9A is a schematic diagram showing a state of an antireflection film formed on a logic gate formation layer in a conventional manufacturing method
  • FIG. 9B shows a state when the antireflection film is patterned in the conventional manufacturing method.
  • FIG. 9C is a schematic diagram showing a state of the antireflection film and the logic gate forming layer remaining in the memory circuit region in the conventional manufacturing method.
  • reference numeral 1 denotes a semiconductor integrated circuit device manufactured by a manufacturing method according to the present invention, in which a memory circuit region is formed in which a memory transistor 2 is formed.
  • ER1 and a peripheral circuit region ER2 in which various peripheral circuits 3 and 4 such as a CPU, an ASIC, a sense amplifier, a column decoder, a row decoder, and an input / output circuit are formed.
  • the semiconductor integrated circuit device 1 is provided with the semiconductor substrate S, and the memory well MW can be formed on the semiconductor substrate S in the memory circuit region ER1.
  • a low breakdown voltage peripheral circuit region ER3 and a high breakdown voltage peripheral circuit region ER4 are formed in the peripheral circuit region ER2, and one logic well LW1 is formed on the semiconductor substrate S in the low breakdown voltage peripheral circuit region ER3.
  • another logic well LW2 is formed on the semiconductor substrate S in the high breakdown voltage peripheral circuit region ER4.
  • one source / drain region D1 and another source / drain region D2 are formed with a predetermined distance, and each source / drain region D1, D2 has a predetermined distance. Can be applied.
  • the memory well MW is provided with extension regions D1a, D2a having a lower impurity concentration than the source / drain regions D1, D2, and the extension region D1a in contact with one source / drain region D1 and the other source / drain regions D1a, D2a.
  • a memory gate structure 2a is provided on the memory well MW between the extension region D2a in contact with the drain region D2.
  • a memory gate insulating layer 6 made of an insulating member such as SiO 2 having a film thickness of 4 [nm] or less (for example, 1 to 4 [nm]) is formed, for example, silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), alumina (Al 2 O 3 ), etc., a charge storage layer EC, an upper insulating layer 9 also made of an insulating member, and a memory gate 10 made of polysilicon or the like.
  • a memory gate structure 2a that is sequentially stacked on the memory gate insulating layer 6 is provided.
  • the memory gate structure 2a has a configuration in which the charge storage layer EC is insulated from the memory well MW and the memory gate 10 by the memory gate insulating layer 6 and the upper insulating layer 9.
  • an insulating film 12 is formed around the memory gate 10, and a sidewall SW made of an insulating member is formed along the side walls of the insulating film 12 and the charge storage layer EC.
  • the surface of the memory well MW other than the formation region where the memory gate structure 2a is formed is made of an insulating member such as SiO 2 and has a film thickness of 4 nm or less (for example, 1 to 4 [nm]) of the memory circuit region insulating layer 6a is formed.
  • the memory well MW formed in the memory circuit region ER1 and the one logic well LW1 formed in the peripheral circuit region ER2 are electrically separated by one element isolation layer IL1, and further formed in the peripheral circuit region ER2.
  • the one logic well LW1 and the other logic well LW2 are also electrically isolated by another element isolation layer IL2.
  • a peripheral circuit 3 made of, for example, a low breakdown voltage MOS transistor is formed in one logic well LW1
  • a peripheral circuit made of a high breakdown voltage MOS transistor is formed in the other logic well LW2. 4 is formed.
  • a logic gate insulating layer having a film thickness of, for example, 4 nm or less is formed between the pair of source / drain regions D3 and D4 formed on the surface.
  • a logic gate structure 3a in which a logic gate 15 is formed via 7 is provided.
  • a side wall SW is formed on the side wall of the logic gate structure 3a, and a pair of extension regions D3a and D4a are formed on the surface of the logic well LW1 below each side wall SW.
  • the other logic well LW2 in the high voltage peripheral circuit region ER4 has a logic gate insulating layer 17 interposed between a pair of source / drain regions D5 and D6 formed on the surface, like the one logic well LW1. And a logic gate structure 4a in which a logic gate 18 is formed.
  • a side wall SW is formed on the side wall of the logic gate structure 4a, and a pair of extension regions D6a and D7a are formed on the surface of the logic well LW2 below each side wall SW.
  • the logic gate structure 4a provided in the other logic well LW2 is thicker than the logic gate insulating layer 7 in the logic gate structure 3a provided in one logic well LW1.
  • the insulating layer 17 (for example, thicker than the thickness of the logic gate insulating layer 7 and 13 nm or less in thickness) has a higher withstand voltage than the one logic gate structure 3a.
  • the peripheral circuit region ER2 not only the peripheral circuit 3 having a low breakdown voltage transistor structure that operates on and off at a low voltage but also a peripheral circuit 4 having a high breakdown voltage transistor structure that operates on and off at a high voltage is provided.
  • charges are injected into the charge storage layer EC of the memory transistor 2 due to the voltage difference between the memory well MW and the memory gate 10, and data is written to the memory transistor 2.
  • data can be erased from the memory transistor 2 by extracting charges from the charge storage layer EC due to a voltage difference between the memory well MW and the memory gate 10.
  • the semiconductor integrated circuit device 1 having the above configuration can be manufactured through the following manufacturing process.
  • the manufacturing method of the present invention first, as shown in FIG. 2A, after preparing a semiconductor substrate S, element isolation layers IL1 and IL2 made of an insulating member are formed by an STI (Shallow Trench Isolation) method or the like. It is formed at the boundary between the memory circuit region ER1 and the peripheral circuit region ER2 and the boundary between the low breakdown voltage peripheral circuit region ER3 and the high breakdown voltage peripheral circuit region ER4.
  • a sacrificial oxide film 21 is formed on the surface of the semiconductor substrate S by thermal oxidation or the like in order to perform impurity implantation.
  • a resist P1 patterned by photolithography using a first photomask (not shown) dedicated to the processing of the memory circuit region ER1.
  • a P-type impurity such as boron is implanted only into the memory circuit region ER1, thereby forming the memory well MW (first photomask process).
  • an N-type impurity such as arsenic can be further implanted into the surface of the memory well MW in the memory circuit region ER1 to form a channel formation region (not shown).
  • the sacrificial oxide film 21 in the memory circuit region ER1 is removed with hydrofluoric acid or the like using the resist P1 as it is.
  • the film thickness is 4 [nm] or less (for example, 1 to 4 [nm]) as shown in FIG.
  • a layered memory gate insulating layer 6 is formed in the memory circuit region ER1, and an ONO film in which a layered charge storage layer EC and an upper insulating layer 9 are sequentially stacked on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2, respectively.
  • a memory gate forming layer 23 to be the memory gate 10 (FIG. 1) is formed on the upper insulating layer 9 in the memory circuit region ER1 and the peripheral circuit region ER2 by subsequent processing.
  • the resist is patterned by a photolithography technique using a second photomask (not shown) dedicated to the processing of the memory circuit region ER1, and portions corresponding to those in FIG. 2C are given the same reference numerals as shown in FIG. 3A.
  • the patterned resist P2 is disposed on the memory gate formation layer 23 (FIG. 2C), and the memory gate formation layer 23 is patterned using the resist P2 to form the memory gate 10 (second photomask process) ).
  • an insulating film 12 made of an insulating member is formed around the memory gate 10 by a thermal oxidation method or the like, as shown in FIG.
  • the charge storage layer EC exposed to the outside other than the formation position of the memory gate 10 is removed, and the patterned memory gate 10 is removed.
  • the upper insulating layer 9 and the charge storage layer EC, which are also patterned, are formed in the lower part of the substrate.
  • the memory gate structure 2a in which the memory gate insulating layer 6, the charge storage layer EC, the upper insulating layer 9, and the memory gate 10 are stacked in this order is formed in the memory circuit region ER1.
  • a P-type impurity such as boron is implanted into the high-breakdown-voltage peripheral circuit region ER4 in the peripheral circuit region ER2, and the same reference numerals are given to portions corresponding to FIG. 4A.
  • the P-type logic well LW2 is formed only in the semiconductor substrate S in the high breakdown voltage peripheral circuit region ER4.
  • a channel formation region (not shown) is formed in the logic well LW2 in the high breakdown voltage peripheral circuit region ER4.
  • the channel formation region of the high breakdown voltage peripheral circuit region ER4 is formed by implanting a P-type impurity such as boron.
  • a P-type logic well LW1 is formed on the semiconductor substrate S in the low breakdown voltage peripheral circuit region ER3 by photolithography and ion implantation.
  • the logic well LW1 is implanted with a P-type impurity such as boron, and has an impurity concentration that matches the characteristics of the low breakdown voltage transistor.
  • a P-type impurity such as boron is further implanted into the surface of the logic well LW1 in the low breakdown voltage peripheral circuit region ER3 to form a channel formation region (not shown).
  • the resist P4 disposed in the high breakdown voltage peripheral circuit region ER4 is also removed.
  • the surface of the memory well MW is exposed in a region other than the formation region of the memory gate structure 2a, and in the low breakdown voltage peripheral circuit region ER3, the surface of the logic well LW1 is exposed, and the high breakdown voltage peripheral In the circuit region ER4, the insulating layer 22 having a predetermined film thickness remains on the surface of the logic well LW2.
  • the low breakdown voltage peripheral circuit region ER3 has a low breakdown voltage logic gate insulating layer 7 on the surface of the logic well LW1.
  • a high breakdown voltage logic gate insulating layer 17 having a thickness larger than that of the logic gate insulating layer 7 by the thickness of the insulating layer 22 can be formed.
  • the memory circuit region insulating layer 6a having the same thickness as the low-voltage logic gate insulating layer 7 having a low thickness can be formed on the surface of the memory well MW.
  • a layered logic gate forming layer 25 to be the logic gates 15 and 18 (FIG. 1) is formed on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2 by subsequent processing.
  • the memory circuit region ER1 since the logic gate forming layer 25 having a predetermined thickness is formed so as to cover the entire memory gate structure 2a, the memory circuit region ER1 swells in accordance with the convex shape of the memory gate structure 2a.
  • a logic gate forming layer 25 can be formed.
  • the memory circuit region processing resist is patterned by a photolithography technique using a third photomask dedicated to processing of the memory circuit region ER1, and the same reference numerals are given to the corresponding portions to FIG. 4B, as shown in FIG. 5A.
  • a memory circuit region processing resist P3 that covers only the logic gate formation layer 25 in the peripheral circuit region ER2 and exposes the logic gate formation layer 25 in the memory circuit region ER1 to the outside is formed on the logic gate formation layer 25.
  • the logic gate forming layer 25 in the memory circuit region ER1 exposed to the outside is removed by dry etching, and the corresponding parts in FIG. 5A are assigned the same reference numerals as shown in FIG.
  • the logic gate forming layer 25 around the memory gate structure 2a is removed to expose the memory gate structure 2a to the outside, and the logic gate forming layer 25 is left only in the peripheral circuit region ER2 (third photomask process).
  • a predetermined film is formed on the memory circuit region insulating layer 6a so as to cover the entire memory gate structure 2a. Since the logic gate forming layer 25 having a thickness is formed, when the logic gate forming layer 25 around the memory gate structure 2a is removed by dry etching, the amount of the logic gate forming layer 25 to be removed by dry etching Will increase.
  • the logic gate forming layer 25 in the memory circuit region ER1 when the logic gate forming layer 25 in the memory circuit region ER1 is removed by dry etching, the logic gate forming layer 25 formed in the peripheral circuit region ER2 is removed. Since the same layered logic gate formation layer 25 remains unprocessed, the amount of etching of the logic gate formation layer 25 in the memory circuit region ER1 also increases, and the reaction that occurs when the logic gate formation layer 25 is dry etched The change in the amount of gas generated also increases. As a result, a change in plasma emission intensity that detects a change in the amount of reaction gas generated during dry etching also increases, and a change in plasma emission intensity can be detected by an automatic end point detection method.
  • the logic gate forming layer 25 is utilized by utilizing an automatic end point detection method for determining whether or not the logic gate forming layer 25 has been etched based on a change in plasma emission intensity during dry etching. The amount of etching can be determined.
  • the plasma emission intensity is measured at the time of dry etching of the logic gate forming layer 25, and a certain amount of the logic gate forming layer 25 remains.
  • the logic gate formation layer 25 in the memory circuit region ER1 can be dry-etched in a predetermined etching time so that the logic gate formation layer 25 in the memory circuit region ER1 can be completely removed. Has been made.
  • the logic gate formation layer 25 by detecting the change in the plasma emission intensity first, even when the logic gate formation layer 25 is formed, even if there is an error in the film thickness of the logic gate formation layer 25, the logic In the process of removing the gate formation layer 25 by dry etching, it is possible to specify that the logic gate formation layer 25 has reached a predetermined amount in the memory circuit region ER1 with reference to a change in plasma emission intensity.
  • an etching time is specified in advance so that a certain amount of the remaining logic gate forming layer 25 can be removed by dry etching and the memory circuit region insulating layer 6a is not over-etched.
  • isotropic etching can be used as this etching.
  • the logic gate forming layer 25 in the memory circuit region ER1 is removed by using isotropic etching, the logic gate forming layer 25 (which can remain in a sidewall shape under the side wall of the memory gate structure 2a during the etching) In this case, since the amount of polysilicon) is reduced, the amount of over-etching for removing it can also be suppressed, and substrate scraping (scratching of the memory circuit region insulating layer 6a) can be suppressed.
  • the memory circuit region processing resist P3 formed in the peripheral circuit region ER2 as a mask, low concentration N-type impurities are implanted into the memory circuit region ER1 by an ion implantation method or the like, and both sides of the memory gate structure 2a are N-type extension regions D1a and D2a are formed on the surface of the memory well MW.
  • the memory circuit region processing resist P3 is removed by, for example, ashing.
  • an antireflection film 30 is formed in the memory circuit region ER1 and the peripheral circuit region ER2 by, for example, a coating method,
  • the gate structure 2a and the logic gate forming layer 25 in the peripheral circuit region ER2 are covered with an antireflection film 30.
  • the peripheral circuit region processing resist is patterned by a photolithography technique using a photomask, and the patterned peripheral circuit region processing resists LP1, LP2, LP3 are formed on the antireflection film 30.
  • a peripheral circuit region processing resist LP1 covering the antireflection film 30 can be formed in the memory circuit region ER1.
  • a peripheral circuit region processing resist LP2 is formed at a position where the logic gate 15 (FIG. 1) formed in the low breakdown voltage peripheral circuit region ER3 is to be formed, and is formed in the high breakdown voltage peripheral circuit region ER4.
  • a peripheral circuit region processing resist LP3 is formed at a planned formation position of the logic gate 18 (FIG. 1).
  • the antireflection film 30 is formed on the logic gate forming layer 25.
  • the light used for patterning LP1, LP2, and LP3 is not diffusely reflected by the logic gate forming layer 25, and the peripheral circuit region processing resists LP1, LP2, and LP3 having a shape corresponding to the photomask patterning can be accurately formed.
  • the antireflection film 30 that is not covered with the peripheral circuit region processing resists LP2 and LP3 in the peripheral circuit region ER2 and is exposed to the outside is removed.
  • the antireflection film 30 other than the formation position of the peripheral circuit region processing resists LP2 and LP3 is removed, and the logic gate forming layer 25 is exposed from the region where the antireflection film 30 is removed. It can be a state.
  • the logic gate forming layer 25 that is not covered with the peripheral circuit region processing resists LP1, LP2, and LP3 and is exposed to the outside by removing the antireflection film 30 is removed, and is the same as the corresponding part in FIG. 6A.
  • the logic gates 15 and 18 are formed by leaving the logic gate formation layer 25 at the logic gate formation scheduled position in the peripheral circuit region ER2.
  • the antireflection film 30 and the logic gate formation layer 25 in the peripheral circuit region ER2 are sequentially removed, the antireflection film 30 is removed only on the logic gate formation layer 25 before being removed.
  • the antireflection film 30 is removed by the thickness of the antireflection film 30 on the logic gate formation layer 25 because it is formed along the side wall of the logic gate formation layer 25 (FIG. 6A).
  • a sidewall-like antireflection film 30a is formed along the side wall of the logic gate formation layer 25 (FIG. 6B).
  • the antireflection film 30a erected in a sidewall shape can remain, the antireflection film 30a does not hinder the etching of the logic gate forming layer 25, and the peripheral circuit region processing resist
  • the logic gate forming layer 25 is left only at the positions where LP2 and LP3 are formed, and the logic gates 15 and 18 can be formed.
  • the remaining antireflection films 30, 30a are also removed, and parts corresponding to those in FIG.
  • the memory gate structure 2a disposed in the memory well MW in the memory circuit region ER1 is exposed to the outside, and the logic gates 15 and 18 disposed in the logic wells LW1 and LW2 in the peripheral circuit region ER2 are exposed to the outside.
  • a low-concentration N-type impurity or P-type impurity is implanted into the peripheral circuit region ER2 by ion implantation or the like using a resist (not shown) patterned for N-type or P-type.
  • the extension regions D3a and D4a are formed on the surface of one logic well LW1 exposed to the outside, and the other portions exposed to the outside are also shown. Extension regions D5a and D6a are formed on the surface of the logic well LW2.
  • FIG. 7B After removing the resist patterned for N-type or P-type, as shown in FIG. 7B in which parts corresponding to those in FIG. 7A are denoted by the same reference numerals, the side walls of the memory gate structure 2a, logic gates, etc. Sidewalls SW are formed on the side walls of the structures 3a and 4a.
  • a process of forming source / drain regions D1, D2, D3, D4, D5, D6 by injecting high-concentration N-type impurities or P-type impurities into the necessary portions by an ion implantation method or the like A semiconductor integrated circuit device 1 having the configuration shown in FIG. 1 can be manufactured.
  • logic gate insulation is provided on the memory circuit region ER1 in which the memory gate structure 2a is formed on the memory well MW and the logic wells LW1 and LW2.
  • a layered logic gate forming layer 25 is formed across the peripheral circuit region ER2 in which the layers 7 and 17 are formed (FIG. 4B, logic gate forming layer forming step).
  • the logic gate forming layer 25 in the peripheral circuit region ER2 is covered with the memory circuit region processing resist P3, and the logic gate forming layer 25 in the memory circuit region ER1 exposed to the outside is removed. As a result, all of the logic gate formation layer 25 on the memory well MW and around the memory gate structure 2a is removed (FIG. 5B, logic gate formation layer removal step).
  • the logic gate forming layer 25 in the memory circuit region ER1 when the logic gate forming layer 25 in the memory circuit region ER1 is removed by dry etching, the layered logic gate forming layer 25 formed in the peripheral circuit region ER2 is used as it is in the memory. Since it also remains in the circuit region ER1, the amount of etching of the logic gate forming layer 25 in the memory circuit region ER1 increases accordingly, and the amount of reaction gas generated due to the etching of the logic gate forming layer 25 also increases. Become.
  • the amount of reaction gas generated during dry etching of the logic gate formation layer 25 in the memory circuit region ER1 is large, the change in the plasma emission intensity that changes according to the reaction gas also increases. Whether or not the logic gate forming layer 25 has been etched can be determined based on the change in the plasma emission intensity during the etching.
  • the amount of etching of the logic gate forming layer 25 is more accurately performed by using an automatic end point detection method that determines whether or not the etching target has been etched based on a change in plasma emission intensity during dry etching.
  • over-etching of the memory circuit region insulating layer 6a can be suppressed when the logic gate forming layer 25 in the memory circuit region ER1 is removed.
  • the antireflection film 30 is formed over the memory circuit region ER1 and the peripheral circuit region ER2 (FIG. 6A, antireflection film formation step).
  • the peripheral circuit region processing resists LP1, LP2, LP3 patterned by exposure are formed on the antireflection film 30, and the reflection covering the memory gate structure 2a and the memory well MW in the memory circuit region ER1.
  • the anti-reflection film 30 and the anti-reflection film 30 at the position where the logic gate is to be formed in the peripheral circuit region ER2 are covered with the peripheral circuit region processing resists LP1, LP2, and LP3, and a predetermined region exposed to the outside in the peripheral circuit region ER2
  • the antireflection film 30 and the logic gate forming layer 25 are sequentially removed (FIG. 6C, logic gate forming step).
  • the logic gates 15 and 18 can be formed by leaving the logic gate formation layer 25 at the logic gate formation scheduled position in the peripheral circuit region ER2.
  • the manufacturing method of the present invention since the logic gate forming layer 25 in the memory circuit region ER1 has already been removed when forming the antireflection film 30, a part of the antireflection film 30 is patterned by patterning the antireflection film 30. Even if the film 30a remains in the memory circuit region ER1, it is possible to prevent the logic gate formation layer 25 from remaining in the memory circuit region ER1 using the antireflection film 30a as a mask. Thus, this manufacturing method can prevent the logic gate forming layer 25 from remaining in the memory circuit region ER1 when the logic gates 15 and 18 are formed.
  • the extension regions D1a and D2a are formed in the memory well MW of the memory circuit region ER1 using the memory circuit region processing resist P3 as it is as a mask (FIG. 5C, extension). Region forming step).
  • a dedicated resist forming step for forming the extension regions D1a and D2a in the memory well of the memory circuit region ER1 becomes unnecessary, and the manufacturing process can be simplified correspondingly.
  • the present invention is not limited to the present embodiment, and various modifications can be made within the scope of the present invention.
  • the number of memory transistors, The number of peripheral circuits and the like may be various numbers
  • the conductivity type of the memory well MW and the logic wells LW1 and LW2 may be either N-type or P-type.
  • the peripheral circuit region ER2 having the low breakdown voltage peripheral circuit region ER3 formed on the surface of the logic well LW1 is formed with the logic gate insulating layer 7 whose thickness is thinner than the thickness of the above-described film.
  • the peripheral circuit region ER2 having only one of the high withstand voltage peripheral circuit region ER4 and the low withstand voltage peripheral circuit region ER3 may be formed.
  • peripheral circuits 3 and 4 in the above-described embodiment in addition to various peripheral circuits (direct peripheral circuits) such as a sense amplifier, a column decoder, and a row decoder formed in the same area as the memory transistor 2, Various other peripheral circuits such as a CPU, an ASIC, and an input / output circuit formed in a different area from the memory transistor may be applied.
  • the logic wells LW1 and LW2 are formed after the memory gate 10 is formed as shown in FIGS. 4A and 4B has been described.
  • the present invention is not limited to this.
  • the logic wells LW1 and LW2 are formed in the same process as the process of forming the memory well MW before forming the memory gate 10, and then, as shown in FIG. 2C. You may move to the ONO film formation process.
  • an automatic end point detection method for measuring a change in the reaction gas generated when the logic gate formation layer is etched and determining an etching amount of the logic gate formation layer based on the change in the reaction gas.
  • the change in the plasma emission intensity generated when the logic gate formation layer 25 in the memory circuit region ER1 is etched is measured, and the etching amount of the logic gate formation layer 25 is determined based on the change in the plasma emission intensity.
  • the present invention is not limited to this, the change in the component of the reaction gas generated when the logic gate formation layer 25 in the memory circuit region ER1 is etched is measured, and the component of the reaction gas Various other automatic end point detection methods such as the automatic end point detection method that determines the etching amount of the logic gate forming layer 25 based on the change are suitable. It may be.

Abstract

The present invention proposes a semiconductor integrated circuit device manufacturing method in which by allowing a logic gate forming layer (25) provided at the periphery of a memory gate (10) to remain as is, to that extent, the generation of a reaction gas which arises due to dry etching when the logic gate forming layer (25) is dry etched becomes easier, and as a result thereof, it becomes possible to remove the logic gate forming layer (25) using an automatic stopping point detection method for determining the etching amount with changes in the reaction gas serving as a reference, and the logic gate forming layer (25) in a memory circuit region (ER1) can be removed more accurately. As a result of the foregoing, over etching of a memory circuit region insulation layer (6a) can be controlled when removing the logic gate forming layer (25) in the memory circuit region (ER1), and because the logic gate forming layer (25) in the memory circuit region (ER1) has already been removed when forming a logic gate (15, 18 (fig. 6)), it is possible to prevent an unwanted state in which the logic gate forming layer (25) remains in the memory circuit region (ER1) when forming the logic gate (15, 18).

Description

半導体集積回路装置の製造方法Manufacturing method of semiconductor integrated circuit device
　本発明は、半導体集積回路装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor integrated circuit device.
　一般的に、半導体集積回路装置には、行列状に配置された複数のメモリトランジスタの他にも、例えばCPU（Central Processing Unit）や、ASIC（Application-Specific Integrated Circuit）、センスアンプ、カラムデコーダ、ロウデコーダ、入出力回路等の各種周辺回路が設けられ得る。ここで、この種の半導体集積回路装置の製造方法としては、特許文献1に示すような製造方法が知られている。実際上、この特許文献1に示す従来の製造方法では、先ず始めにメモリトランジスタのメモリゲートを形成し、その後、周辺回路のロジックゲートを製造し得るようになされている。 Generally, in a semiconductor integrated circuit device, besides a plurality of memory transistors arranged in a matrix, for example, a CPU (Central Processing Unit), an ASIC (Application-Specific Integrated Circuit), a sense amplifier, a column decoder, Various peripheral circuits such as a row decoder and an input / output circuit can be provided. Here, as a manufacturing method of this type of semiconductor integrated circuit device, a manufacturing method as shown in Patent Document 1 is known. Actually, in the conventional manufacturing method shown in Patent Document 1, the memory gate of the memory transistor is first formed, and then the logic gate of the peripheral circuit can be manufactured.
特開2007-227585号公報JP 2007-227585 JP
　ここで、図８は、従来の製造方法においてメモリゲート105およびロジックゲート110,111を順に形成したとき、その後、必要となる製造工程の説明に供する概略図である。この場合、半導体基板Sには、メモリトランジスタが形成されるメモリ回路領域ER1と、周辺回路が形成される周辺回路領域ER2とが設けられており、当該メモリ回路領域ER1と周辺回路領域ER2との境界に素子分離層IL1が形成され、周辺回路領域ER2にも素子分離層IL2が形成されている。 Here, FIG. 8 is a schematic diagram for explaining a manufacturing process required after the memory gate 105 and the logic gates 110 and 111 are formed in order in the conventional manufacturing method. In this case, the semiconductor substrate S is provided with a memory circuit region ER1 in which a memory transistor is formed and a peripheral circuit region ER2 in which a peripheral circuit is formed, and the memory circuit region ER1 and the peripheral circuit region ER2 An element isolation layer IL1 is formed at the boundary, and an element isolation layer IL2 is also formed in the peripheral circuit region ER2.
　また、メモリ回路領域ER1には、半導体基板SにメモリウエルMWが形成されており、この製造工程の段階にて、既に当該メモリウエルMWの表面にメモリゲート絶縁層102を介して電荷蓄積層EC、上部絶縁層104、およびメモリゲート105が順に積層形成されている。さらに、この製造工程の段階では、メモリゲート絶縁層102、電荷蓄積層EC、上部絶縁層104、およびメモリゲート105がメモリウエルMW上に順に積層形成された形成領域以外の領域にあるメモリウエルMW上に、絶縁部材でなるメモリ回路領域絶縁層102aが形成されている。なお、メモリゲート105には、その周辺に絶縁膜107が形成されている。 Further, in the memory circuit region ER1, a memory well MW is formed in the semiconductor substrate S. At the stage of this manufacturing process, the charge storage layer EC is already formed on the surface of the memory well MW via the memory gate insulating layer 102. The upper insulating layer 104 and the memory gate 105 are sequentially stacked. Further, at the stage of this manufacturing process, the memory well MW is located in a region other than the formation region in which the memory gate insulating layer 102, the charge storage layer EC, the upper insulating layer 104, and the memory gate 105 are sequentially stacked on the memory well MW. A memory circuit region insulating layer 102a made of an insulating member is formed thereon. Note that an insulating film 107 is formed around the memory gate 105.
　そして、従来の製造方法では、このようなメモリゲート105が形成された後、周辺回路領域ER2のロジックゲート絶縁層101,103上にそれぞれロジックゲート110,111が形成され得る。ロジックゲート110,111を形成する際には、先ず始めに、メモリゲート105が形成されたメモリ回路領域ER1から、周辺回路領域ER2のロジックゲート絶縁層101,103上に亘って層状のロジックゲート形成層（図示せず）が形成された後、当該ロジックゲート形成層をレジスト（図示せず）によってパターニングすることにより、図８に示すようなロジックゲート110,111を周辺回路領域ER2のロジックゲート絶縁層101,103上に形成する。 In the conventional manufacturing method, after such a memory gate 105 is formed, logic gates 110 and 111 can be formed on the logic gate insulating layers 101 and 103 in the peripheral circuit region ER2, respectively. When forming the logic gates 110 and 111, first, a layered logic gate formation layer (not shown) extends from the memory circuit region ER1 in which the memory gate 105 is formed to the logic gate insulating layers 101 and 103 in the peripheral circuit region ER2. 8), the logic gate formation layer is patterned with a resist (not shown) to form the logic gates 110 and 111 as shown in FIG. 8 on the logic gate insulating layers 101 and 103 in the peripheral circuit region ER2. .
　この際、メモリ回路領域ER1には、メモリゲート105周辺の絶縁膜107や電荷蓄積層ECの側壁に沿ってサイドウォール状のロジックゲート形成層109が残存してしまう。そのため、図８に示すように、従来の製造方法では、周辺回路領域ER2に形成したロジックゲート110,111を覆うようにレジスト115を形成し、メモリ回路領域ER1に残存したサイドウォール状のロジックゲート形成層109をドライエッチングによって除去していた。 At this time, in the memory circuit region ER1, the insulating film 107 around the memory gate 105 and the side wall-like logic gate formation layer 109 remain along the side wall of the charge storage layer EC. Therefore, as shown in FIG. 8, in the conventional manufacturing method, a resist 115 is formed so as to cover the logic gates 110 and 111 formed in the peripheral circuit region ER2, and a side wall-like logic gate forming layer remaining in the memory circuit region ER1 is formed. 109 was removed by dry etching.
　しかしながら、このような従来の製造方法では、メモリゲート周辺の絶縁膜107や電荷蓄積層ECの側壁にロジックゲート形成層109がサイドウォール状に付着していることから、残存しているロジックゲート形成層109の量が極めて少なく、残存したロジックゲート形成層109をドライエッチングにより除去する際、例えば、ロジックゲート形成層109のエッチングにより発生するプラズマ発光強度の変化も小さく、当該プラズマ発光強度の変化を基にエッチングの終了を判断する自動終点検出法を利用することが困難であった。またロジックゲート110,111のパターニングは一般的に異方性エッチングで行われるため、エッチングが半導体基板Sに対し垂直方向にしか進まず、ロジックゲート形成層109がメモリゲート105の高さと同じ程度に大きく残存するという問題があった。 However, in such a conventional manufacturing method, since the logic gate forming layer 109 is attached to the side wall of the insulating film 107 and the charge storage layer EC around the memory gate, the remaining logic gate is formed. When the amount of the layer 109 is extremely small and the remaining logic gate formation layer 109 is removed by dry etching, for example, the change in the plasma emission intensity generated by the etching of the logic gate formation layer 109 is small, and the change in the plasma emission intensity is reduced. Therefore, it is difficult to use an automatic end point detection method that determines the end of etching based on this. In addition, since the patterning of the logic gates 110 and 111 is generally performed by anisotropic etching, the etching only proceeds in a direction perpendicular to the semiconductor substrate S, and the logic gate forming layer 109 remains as large as the height of the memory gate 105. There was a problem to do.
　そのため、サイドウォール状に残存した微小量のロジックゲート形成層109をドライエッチングにより除去する際には、下地となるメモリ回路領域絶縁層102aを、ある程度オーバーエッチングせざるを得ず、例えばメモリ回路領域絶縁層102aの膜厚が薄い場合には、当該メモリ回路領域絶縁層102aまでも除去してしまいシリコン基板が削れる恐れがあるという問題があった。 Therefore, when the minute amount of logic gate forming layer 109 remaining in the sidewall shape is removed by dry etching, the underlying memory circuit region insulating layer 102a must be overetched to some extent, for example, the memory circuit region When the thickness of the insulating layer 102a is thin, there is a problem that even the memory circuit region insulating layer 102a is removed and the silicon substrate may be shaved.
　また、従来の製造方法では、メモリ回路領域ER1にメモリゲート105を形成した後、周辺回路領域ER2にロジックゲート110,111を形成する際、図８との対応部分に同一符号を付して示す図９Ａのように、メモリゲート105が形成されたメモリ回路領域ER1のメモリ回路領域絶縁層102aから、周辺回路領域のロジックゲート絶縁層101,103に亘って層状のロジックゲート形成層160を形成した後、塗布法によって当該ロジックゲート形成層160の表面に層状の反射防止膜（Bottom Anti‐Reflective Coating：BARC）161を形成する。 Further, in the conventional manufacturing method, when the logic gates 110 and 111 are formed in the peripheral circuit region ER2 after the memory gate 105 is formed in the memory circuit region ER1, FIG. Thus, after forming the logic gate forming layer 160 in a layer form from the memory circuit region insulating layer 102a in the memory circuit region ER1 in which the memory gate 105 is formed to the logic gate insulating layers 101 and 103 in the peripheral circuit region, a coating method is performed. Thus, a layered antireflection film (BottomBotAnti-Reflective Coating: BARC) 161 is formed on the surface of the logic gate forming layer 160.
　次いで、従来の製造方法では、層状に形成されたロジックゲート形成層160上に形成された反射防止膜161上に層状のレジスト（図示せず）を形成し、フォトマスクを用いて当該レジストをパターニングする。ここで、フォトマスクを用いてレジストをパターニングする際には、ロジックゲート形成層160上に形成した反射防止膜161によって、レジストをパターニングする際に用いる光がロジックゲート形成層160で乱反射されず、フォトマスクのパターニングに対応した形状のレジストを精度良く形成し得る。 Next, in the conventional manufacturing method, a layered resist (not shown) is formed on the antireflection film 161 formed on the logic gate forming layer 160 formed in a layered shape, and the resist is patterned using a photomask. To do. Here, when patterning a resist using a photomask, the light used for patterning the resist is not irregularly reflected by the logic gate formation layer 160 by the antireflection film 161 formed on the logic gate formation layer 160. A resist having a shape corresponding to the patterning of the photomask can be formed with high accuracy.
　これにより、図９Ａに示すように、周辺回路領域ER2には、ロジックゲートの形成予定位置にのみレジスト163,164が残存し得る。次いで、周辺回路領域ER2のロジックゲート形成層160上に形成された反射防止膜161の膜厚分のエッチング量で反射防止膜161を除去する。これにより、図９Ａとの対応部分に同一符号を付して示す図９Ｂのように、周辺回路領域ERには、レジスト163,164に覆われた領域にのみ反射防止膜161が残存し得る。 As a result, as shown in FIG. 9A, resists 163 and 164 can remain only in the position where the logic gate is to be formed in the peripheral circuit region ER2. Next, the antireflection film 161 is removed by an etching amount corresponding to the film thickness of the antireflection film 161 formed on the logic gate formation layer 160 in the peripheral circuit region ER2. As a result, the antireflection film 161 can remain only in the region covered with the resists 163 and 164 in the peripheral circuit region ER, as shown in FIG.
　ここで、メモリ回路領域ER1には、メモリゲート105の突出形状に合わせてロジックゲート形成層160が盛り上がり段差が形成されることから、反射防止膜161をロジックゲート形成層160上に形成した際に、ロジックゲート形成層160の段差部分周辺に反射防止膜161が溜まり易い。そのため、図９Ｂに示すように、周辺回路領域ER2で外部に露出した反射防止膜161を除去できても、メモリ回路領域ER1では、ロジックゲート形成層160の段差部分に反射防止膜161が残存してしまうことがあった。 Here, in the memory circuit region ER1, since the logic gate formation layer 160 is raised according to the protruding shape of the memory gate 105, a step difference is formed. Therefore, when the antireflection film 161 is formed on the logic gate formation layer 160, The antireflection film 161 tends to accumulate around the step portion of the logic gate forming layer 160. Therefore, as shown in FIG. 9B, even if the antireflection film 161 exposed to the outside in the peripheral circuit region ER2 can be removed, the antireflection film 161 remains in the step portion of the logic gate formation layer 160 in the memory circuit region ER1. There was a case.
　このような場合には、図９Ｂとの対応部分に同一符号を付して示す図９Ｃのように、パターニングされたレジスト163,164によってロジックゲート形成層160を除去した際、レジスト163,164の形状に対応したロジックゲート110,111を周辺回路領域ER2に形成し得るものの、メモリ回路領域ER1に残存してしまった反射防止膜161によってロジックゲート形成層171が残存してしまう。このように、従来の製造方法では、ロジックゲート163,164を形成した際に、メモリ回路領域ER1にもロジックゲート形成層171が残存してしまうという問題があった。 In such a case, when the logic gate forming layer 160 is removed by the patterned resists 163 and 164, as shown in FIG. Although the logic gates 110 and 111 can be formed in the peripheral circuit region ER2, the logic gate forming layer 171 remains due to the antireflection film 161 remaining in the memory circuit region ER1. Thus, the conventional manufacturing method has a problem that when the logic gates 163 and 164 are formed, the logic gate formation layer 171 remains in the memory circuit region ER1.
　そこで、本発明は以上の点を考慮してなされたもので、メモリ回路領域のロジックゲート形成層の残存を防止し得るとともに、メモリ回路領域のロジックゲート形成層をエッチングする際にメモリ回路領域絶縁層に対するオーバーエッチングを抑制し得る半導体集積回路装置の製造方法を提案することを目的とする。 Therefore, the present invention has been made in consideration of the above points, and can prevent the logic gate formation layer from remaining in the memory circuit area, and can also insulate the memory circuit area when etching the logic gate formation layer in the memory circuit area. An object of the present invention is to propose a method of manufacturing a semiconductor integrated circuit device capable of suppressing over-etching on a layer.
　かかる課題を解決するため本発明の半導体集積回路装置の製造方法は、メモリゲート絶縁層、電荷蓄積層、上部絶縁層、およびメモリゲートの順で積層されたメモリゲート構造体がメモリウエル上に形成されるメモリ回路領域と、ロジックゲート絶縁層を介してロジックゲートがロジックウエル上に形成される周辺回路領域とを備える半導体集積回路装置の製造方法であって、前記メモリゲート構造体の形成領域以外の前記メモリウエル上にメモリ回路領域絶縁層が形成された前記メモリ回路領域と、前記ロジックウエル上に前記ロジックゲート絶縁層が形成された前記周辺回路領域とに亘って層状のロジックゲート形成層を形成するロジックゲート形成層形成工程と、前記周辺回路領域の前記ロジックゲート形成層をメモリ回路領域加工レジストにより覆い、外部に露出した前記メモリ回路領域の前記ロジックゲート形成層を除去することにより、前記メモリ回路領域絶縁層上および前記メモリゲート構造体周辺の前記ロジックゲート形成層を除去するロジックゲート形成層除去工程と、露光によってパターニングされた周辺回路領域加工レジストを形成し、前記メモリ回路領域の前記メモリゲート構造体および前記メモリ回路領域絶縁層と、前記周辺回路領域のロジックゲート形成予定位置とを前記周辺回路領域加工レジストで覆い、前記ロジックゲート形成層を除去することにより、前記周辺回路領域の前記ロジックゲート形成予定位置に前記ロジックゲート形成層を残存させて前記ロジックゲートを形成するロジックゲート形成工程と、前記周辺回路領域加工レジストを除去する除去工程とを備えることを特徴とする。 In order to solve this problem, a semiconductor integrated circuit device manufacturing method according to the present invention includes a memory gate structure in which a memory gate insulating layer, a charge storage layer, an upper insulating layer, and a memory gate are stacked in this order on a memory well. And a peripheral circuit region in which a logic gate is formed on a logic well through a logic gate insulating layer, and a method for manufacturing a semiconductor integrated circuit device other than the region where the memory gate structure is formed A layered logic gate forming layer extending between the memory circuit region in which a memory circuit region insulating layer is formed on the memory well and the peripheral circuit region in which the logic gate insulating layer is formed on the logic well. Forming a logic gate forming layer; and processing the logic gate forming layer in the peripheral circuit region into a memory circuit region Logic gate formation for removing the logic gate forming layer on the memory circuit region insulating layer and around the memory gate structure by removing the logic gate forming layer in the memory circuit region exposed to the outside and exposed to the outside A layer removal step, forming a peripheral circuit region processing resist patterned by exposure, the memory gate structure in the memory circuit region and the memory circuit region insulating layer, and a logic gate formation planned position in the peripheral circuit region Logic gate formation for covering the peripheral circuit region processing resist and removing the logic gate formation layer to leave the logic gate formation layer at the logic gate formation planned position in the peripheral circuit region to form the logic gate Process and peripheral circuit region processing resist Characterized in that it comprises a removal step of removed by.
　本発明によれば、メモリゲートの周辺にロジックゲート形成層をそのまま残存させることにより、その分、ロジックゲート形成層をエッチング（除去）した際にエッチングにより生じる反応ガスが発生し易くなるので、反応ガスの変化を目安としてエッチング量を判定する自動終点検出法を利用してロジックゲート形成層を除去できるようになり、より正確にメモリ回路領域のロジックゲート形成層を除去し得る。かくして、メモリ回路領域のロジックゲート形成層を除去する際にメモリ回路領域絶縁層に対するオーバーエッチングを抑制し得る。 According to the present invention, by leaving the logic gate forming layer as it is around the memory gate, a reactive gas generated by etching is easily generated when the logic gate forming layer is etched (removed). The logic gate forming layer can be removed by using an automatic end point detection method for determining the etching amount with reference to a change in gas, and the logic gate forming layer in the memory circuit region can be more accurately removed. Thus, overetching of the memory circuit region insulating layer can be suppressed when the logic gate forming layer in the memory circuit region is removed.
　また、本発明によれば、ロジックゲートを形成する際にメモリ回路領域のロジックゲート形成層が既に除去されていることから、当該ロジックゲートを形成した際にメモリ回路領域にロジックゲート形成層が残存してしまうことを防止できる。 Further, according to the present invention, since the logic gate formation layer in the memory circuit area has already been removed when forming the logic gate, the logic gate formation layer remains in the memory circuit area when the logic gate is formed. Can be prevented.
本発明による製造方法によって製造された半導体集積回路装置の断面構成を示す概略図である。It is the schematic which shows the cross-sectional structure of the semiconductor integrated circuit device manufactured by the manufacturing method by this invention. 図２Ａは、半導体集積回路装置の製造工程（1）を示す概略図であり、図２Ｂは、半導体集積回路装置の製造工程（2）を示す概略図であり、図２Ｃは、半導体集積回路装置の製造工程（3）を示す概略図である。2A is a schematic diagram showing a manufacturing process (1) of a semiconductor integrated circuit device, FIG. 2B is a schematic diagram showing a manufacturing process (2) of the semiconductor integrated circuit device, and FIG. 2C is a semiconductor integrated circuit device. It is the schematic which shows the manufacturing process (3). 図３Ａは、半導体集積回路装置の製造工程（4）を示す概略図であり、図３Ｂは、半導体集積回路装置の製造工程（5）を示す概略図であり、図３Ｃは、半導体集積回路装置の製造工程（6）を示す概略図である。3A is a schematic view showing a manufacturing process (4) of the semiconductor integrated circuit device, FIG. 3B is a schematic view showing a manufacturing process (5) of the semiconductor integrated circuit device, and FIG. 3C is a semiconductor integrated circuit device. It is the schematic which shows the manufacturing process (6). 図４Ａは、半導体集積回路装置の製造工程（7）を示す概略図であり、図４Ｂは、半導体集積回路装置の製造工程（8）を示す概略図であり、図４Ｃは、半導体集積回路装置の製造工程（9）を示す概略図である。4A is a schematic diagram showing a manufacturing process (7) of the semiconductor integrated circuit device, FIG. 4B is a schematic diagram showing a manufacturing process (8) of the semiconductor integrated circuit device, and FIG. 4C is a semiconductor integrated circuit device. It is the schematic which shows the manufacturing process (9). 図５Ａは、半導体集積回路装置の製造工程（10）を示す概略図であり、図５Ｂは、半導体集積回路装置の製造工程（11）を示す概略図であり、図５Ｃは、半導体集積回路装置の製造工程（12）を示す概略図である。5A is a schematic view showing a manufacturing process (10) of the semiconductor integrated circuit device, FIG. 5B is a schematic view showing a manufacturing process (11) of the semiconductor integrated circuit device, and FIG. 5C is a semiconductor integrated circuit device. It is the schematic which shows the manufacturing process (12). 図６Ａは、半導体集積回路装置の製造工程（13）を示す概略図であり、図６Ｂは、半導体集積回路装置の製造工程（14）を示す概略図であり、図６Ｃは、半導体集積回路装置の製造工程（15）を示す概略図である。6A is a schematic view showing a manufacturing process (13) of the semiconductor integrated circuit device, FIG. 6B is a schematic view showing a manufacturing process (14) of the semiconductor integrated circuit device, and FIG. 6C is a semiconductor integrated circuit device. It is the schematic which shows the manufacturing process (15). 図７Ａは、半導体集積回路装置の製造工程（16）を示す概略図であり、図７Ｂは、半導体集積回路装置の製造工程（17）を示す概略図である。FIG. 7A is a schematic diagram showing a manufacturing process (16) of the semiconductor integrated circuit device, and FIG. 7B is a schematic diagram showing a manufacturing process (17) of the semiconductor integrated circuit device. 従来の製造方法においてメモリ回路領域に残存したロジックゲート形成層の説明に供する概略図である。It is the schematic where it uses for description of the logic gate formation layer which remained in the memory circuit area | region in the conventional manufacturing method. 図９Ａは、従来の製造方法においてロジックゲート形成層上に形成された反射防止膜の様子を示す概略図であり、図９Ｂは、従来の製造方法において反射防止膜をパターニングしたときの様子を示す概略図であり、図９Ｃは、従来の製造方法においてメモリ回路領域に残存した反射防止膜およびロジックゲート形成層の様子を示す概略図である。FIG. 9A is a schematic diagram showing a state of an antireflection film formed on a logic gate formation layer in a conventional manufacturing method, and FIG. 9B shows a state when the antireflection film is patterned in the conventional manufacturing method. FIG. 9C is a schematic diagram showing a state of the antireflection film and the logic gate forming layer remaining in the memory circuit region in the conventional manufacturing method.
　以下、本発明を実施するための形態について説明する。なお、説明は以下に示す順序とする。
１．本発明による製造方法により製造された半導体集積回路装置の構成
２．半導体集積回路装置の製造方法
３．作用および効果
４．他の実施の形態 Hereinafter, modes for carrying out the present invention will be described. The description will be in the following order.
1. 1. Configuration of a semiconductor integrated circuit device manufactured by a manufacturing method according to the present invention 2. Manufacturing method of semiconductor integrated circuit device 3. Action and effect Other embodiments
　（１）本発明による製造方法により製造された半導体集積回路装置の構成
　図１において、1は本発明の製造方法によって製造された半導体集積回路装置を示し、メモリトランジスタ2が形成されるメモリ回路領域ER1と、例えばCPUや、ASIC、センスアンプ、カラムデコーダ、ロウデコーダ、入出力回路等の各種周辺回路3,4が形成される周辺回路領域ER2とを有している。 (1) Configuration of a semiconductor integrated circuit device manufactured by a manufacturing method according to the present invention In FIG. 1, reference numeral 1 denotes a semiconductor integrated circuit device manufactured by a manufacturing method according to the present invention, in which a memory circuit region is formed in which a memory transistor 2 is formed. ER1 and a peripheral circuit region ER2 in which various peripheral circuits 3 and 4 such as a CPU, an ASIC, a sense amplifier, a column decoder, a row decoder, and an input / output circuit are formed.
　この場合、半導体集積回路装置1には、半導体基板Sが設けられており、メモリ回路領域ER1の半導体基板S上にメモリウエルMWが形成され得る。一方、周辺回路領域ER2には、例えば低耐圧周辺回路領域ER3と高耐圧周辺回路領域ER4とが形成されており、低耐圧周辺回路領域ER3にある半導体基板S上に一のロジックウエルLW1が形成され、高耐圧周辺回路領域ER4にある半導体基板S上に他のロジックウエルLW2が形成されている。ここで、メモリウエルMWの表面には、一のソース・ドレイン領域D1と、他のソース・ドレイン領域D2とが所定距離を空けて形成されており、各ソース・ドレイン領域D1,D2にそれぞれ所定の電圧が印加され得る。 In this case, the semiconductor integrated circuit device 1 is provided with the semiconductor substrate S, and the memory well MW can be formed on the semiconductor substrate S in the memory circuit region ER1. On the other hand, for example, a low breakdown voltage peripheral circuit region ER3 and a high breakdown voltage peripheral circuit region ER4 are formed in the peripheral circuit region ER2, and one logic well LW1 is formed on the semiconductor substrate S in the low breakdown voltage peripheral circuit region ER3. Then, another logic well LW2 is formed on the semiconductor substrate S in the high breakdown voltage peripheral circuit region ER4. Here, on the surface of the memory well MW, one source / drain region D1 and another source / drain region D2 are formed with a predetermined distance, and each source / drain region D1, D2 has a predetermined distance. Can be applied.
　また、メモリウエルMWには、ソース・ドレイン領域D1,D2よりも不純物濃度が低いエクステンション領域D1a,D2aが設けられており、一のソース・ドレイン領域D1に接するエクステンション領域D1aと、他のソース・ドレイン領域D2に接するエクステンション領域D2aとの間のメモリウエルMW上に、メモリゲート構造体2aが設けられている。 The memory well MW is provided with extension regions D1a, D2a having a lower impurity concentration than the source / drain regions D1, D2, and the extension region D1a in contact with one source / drain region D1 and the other source / drain regions D1a, D2a. A memory gate structure 2a is provided on the memory well MW between the extension region D2a in contact with the drain region D2.
　メモリウエルMWの表面には、膜厚が4［nm］以下（例えば1～4［nm］）のSiO2等の絶縁部材でなるメモリゲート絶縁層6が形成されており、例えば窒化シリコン（Si3N4）や、酸窒化シリコン(SiON)、アルミナ(Al2O3)等でなる電荷蓄積層ECと、同じく絶縁部材でなる上部絶縁層9と、ポリシリコン等でなるメモリゲート10とがメモリゲート絶縁層6上に順に積層形成されたメモリゲート構造体2aが設けられている。 On the surface of the memory well MW, a memory gate insulating layer 6 made of an insulating member such as SiO 2 having a film thickness of 4 [nm] or less (for example, 1 to 4 [nm]) is formed, for example, silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), alumina (Al 2 O 3 ), etc., a charge storage layer EC, an upper insulating layer 9 also made of an insulating member, and a memory gate 10 made of polysilicon or the like. A memory gate structure 2a that is sequentially stacked on the memory gate insulating layer 6 is provided.
　これによりメモリゲート構造体2aは、メモリゲート絶縁層6および上部絶縁層9によって、電荷蓄積層ECがメモリウエルMWおよびメモリゲート10から絶縁された構成を有する。なお、メモリゲート構造体2aには、メモリゲート10周辺に絶縁膜12が形成されており、当該絶縁膜12および電荷蓄積層ECの側壁に沿って絶縁部材でなるサイドウォールSWが形成されている。また、メモリ回路領域ER1には、メモリゲート構造体2aが形成された形成領域以外のメモリウエルMW表面に、SiO2等の絶縁部材でなり、かつ膜厚が4［nm］以下（例えば1～4［nm］）のメモリ回路領域絶縁層6aが形成されている。 Thus, the memory gate structure 2a has a configuration in which the charge storage layer EC is insulated from the memory well MW and the memory gate 10 by the memory gate insulating layer 6 and the upper insulating layer 9. In the memory gate structure 2a, an insulating film 12 is formed around the memory gate 10, and a sidewall SW made of an insulating member is formed along the side walls of the insulating film 12 and the charge storage layer EC. . In the memory circuit region ER1, the surface of the memory well MW other than the formation region where the memory gate structure 2a is formed is made of an insulating member such as SiO 2 and has a film thickness of 4 nm or less (for example, 1 to 4 [nm]) of the memory circuit region insulating layer 6a is formed.
　メモリ回路領域ER1に形成されたメモリウエルMWと、周辺回路領域ER2に形成された一のロジックウエルLW1は、一の素子分離層IL1によって電気的に分離されており、さらに周辺回路領域ER2に形成された一のロジックウエルLW1と、他のロジックウエルLW2も他の素子分離層IL2によって電気的に分離されている。ここで、この実施の形態の場合、一のロジックウエルLW1には、例えば低耐圧のMOSトランジスタでなる周辺回路3が形成され、他のロジックウエルLW2には、高耐圧のMOSトランジスタでなる周辺回路4が形成されている。 The memory well MW formed in the memory circuit region ER1 and the one logic well LW1 formed in the peripheral circuit region ER2 are electrically separated by one element isolation layer IL1, and further formed in the peripheral circuit region ER2. The one logic well LW1 and the other logic well LW2 are also electrically isolated by another element isolation layer IL2. In this embodiment, a peripheral circuit 3 made of, for example, a low breakdown voltage MOS transistor is formed in one logic well LW1, and a peripheral circuit made of a high breakdown voltage MOS transistor is formed in the other logic well LW2. 4 is formed.
　実際上、低耐圧周辺回路領域ER3にある一のロジックウエルLW1には、表面に形成された対のソース・ドレイン領域D3,D4間に、例えば膜厚が4［nm］以下のロジックゲート絶縁層7を介してロジックゲート15が形成されたロジックゲート構造体3aが設けられている。なお、ロジックゲート構造体3aの側壁には、サイドウォールSWが形成されており、各サイドウォールSW下部のロジックウエルLW1表面に対のエクステンション領域D3a,D4aが形成されている。 Actually, in one logic well LW1 in the low breakdown voltage peripheral circuit region ER3, a logic gate insulating layer having a film thickness of, for example, 4 nm or less is formed between the pair of source / drain regions D3 and D4 formed on the surface. A logic gate structure 3a in which a logic gate 15 is formed via 7 is provided. A side wall SW is formed on the side wall of the logic gate structure 3a, and a pair of extension regions D3a and D4a are formed on the surface of the logic well LW1 below each side wall SW.
　また、高耐圧周辺回路領域ER4にある他のロジックウエルLW2は、一のロジックウエルLW1と同様に、表面に形成された対のソース・ドレイン領域D5,D6間に、ロジックゲート絶縁層17を介してロジックゲート18が形成されたロジックゲート構造体4aを有する。なお、ロジックゲート構造体4aの側壁には、サイドウォールSWが形成されており、各サイドウォールSW下部のロジックウエルLW2表面に対のエクステンション領域D6a,D7aが形成されている。 The other logic well LW2 in the high voltage peripheral circuit region ER4 has a logic gate insulating layer 17 interposed between a pair of source / drain regions D5 and D6 formed on the surface, like the one logic well LW1. And a logic gate structure 4a in which a logic gate 18 is formed. A side wall SW is formed on the side wall of the logic gate structure 4a, and a pair of extension regions D6a and D7a are formed on the surface of the logic well LW2 below each side wall SW.
　この場合、他のロジックウエルLW2に設けられたロジックゲート構造体4aは、一のロジックウエルLW1に設けられたロジックゲート構造体3aにおけるロジックゲート絶縁層7の膜厚よりも膜厚が厚いロジックゲート絶縁層17（例えば、ロジックゲート絶縁層7の膜厚より厚く、13［nm］以下の膜厚）を有しており、一のロジックゲート構造体3aよりも耐圧性が向上されている。このように周辺回路領域ER2には、低電圧でオンオフ動作する低耐圧トランジスタ構造の周辺回路3だけでなく、高電圧でオンオフ動作する高耐圧トランジスタ構造の周辺回路4も設けられている。 In this case, the logic gate structure 4a provided in the other logic well LW2 is thicker than the logic gate insulating layer 7 in the logic gate structure 3a provided in one logic well LW1. The insulating layer 17 (for example, thicker than the thickness of the logic gate insulating layer 7 and 13 nm or less in thickness) has a higher withstand voltage than the one logic gate structure 3a. As described above, in the peripheral circuit region ER2, not only the peripheral circuit 3 having a low breakdown voltage transistor structure that operates on and off at a low voltage but also a peripheral circuit 4 having a high breakdown voltage transistor structure that operates on and off at a high voltage is provided.
　このような構成を有した半導体集積回路装置1は、メモリウエルMWおよびメモリゲート10の電圧差によって、例えばメモリトランジスタ2の電荷蓄積層ECに電荷が注入され、当該メモリトランジスタ2にデータを書き込むことできるとともに、メモリウエルMWおよびメモリゲート10の電圧差によって、当該電荷蓄積層ECから電荷が引き抜かれることにより、当該メモリトランジスタ2からデータを消去し得る。 In the semiconductor integrated circuit device 1 having such a configuration, for example, charges are injected into the charge storage layer EC of the memory transistor 2 due to the voltage difference between the memory well MW and the memory gate 10, and data is written to the memory transistor 2. In addition, data can be erased from the memory transistor 2 by extracting charges from the charge storage layer EC due to a voltage difference between the memory well MW and the memory gate 10.
　（２）半導体集積回路装置の製造方法
　以上のような構成を有する半導体集積回路装置1は、下記の製造工程を経て製造できる。この場合、本発明の製造方法では、先ず始めに、図２Ａに示すように、半導体基板Sを用意した後、STI（Shallow Trench Isolation）法等により絶縁部材からなる素子分離層IL1,IL2を、メモリ回路領域ER1および周辺回路領域ER2の境界と、低耐圧周辺回路領域ER3および高耐圧周辺回路領域ER4の境界とに形成する。次いで、不純物注入を行うために、熱酸化法等によって半導体基板Sの表面に犠牲酸化膜21を形成する。 (2) Manufacturing Method of Semiconductor Integrated Circuit Device The semiconductor integrated circuit device 1 having the above configuration can be manufactured through the following manufacturing process. In this case, in the manufacturing method of the present invention, first, as shown in FIG. 2A, after preparing a semiconductor substrate S, element isolation layers IL1 and IL2 made of an insulating member are formed by an STI (Shallow Trench Isolation) method or the like. It is formed at the boundary between the memory circuit region ER1 and the peripheral circuit region ER2 and the boundary between the low breakdown voltage peripheral circuit region ER3 and the high breakdown voltage peripheral circuit region ER4. Next, a sacrificial oxide film 21 is formed on the surface of the semiconductor substrate S by thermal oxidation or the like in order to perform impurity implantation.
　次いで、図２Ａとの対応部分に同一符号を付して示す図２Ｂのように、メモリ回路領域ER1の加工専用の第1フォトマスク（図示せず）用いたフォトリソグラフィ技術によってパターニングされたレジストP1により、メモリ回路領域ER1にのみ例えばボロン等のP型不純物を注入して、メモリウエルMWを形成する（第1フォトマスク工程）。また、このメモリ回路領域ER1のメモリウエルMWの表面には、さらに砒素等のN型不純物が注入されてチャネル形成領域（図示せず）が形成され得る。次いで、このレジストP1をそのまま用いて、メモリ回路領域ER1の犠牲酸化膜21をフッ酸等により除去する。 Next, as shown in FIG. 2B in which the same reference numerals are assigned to the corresponding parts as in FIG. 2A, a resist P1 patterned by photolithography using a first photomask (not shown) dedicated to the processing of the memory circuit region ER1. Thus, a P-type impurity such as boron is implanted only into the memory circuit region ER1, thereby forming the memory well MW (first photomask process). Further, an N-type impurity such as arsenic can be further implanted into the surface of the memory well MW in the memory circuit region ER1 to form a channel formation region (not shown). Next, the sacrificial oxide film 21 in the memory circuit region ER1 is removed with hydrofluoric acid or the like using the resist P1 as it is.
　次いで、例えばアッシング等によりレジストP1を除去した後、図２Ｂとの対応部分に同一符号を付して示す図２Ｃのように、膜厚が4［nm］以下（例えば1～4［nm］）層状のメモリゲート絶縁層6をメモリ回路領域ER1に形成し、さらに、メモリ回路領域ER1および周辺回路領域ER2の全面にそれぞれ層状の電荷蓄積層ECおよび上部絶縁層9を順に積層させたONO膜を形成する。そして、後の加工によってメモリゲート10（図１）となるメモリゲート形成層23を、メモリ回路領域ER1および周辺回路領域ER2の上部絶縁層9上に形成する。 Next, after removing the resist P1 by, for example, ashing or the like, the film thickness is 4 [nm] or less (for example, 1 to 4 [nm]) as shown in FIG. A layered memory gate insulating layer 6 is formed in the memory circuit region ER1, and an ONO film in which a layered charge storage layer EC and an upper insulating layer 9 are sequentially stacked on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2, respectively. Form. Then, a memory gate forming layer 23 to be the memory gate 10 (FIG. 1) is formed on the upper insulating layer 9 in the memory circuit region ER1 and the peripheral circuit region ER2 by subsequent processing.
　次いで、メモリ回路領域ER1の加工専用の第2フォトマスク（図示せず）を用いたフォトリソグラフィ技術によってレジストをパターニングし、図２Ｃとの対応部分に同一符号を付して示す図３Ａのように、パターニングされたレジストP2をメモリゲート形成層23（図２Ｃ）上に配置させ、当該レジストP2を用いてメモリゲート形成層23をパターニングすることにより、メモリゲート10を形成する（第2フォトマスク工程）。 Next, the resist is patterned by a photolithography technique using a second photomask (not shown) dedicated to the processing of the memory circuit region ER1, and portions corresponding to those in FIG. 2C are given the same reference numerals as shown in FIG. 3A. Then, the patterned resist P2 is disposed on the memory gate formation layer 23 (FIG. 2C), and the memory gate formation layer 23 is patterned using the resist P2 to form the memory gate 10 (second photomask process) ).
　次いで、例えばアッシング等によりレジストP2を除去した後、図３Ａとの対応部分に同一符号を付して示す図３Ｂのように、メモリゲート10の形成位置以外で外部に露出している上部絶縁層9を除去した後、図３Ｂとの対応部分に同一符号を付して示す図３Ｃのように、熱酸化法等によって絶縁部材でなる絶縁膜12をメモリゲート10の周辺に形成する。 Next, after removing the resist P2 by, for example, ashing or the like, the upper insulating layer exposed to the outside other than the formation position of the memory gate 10 as shown in FIG. After 9 is removed, an insulating film 12 made of an insulating member is formed around the memory gate 10 by a thermal oxidation method or the like, as shown in FIG.
　次いで、図３Ｃとの対応部分に同一符号を付して示す図４Ａのように、メモリゲート10の形成位置以外で外部に露出している電荷蓄積層ECを除去し、パターニングされたメモリゲート10の下部に、同じくパターニングされた上部絶縁層9および電荷蓄積層ECを形成する。これにより、メモリゲート絶縁層6、電荷蓄積層EC、上部絶縁層9、およびメモリゲート10の順で積層されたメモリゲート構造体2aをメモリ回路領域ER1に形成する。 Next, as shown in FIG. 4A in which parts corresponding to those in FIG. 3C are assigned the same reference numerals, the charge storage layer EC exposed to the outside other than the formation position of the memory gate 10 is removed, and the patterned memory gate 10 is removed. The upper insulating layer 9 and the charge storage layer EC, which are also patterned, are formed in the lower part of the substrate. As a result, the memory gate structure 2a in which the memory gate insulating layer 6, the charge storage layer EC, the upper insulating layer 9, and the memory gate 10 are stacked in this order is formed in the memory circuit region ER1.
　次いで、フォトリソグラフィ技術およびイオン注入法を利用して、周辺回路領域ER2のうち高耐圧周辺回路領域ER4に例えばボロン等のP型不純物を注入し、図４Ａとの対応部分に同一符号を付して示す図４Ｂのように、高耐圧周辺回路領域ER4の半導体基板SにのみP型でなるロジックウエルLW2を形成する。また、高耐圧周辺回路領域ER4のロジックウエルLW2にチャネル形成領域（図示せず）を形成する。高耐圧周辺回路領域ER4のチャネル形成領域は、例えばボロン等のP型不純物を注入することにより形成する。 Next, using a photolithography technique and an ion implantation method, a P-type impurity such as boron is implanted into the high-breakdown-voltage peripheral circuit region ER4 in the peripheral circuit region ER2, and the same reference numerals are given to portions corresponding to FIG. 4A. As shown in FIG. 4B, the P-type logic well LW2 is formed only in the semiconductor substrate S in the high breakdown voltage peripheral circuit region ER4. Further, a channel formation region (not shown) is formed in the logic well LW2 in the high breakdown voltage peripheral circuit region ER4. The channel formation region of the high breakdown voltage peripheral circuit region ER4 is formed by implanting a P-type impurity such as boron.
　次いで、低耐圧周辺回路領域ER3の半導体基板Sに、フォトリソグラフィ技術およびイオン注入法により、P型のロジックウエルLW1を形成する。ロジックウエルLW1は、例えばボロン等のP型不純物が注入されて、低耐圧トランジスタの特性に合わせた不純物濃度になっている。また、この低耐圧周辺回路領域ER3のロジックウエルLW1の表面にも、さらに例えばボロン等のP型不純物が注入されて、チャネル形成領域（図示せず）が形成される。 Next, a P-type logic well LW1 is formed on the semiconductor substrate S in the low breakdown voltage peripheral circuit region ER3 by photolithography and ion implantation. The logic well LW1 is implanted with a P-type impurity such as boron, and has an impurity concentration that matches the characteristics of the low breakdown voltage transistor. Further, a P-type impurity such as boron is further implanted into the surface of the logic well LW1 in the low breakdown voltage peripheral circuit region ER3 to form a channel formation region (not shown).
　次いで、メモリ回路領域ER1にてメモリゲート構造体2aの形成領域以外で外部に露出しているメモリゲート絶縁層6と、周辺回路領域ER2で残存している犠牲酸化膜21とを除去した後、例えば熱酸化法を使用して、メモリ回路領域ER1で外部に露出したメモリウエルMW表面や、周辺回路領域ER2で外部に露出したロジックウエルLW1,LW2表面にSiO2等からなる所定膜厚の絶縁層22を形成する。次いで、フォトマスク（図示せず）を用いたフォトリソグラフィ技術によってレジストをパターニングし、高耐圧周辺回路領域ER4にある絶縁層22のみを覆ったレジストP4を当該絶縁層22上に形成する。 Next, after removing the memory gate insulating layer 6 exposed outside in the memory circuit region ER1 other than the formation region of the memory gate structure 2a and the sacrificial oxide film 21 remaining in the peripheral circuit region ER2, For example, by using a thermal oxidation method, insulation of a predetermined film thickness made of SiO 2 or the like on the surface of the memory well MW exposed to the outside in the memory circuit region ER1 or the surface of the logic well LW1, LW2 exposed to the outside in the peripheral circuit region ER2 Layer 22 is formed. Next, a resist is patterned by a photolithography technique using a photomask (not shown), and a resist P4 that covers only the insulating layer 22 in the high-voltage peripheral circuit region ER4 is formed on the insulating layer 22.
　次いで、メモリ回路領域ER1および低耐圧周辺回路領域ER3にて外部に露出している絶縁層22をフッ酸等により除去した後、高耐圧周辺回路領域ER4に配置されているレジストP4も除去する。これにより、メモリ回路領域ERでは、メモリゲート構造体2aの形成領域以外の領域にメモリウエルMWの表面が露出し、低耐圧周辺回路領域ER3では、ロジックウエルLW1の表面が露出し、高耐圧周辺回路領域ER4では、所定膜厚の絶縁層22がロジックウエルLW2の表面に残存した状態となる。 Next, after the insulating layer 22 exposed to the outside in the memory circuit region ER1 and the low breakdown voltage peripheral circuit region ER3 is removed with hydrofluoric acid or the like, the resist P4 disposed in the high breakdown voltage peripheral circuit region ER4 is also removed. As a result, in the memory circuit region ER, the surface of the memory well MW is exposed in a region other than the formation region of the memory gate structure 2a, and in the low breakdown voltage peripheral circuit region ER3, the surface of the logic well LW1 is exposed, and the high breakdown voltage peripheral In the circuit region ER4, the insulating layer 22 having a predetermined film thickness remains on the surface of the logic well LW2.
　次いで、例えば熱酸化法等によって、メモリ回路領域ER1および周辺回路領域ER2の全面に絶縁層を形成する。これにより、図４Ｂとの対応部分に同一符号を付して示す図４Ｃのように、低耐圧周辺回路領域ER3には、ロジックウエルLW1表面に膜厚の薄い低耐圧用のロジックゲート絶縁層7が形成されるとともに、高耐圧周辺回路領域ER4には、絶縁層22の膜厚分だけロジックゲート絶縁層7よりも膜厚が厚い高耐圧用のロジックゲート絶縁層17が形成され得る。また、この際、メモリ回路領域ER1には、膜厚の薄い低耐圧用のロジックゲート絶縁層7と同じ膜厚のメモリ回路領域絶縁層6aが、メモリウエルMW表面に形成され得る。 Next, an insulating layer is formed on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2 by, eg, thermal oxidation. As a result, as shown in FIG. 4C in which the same reference numerals are assigned to the parts corresponding to those in FIG. 4B, the low breakdown voltage peripheral circuit region ER3 has a low breakdown voltage logic gate insulating layer 7 on the surface of the logic well LW1. In the high breakdown voltage peripheral circuit region ER4, a high breakdown voltage logic gate insulating layer 17 having a thickness larger than that of the logic gate insulating layer 7 by the thickness of the insulating layer 22 can be formed. At this time, in the memory circuit region ER1, the memory circuit region insulating layer 6a having the same thickness as the low-voltage logic gate insulating layer 7 having a low thickness can be formed on the surface of the memory well MW.
　次いで、メモリ回路領域ER1および周辺回路領域ER2の全面に、後の加工によってロジックゲート15,18（図１）となる層状のロジックゲート形成層25を形成する。この際、メモリ回路領域ER1では、メモリゲート構造体2a全体を覆うように所定の膜厚でなるロジックゲート形成層25が形成されることから、メモリゲート構造体2aの凸形状に合わせて膨らんだロジックゲート形成層25が形成され得る。 Next, a layered logic gate forming layer 25 to be the logic gates 15 and 18 (FIG. 1) is formed on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2 by subsequent processing. At this time, in the memory circuit region ER1, since the logic gate forming layer 25 having a predetermined thickness is formed so as to cover the entire memory gate structure 2a, the memory circuit region ER1 swells in accordance with the convex shape of the memory gate structure 2a. A logic gate forming layer 25 can be formed.
　次いで、メモリ回路領域ER1の加工専用の第3フォトマスクを用いたフォトリソグラフィ技術によってメモリ回路領域加工レジストをパターニングし、図４Ｂとの対応部分に同一符号を付して示す図５Ａのように、周辺回路領域ER2のロジックゲート形成層25のみを覆い、かつメモリ回路領域ER1のロジックゲート形成層25を外部に露出させたメモリ回路領域加工レジストP3をロジックゲート形成層25上に形成する。 Next, the memory circuit region processing resist is patterned by a photolithography technique using a third photomask dedicated to processing of the memory circuit region ER1, and the same reference numerals are given to the corresponding portions to FIG. 4B, as shown in FIG. 5A. A memory circuit region processing resist P3 that covers only the logic gate formation layer 25 in the peripheral circuit region ER2 and exposes the logic gate formation layer 25 in the memory circuit region ER1 to the outside is formed on the logic gate formation layer 25.
　次いで、外部に露出しているメモリ回路領域ER1のロジックゲート形成層25をドライエッチングによって除去し、図５Ａとの対応部分に同一符号を付して示す図５Ｂのように、メモリ回路領域ER1におけるメモリゲート構造体2a周辺のロジックゲート形成層25を除去してメモリゲート構造体2aを外部に露出させ、周辺回路領域ER2にのみロジックゲート形成層25を残存させる（第3フォトマスク工程）。 Next, the logic gate forming layer 25 in the memory circuit region ER1 exposed to the outside is removed by dry etching, and the corresponding parts in FIG. 5A are assigned the same reference numerals as shown in FIG. The logic gate forming layer 25 around the memory gate structure 2a is removed to expose the memory gate structure 2a to the outside, and the logic gate forming layer 25 is left only in the peripheral circuit region ER2 (third photomask process).
　ここで、本発明の製造方法では、メモリ回路領域ER1のロジックゲート形成層25をドライエッチングによって除去する前、メモリゲート構造体2a全体を覆うようにしてメモリ回路領域絶縁層6a上に所定の膜厚でなる層状のロジックゲート形成層25が形成されていることから、ドライエッチングによってメモリゲート構造体2a周辺のロジックゲート形成層25を除去する際、ドライエッチングにより除去するロジックゲート形成層25の量が多くなる。 Here, in the manufacturing method of the present invention, before removing the logic gate forming layer 25 in the memory circuit region ER1 by dry etching, a predetermined film is formed on the memory circuit region insulating layer 6a so as to cover the entire memory gate structure 2a. Since the logic gate forming layer 25 having a thickness is formed, when the logic gate forming layer 25 around the memory gate structure 2a is removed by dry etching, the amount of the logic gate forming layer 25 to be removed by dry etching Will increase.
　このように、本発明の製造方法では、図５Ａに示したように、メモリ回路領域ER1のロジックゲート形成層25をドライエッチングによって除去する際、周辺回路領域ER2に形成されたロジックゲート形成層25と同じ層状のロジックゲート形成層25が未加工のまま残っていることから、メモリ回路領域ER1におけるロジックゲート形成層25のエッチング量も多くなり、ロジックゲート形成層25をドライエッチングした際に生じる反応ガスの発生量の変化も大きくなる。その結果、ドライエッチング時に発生する反応ガスの発生量の変化を検出するプラズマ発光強度の変化も大きくなり、自動終点検出法によってプラズマ発光強度の変化を検出できる。これにより、本発明の製造方法では、ドライエッチング時におけるプラズマ発光強度の変化を基にロジックゲート形成層25がエッチングされたか否かを判断する自動終点検出法を利用して、ロジックゲート形成層25のエッチング量を決定し得る。 Thus, in the manufacturing method of the present invention, as shown in FIG. 5A, when the logic gate forming layer 25 in the memory circuit region ER1 is removed by dry etching, the logic gate forming layer 25 formed in the peripheral circuit region ER2 is removed. Since the same layered logic gate formation layer 25 remains unprocessed, the amount of etching of the logic gate formation layer 25 in the memory circuit region ER1 also increases, and the reaction that occurs when the logic gate formation layer 25 is dry etched The change in the amount of gas generated also increases. As a result, a change in plasma emission intensity that detects a change in the amount of reaction gas generated during dry etching also increases, and a change in plasma emission intensity can be detected by an automatic end point detection method. Thus, in the manufacturing method of the present invention, the logic gate forming layer 25 is utilized by utilizing an automatic end point detection method for determining whether or not the logic gate forming layer 25 has been etched based on a change in plasma emission intensity during dry etching. The amount of etching can be determined.
　実際上、本発明の製造方法において自動終点検出法を用いる場合には、ロジックゲート形成層25のドライエッチング時にプラズマ発光強度を計測してゆき、一定量のロジックゲート形成層25が残存したことを示すプラズマ発光強度の変化を検出すると、予め特定しておいたエッチング時間でメモリ回路領域ER1におけるロジックゲート形成層25をドライエッチングし、メモリ回路領域ER1におけるロジックゲート形成層25を全て除去し得るようになされている。 Actually, when the automatic end point detection method is used in the manufacturing method of the present invention, the plasma emission intensity is measured at the time of dry etching of the logic gate forming layer 25, and a certain amount of the logic gate forming layer 25 remains. When the change in the plasma emission intensity shown is detected, the logic gate formation layer 25 in the memory circuit region ER1 can be dry-etched in a predetermined etching time so that the logic gate formation layer 25 in the memory circuit region ER1 can be completely removed. Has been made.
　このように本発明の製造方法では、初めにプラズマ発光強度の変化を検出することにより、ロジックゲート形成層25の形成時、仮に当該ロジックゲート形成層25の膜厚に誤差がある場合でも、ロジックゲート形成層25をドライエッチングにより除去してゆく過程で、プラズマ発光強度の変化を目安に、メモリ回路領域ER1にてロジックゲート形成層25が予め決めた一定量となったことを特定し得る。 As described above, in the manufacturing method of the present invention, by detecting the change in the plasma emission intensity first, even when the logic gate formation layer 25 is formed, even if there is an error in the film thickness of the logic gate formation layer 25, the logic In the process of removing the gate formation layer 25 by dry etching, it is possible to specify that the logic gate formation layer 25 has reached a predetermined amount in the memory circuit region ER1 with reference to a change in plasma emission intensity.
　そして、この際、予め、残存した一定量のロジックゲート形成層25を全てドライエッチングにより除去し得、かつメモリ回路領域絶縁層6aをオーバーエッチングしないようなエッチング時間を予め特定しておく。またこの際、周辺回路領域ER2はメモリ回路領域加工レジストP3で覆われてエッチングされないことから、このエッチングとしては等方性エッチングを用いることができる。等方性エッチングを用いて、メモリ回路領域ER1のロジックゲート形成層25を除去した場合には、エッチング途中においてメモリゲート構造体2aの側壁下部にサイドウォール状に残存し得るロジックゲート形成層25（この場合、ポリシリコン）の量が少なくなることから、それを除去するためのオーバーエッチング量も抑えることができ、基板削れ（メモリ回路領域絶縁層6aの削れ）を抑制し得る。 At this time, an etching time is specified in advance so that a certain amount of the remaining logic gate forming layer 25 can be removed by dry etching and the memory circuit region insulating layer 6a is not over-etched. At this time, since the peripheral circuit region ER2 is covered with the memory circuit region processing resist P3 and is not etched, isotropic etching can be used as this etching. When the logic gate forming layer 25 in the memory circuit region ER1 is removed by using isotropic etching, the logic gate forming layer 25 (which can remain in a sidewall shape under the side wall of the memory gate structure 2a during the etching) In this case, since the amount of polysilicon) is reduced, the amount of over-etching for removing it can also be suppressed, and substrate scraping (scratching of the memory circuit region insulating layer 6a) can be suppressed.
　これにより、メモリ回路領域ER1のロジックゲート形成層25が、プラズマ発光強度の変化が小さい、極わずかな量のロジックゲート形成層25となっても、予め設定したエッチング時間を基にドライエッチングすることによって、メモリ回路領域絶縁層6aのオーバーエッチングを抑制しつつ、メモリ回路領域ER1の全てのロジックゲート形成層25を確実に除去し得る。なお、メモリ回路領域ER1において残存した微小なロジックゲート形成層25を、さらにエッチングにより除去する際には、より選択比の高いエッチングを行うことが望ましく、例えば等方性エッチングの後に異方性エッチングを行っても良い。 As a result, even if the logic gate formation layer 25 in the memory circuit region ER1 becomes a very small amount of the logic gate formation layer 25 with a small change in plasma emission intensity, dry etching is performed based on a preset etching time. Thus, all the logic gate forming layers 25 in the memory circuit region ER1 can be surely removed while suppressing over-etching of the memory circuit region insulating layer 6a. Note that when the minute logic gate formation layer 25 remaining in the memory circuit region ER1 is further removed by etching, it is desirable to perform etching with a higher selectivity, for example, anisotropic etching after isotropic etching. May be performed.
　このようにして本発明の製造方法では、図５Ａとの対応部分に同一符号を付して示す図５Ｂのように、メモリ回路領域絶縁層6aのオーバーエッチングを抑制しつつ、メモリ回路領域ER1のロジックゲート形成層25を全て除去し、周辺回路領域ER2にロジックゲート形成層25が残存した状態となり得る。 In this way, in the manufacturing method of the present invention, as shown in FIG. 5B in which parts corresponding to those in FIG. 5A are assigned the same reference numerals, over-etching of the memory circuit region insulating layer 6a is suppressed, and the memory circuit region ER1 is The logic gate formation layer 25 can be completely removed, leaving the logic gate formation layer 25 in the peripheral circuit region ER2.
　次いで、周辺回路領域ER2に形成されたメモリ回路領域加工レジストP3をマスクにして、イオン注入法等によりメモリ回路領域ER1に低濃度のN型不純物を注入し、メモリゲート構造体2aの両脇のメモリウエルMW表面にN型のエクステンション領域D1a,D2aを形成する。次いで、図５Ｂとの対応部分に同一符号を付して示す図５Ｃのように、例えばアッシング等によりメモリ回路領域加工レジストP3を除去する。 Next, using the memory circuit region processing resist P3 formed in the peripheral circuit region ER2 as a mask, low concentration N-type impurities are implanted into the memory circuit region ER1 by an ion implantation method or the like, and both sides of the memory gate structure 2a are N-type extension regions D1a and D2a are formed on the surface of the memory well MW. Next, as shown in FIG. 5C in which the same reference numerals are assigned to portions corresponding to FIG. 5B, the memory circuit region processing resist P3 is removed by, for example, ashing.
　次いで、図５Ｃとの対応部分に同一符号を付して示す図６Ａのように、例えば塗布法によってメモリ回路領域ER1および周辺回路領域ER2に反射防止膜30を形成し、メモリ回路領域ER1のメモリゲート構造体2aや、周辺回路領域ER2のロジックゲート形成層25を反射防止膜30で覆う。次いで、フォトマスクを用いたフォトリソグラフィ技術によって周辺回路領域加工レジストをパターニングし、パターニングされた周辺回路領域加工レジストLP1,LP2,LP3を反射防止膜30上に形成する。 Next, as shown in FIG. 6A in which parts corresponding to those in FIG. 5C are assigned the same reference numerals, an antireflection film 30 is formed in the memory circuit region ER1 and the peripheral circuit region ER2 by, for example, a coating method, The gate structure 2a and the logic gate forming layer 25 in the peripheral circuit region ER2 are covered with an antireflection film 30. Next, the peripheral circuit region processing resist is patterned by a photolithography technique using a photomask, and the patterned peripheral circuit region processing resists LP1, LP2, LP3 are formed on the antireflection film 30.
　この場合、メモリ回路領域ER1には、反射防止膜30を覆う周辺回路領域加工レジストLP1が形成され得る。また、周辺回路領域ER2には、低耐圧周辺回路領域ER3に形成されるロジックゲート15（図１）の形成予定位置に周辺回路領域加工レジストLP2が形成され、高耐圧周辺回路領域ER4に形成されるロジックゲート18（図１）の形成予定位置に周辺回路領域加工レジストLP3が形成される。 In this case, a peripheral circuit region processing resist LP1 covering the antireflection film 30 can be formed in the memory circuit region ER1. In the peripheral circuit region ER2, a peripheral circuit region processing resist LP2 is formed at a position where the logic gate 15 (FIG. 1) formed in the low breakdown voltage peripheral circuit region ER3 is to be formed, and is formed in the high breakdown voltage peripheral circuit region ER4. A peripheral circuit region processing resist LP3 is formed at a planned formation position of the logic gate 18 (FIG. 1).
　そして、フォトマスクを用いて、このような周辺回路領域加工レジストLP1,LP2,LP3を形成する際、ロジックゲート形成層25上に反射防止膜30が形成されていることから、周辺回路領域加工レジストLP1,LP2,LP3をパターニングする際に用いる光がロジックゲート形成層25で乱反射されずに、フォトマスクのパターニングに対応した形状の周辺回路領域加工レジストLP1,LP2,LP3を精度良く形成し得る。 When such peripheral circuit region processing resists LP1, LP2, LP3 are formed using a photomask, the antireflection film 30 is formed on the logic gate forming layer 25. The light used for patterning LP1, LP2, and LP3 is not diffusely reflected by the logic gate forming layer 25, and the peripheral circuit region processing resists LP1, LP2, and LP3 having a shape corresponding to the photomask patterning can be accurately formed.
　次いで、周辺回路領域ER2において周辺回路領域加工レジストLP2,LP3に覆われておらず、外部に露出している反射防止膜30を除去する。これにより、周辺回路領域ER2には、周辺回路領域加工レジストLP2,LP3の形成位置以外の反射防止膜30が除去され、当該反射防止膜30が除去された領域からロジックゲート形成層25が露出した状態となり得る。 Next, the antireflection film 30 that is not covered with the peripheral circuit region processing resists LP2 and LP3 in the peripheral circuit region ER2 and is exposed to the outside is removed. Thereby, in the peripheral circuit region ER2, the antireflection film 30 other than the formation position of the peripheral circuit region processing resists LP2 and LP3 is removed, and the logic gate forming layer 25 is exposed from the region where the antireflection film 30 is removed. It can be a state.
　次いで、同じく周辺回路領域加工レジストLP1,LP2,LP3に覆われておらず、反射防止膜30を除去したことで外部に露出したロジックゲート形成層25を除去し、図６Ａとの対応部分に同一符号を付して示す図６Ｂのように、周辺回路領域ER2のロジックゲート形成予定位置にロジックゲート形成層25を残存させてロジックゲート15,18を形成する。 Next, the logic gate forming layer 25 that is not covered with the peripheral circuit region processing resists LP1, LP2, and LP3 and is exposed to the outside by removing the antireflection film 30 is removed, and is the same as the corresponding part in FIG. 6A. As shown in FIG. 6B, the logic gates 15 and 18 are formed by leaving the logic gate formation layer 25 at the logic gate formation scheduled position in the peripheral circuit region ER2.
　なお、このように、反射防止膜30と、周辺回路領域ER2のロジックゲート形成層25とを順に除去してゆく際、反射防止膜30は、除去される前、ロジックゲート形成層25上だけでなく、当該ロジックゲート形成層25の側壁を沿うように形成されていたことから（図６Ａ）、ロジックゲート形成層25上での反射防止膜30の膜厚分だけ反射防止膜30が除去されることで、ロジックゲート形成層25の側壁に沿ったサイドウォール状の反射防止膜30aが形成される（図６Ｂ）。 As described above, when the antireflection film 30 and the logic gate formation layer 25 in the peripheral circuit region ER2 are sequentially removed, the antireflection film 30 is removed only on the logic gate formation layer 25 before being removed. However, the antireflection film 30 is removed by the thickness of the antireflection film 30 on the logic gate formation layer 25 because it is formed along the side wall of the logic gate formation layer 25 (FIG. 6A). Thus, a sidewall-like antireflection film 30a is formed along the side wall of the logic gate formation layer 25 (FIG. 6B).
　しかしながら、本発明の製造方法では、サイドウォール状に立設した反射防止膜30aが残存し得るものの、当該反射防止膜30aがロジックゲート形成層25のエッチングを妨げることはなく、周辺回路領域加工レジストLP2,LP3の形成位置にだけロジックゲート形成層25を残存させ、ロジックゲート15,18を形成できる。 However, in the manufacturing method of the present invention, although the antireflection film 30a erected in a sidewall shape can remain, the antireflection film 30a does not hinder the etching of the logic gate forming layer 25, and the peripheral circuit region processing resist The logic gate forming layer 25 is left only at the positions where LP2 and LP3 are formed, and the logic gates 15 and 18 can be formed.
　次いで、例えばアッシング等により周辺回路領域加工レジストLP1,LP2,LP3を除去した後、残存した反射防止膜30,30aも除去し、図６Ｂとの対応部分に同一符号を付して示す図６Ｃのように、メモリ回路領域ER1のメモリウエルMWに配置されたメモリゲート構造体2aを外部に露出させるとともに、周辺回路領域ER2のロジックウエルLW1,LW2に配置されたロジックゲート15,18を外部に露出させる。 Next, after the peripheral circuit region processing resists LP1, LP2, LP3 are removed by, for example, ashing or the like, the remaining antireflection films 30, 30a are also removed, and parts corresponding to those in FIG. As described above, the memory gate structure 2a disposed in the memory well MW in the memory circuit region ER1 is exposed to the outside, and the logic gates 15 and 18 disposed in the logic wells LW1 and LW2 in the peripheral circuit region ER2 are exposed to the outside. Let
　次いで、N型用またはP型用にパターニングされたレジスト（図示せず）を用いて周辺回路領域ER2に、イオン注入法等によって低濃度のN型不純物またはP型不純物を注入して、図６Ｃとの対応部分と同一符号を付して示す図７Ａのように、外部に露出している一のロジックウエルLW1表面にエクステンション領域D3a,D4aを形成するとともに、同じく外部に露出している他のロジックウエルLW2表面にエクステンション領域D5a,D6aを形成する。 Next, a low-concentration N-type impurity or P-type impurity is implanted into the peripheral circuit region ER2 by ion implantation or the like using a resist (not shown) patterned for N-type or P-type. As shown in FIG. 7A, the extension regions D3a and D4a are formed on the surface of one logic well LW1 exposed to the outside, and the other portions exposed to the outside are also shown. Extension regions D5a and D6a are formed on the surface of the logic well LW2.
　次いで、N型用またはP型用にパターニングされたレジストを除去した後、図７Ａとの対応部分に同一符号を付して示す図７Ｂのように、メモリゲート構造体2aの側壁や、ロジックゲート構造体3a,4aの側壁にサイドウォールSWを形成する。その後、例えばイオン注入法等により高濃度のN型不純物やP型不純物を必要箇所に注入してソース・ドレイン領域D1,D2,D3,D4,D5,D6を形成する工程等を経ることで、図１に示すような構成を有する半導体集積回路装置1を製造できる。 Next, after removing the resist patterned for N-type or P-type, as shown in FIG. 7B in which parts corresponding to those in FIG. 7A are denoted by the same reference numerals, the side walls of the memory gate structure 2a, logic gates, etc. Sidewalls SW are formed on the side walls of the structures 3a and 4a. After that, for example, a process of forming source / drain regions D1, D2, D3, D4, D5, D6 by injecting high-concentration N-type impurities or P-type impurities into the necessary portions by an ion implantation method or the like, A semiconductor integrated circuit device 1 having the configuration shown in FIG. 1 can be manufactured.
　（３）作用および効果
　以上のような半導体集積回路装置1の製造方法では、メモリウエルMW上にメモリゲート構造体2aが形成されたメモリ回路領域ER1と、ロジックウエルLW1,LW2上にロジックゲート絶縁層7,17が形成された周辺回路領域ER2とに亘って層状のロジックゲート形成層25を形成する（図４Ｂ、ロジックゲート形成層形成工程）。 (3) Action and Effect In the manufacturing method of the semiconductor integrated circuit device 1 as described above, logic gate insulation is provided on the memory circuit region ER1 in which the memory gate structure 2a is formed on the memory well MW and the logic wells LW1 and LW2. A layered logic gate forming layer 25 is formed across the peripheral circuit region ER2 in which the layers 7 and 17 are formed (FIG. 4B, logic gate forming layer forming step).
　また、この半導体集積回路装置1の製造方法では、周辺回路領域ER2のロジックゲート形成層25をメモリ回路領域加工レジストP3により覆い、外部に露出したメモリ回路領域ER1のロジックゲート形成層25を除去することにより、メモリウエルMW上およびメモリゲート構造体2a周辺のロジックゲート形成層25を全て除去する（図５Ｂ、ロジックゲート形成層除去工程）。 Further, in the method of manufacturing the semiconductor integrated circuit device 1, the logic gate forming layer 25 in the peripheral circuit region ER2 is covered with the memory circuit region processing resist P3, and the logic gate forming layer 25 in the memory circuit region ER1 exposed to the outside is removed. As a result, all of the logic gate formation layer 25 on the memory well MW and around the memory gate structure 2a is removed (FIG. 5B, logic gate formation layer removal step).
　これにより、この半導体集積回路装置1の製造方法では、メモリ回路領域ER1のロジックゲート形成層25をドライエッチングによって除去する際、周辺回路領域ER2に形成された層状のロジックゲート形成層25がそのままメモリ回路領域ER1にも残存していることから、その分、メモリ回路領域ER1におけるロジックゲート形成層25のエッチング量を多くなり、ロジックゲート形成層25のエッチングに伴い発生する反応ガスの発生量も多くなる。 Thus, in this method of manufacturing the semiconductor integrated circuit device 1, when the logic gate forming layer 25 in the memory circuit region ER1 is removed by dry etching, the layered logic gate forming layer 25 formed in the peripheral circuit region ER2 is used as it is in the memory. Since it also remains in the circuit region ER1, the amount of etching of the logic gate forming layer 25 in the memory circuit region ER1 increases accordingly, and the amount of reaction gas generated due to the etching of the logic gate forming layer 25 also increases. Become.
　よって、この製造方法では、メモリ回路領域ER1におけるロジックゲート形成層25のドライエッチング時に発生する反応ガスの発生量が多い分、反応ガスに応じて変化するプラズマ発光強度の変化も大きくなるので、ドライエッチング時におけるプラズマ発光強度の変化を基にロジックゲート形成層25がエッチングされたか否かを判断できる。かくして、この製造方法では、ドライエッチング時におけるプラズマ発光強度の変化を基にエッチング対象がエッチングし終えたか否かを判断する自動終点検出法を利用してロジックゲート形成層25のエッチング量を一段と正確に決定でき、メモリ回路領域ER1のロジックゲート形成層25を除去する際にメモリ回路領域絶縁層6aに対するオーバーエッチングを抑制し得る。 Therefore, in this manufacturing method, since the amount of reaction gas generated during dry etching of the logic gate formation layer 25 in the memory circuit region ER1 is large, the change in the plasma emission intensity that changes according to the reaction gas also increases. Whether or not the logic gate forming layer 25 has been etched can be determined based on the change in the plasma emission intensity during the etching. Thus, in this manufacturing method, the amount of etching of the logic gate forming layer 25 is more accurately performed by using an automatic end point detection method that determines whether or not the etching target has been etched based on a change in plasma emission intensity during dry etching. Thus, over-etching of the memory circuit region insulating layer 6a can be suppressed when the logic gate forming layer 25 in the memory circuit region ER1 is removed.
　また、この製造方法では、メモリ回路領域加工レジストP3を除去した後、メモリ回路領域ER1および周辺回路領域ER2に亘って反射防止膜30を形成する（図６Ａ、反射防止膜形成工程）。そして、この製造方法では、露光によってパターニングされた周辺回路領域加工レジストLP1,LP2,LP3を反射防止膜30上に形成し、メモリ回路領域ER1のメモリゲート構造体2aおよびメモリウエルMWを覆った反射防止膜30と、周辺回路領域ER2のロジックゲート形成予定位置にある反射防止膜30とを周辺回路領域加工レジストLP1,LP2,LP3で覆い、周辺回路領域ER2にて外部に露出させた所定領域の反射防止膜30およびロジックゲート形成層25を順に除去する（図６Ｃ、ロジックゲート形成工程）。 In this manufacturing method, after removing the memory circuit region processing resist P3, the antireflection film 30 is formed over the memory circuit region ER1 and the peripheral circuit region ER2 (FIG. 6A, antireflection film formation step). In this manufacturing method, the peripheral circuit region processing resists LP1, LP2, LP3 patterned by exposure are formed on the antireflection film 30, and the reflection covering the memory gate structure 2a and the memory well MW in the memory circuit region ER1. The anti-reflection film 30 and the anti-reflection film 30 at the position where the logic gate is to be formed in the peripheral circuit region ER2 are covered with the peripheral circuit region processing resists LP1, LP2, and LP3, and a predetermined region exposed to the outside in the peripheral circuit region ER2 The antireflection film 30 and the logic gate forming layer 25 are sequentially removed (FIG. 6C, logic gate forming step).
　これにより、この製造方法では、周辺回路領域ER2のロジックゲート形成予定位置にロジックゲート形成層25を残存させてロジックゲート15,18を形成できる。このように本発明の製造方法では、反射防止膜30を形成する際にメモリ回路領域ER1のロジックゲート形成層25が既に除去されていることから、反射防止膜30のパターニングによって一部の反射防止膜30aがメモリ回路領域ER1に残存したとしても、反射防止膜30aがマスクとなってメモリ回路領域ER1にロジックゲート形成層25が残存してしまうことを防止できる。かくして、この製造方法では、ロジックゲート15,18を形成する際に、ロジックゲート形成層25がメモリ回路領域ER1に残存してしまうことを防止できる。 Thereby, in this manufacturing method, the logic gates 15 and 18 can be formed by leaving the logic gate formation layer 25 at the logic gate formation scheduled position in the peripheral circuit region ER2. As described above, in the manufacturing method of the present invention, since the logic gate forming layer 25 in the memory circuit region ER1 has already been removed when forming the antireflection film 30, a part of the antireflection film 30 is patterned by patterning the antireflection film 30. Even if the film 30a remains in the memory circuit region ER1, it is possible to prevent the logic gate formation layer 25 from remaining in the memory circuit region ER1 using the antireflection film 30a as a mask. Thus, this manufacturing method can prevent the logic gate forming layer 25 from remaining in the memory circuit region ER1 when the logic gates 15 and 18 are formed.
　因みに、この製造方法では、ロジックゲート形成層除去工程の後に、メモリ回路領域加工レジストP3をそのままマスクとして利用しメモリ回路領域ER1のメモリウエルMWにエクステンション領域D1a,D2aを形成する（図５Ｃ、エクステンション領域形成工程）。これにより、本発明の製造方法では、メモリ回路領域ER1のメモリウエルにエクステンション領域D1a,D2aを形成する専用のレジストの形成工程が不要となり、その分、製造工程の簡略化を実現し得る。 Incidentally, in this manufacturing method, after the logic gate formation layer removing step, the extension regions D1a and D2a are formed in the memory well MW of the memory circuit region ER1 using the memory circuit region processing resist P3 as it is as a mask (FIG. 5C, extension). Region forming step). Thus, in the manufacturing method of the present invention, a dedicated resist forming step for forming the extension regions D1a and D2a in the memory well of the memory circuit region ER1 becomes unnecessary, and the manufacturing process can be simplified correspondingly.
　なお、この半導体集積回路装置1の製造方法では、メモリ回路領域ER1の加工専用に用いる専用のフォトマスクでレジストをパターニングする専用フォトマスク工程に着目すると、(i)メモリ回路領域ER1の加工専用の第1フォトマスクを用いてパターニングされたレジストP1により、メモリ回路領域ER1の半導体基板Sに不純物を注入し、メモリウエルMWを形成する第1フォトマスク工程（図２Ｂ）と、(ii)メモリゲート絶縁層6、電荷蓄積層EC、上部絶縁層9、およびメモリゲート形成層23を形成した後（図２Ｃ）、メモリ回路領域ER1の加工専用の第2フォトマスクを用いてパターニングした別のレジストP2によりメモリゲート形成層23をパターニングすることにより、メモリゲート10を形成する第2フォトマスク加工工程（図３Ａ）と、(iii)メモリ回路領域ER1の加工専用の第3フォトマスクを用いたパターニングによりメモリ回路領域加工レジストP3を形成する第3フォトマスク加工工程の合計3工程に留めることができる。 In this manufacturing method of the semiconductor integrated circuit device 1, when focusing on a dedicated photomask process for patterning a resist with a dedicated photomask used exclusively for processing the memory circuit region ER1, (i) dedicated to processing the memory circuit region ER1. A first photomask process (FIG. 2B) for injecting impurities into the semiconductor substrate S in the memory circuit region ER1 by the resist P1 patterned using the first photomask to form a memory well MW; and (ii) a memory gate. After forming the insulating layer 6, the charge storage layer EC, the upper insulating layer 9, and the memory gate forming layer 23 (FIG. 2C), another resist P2 patterned using a second photomask dedicated to processing the memory circuit region ER1 Patterning the memory gate formation layer 23 by the second photomask processing step (FIG. 3A) for forming the memory gate 10, and (iii) the memory circuit region ER1. A total of three steps of the third photomask processing step for forming the memory circuit region processing resist P3 can be limited by patterning using a third photomask dedicated to processing.
　かくして、半導体集積回路装置1の製造方法では、一般的な周辺回路の製造プロセスに対して、フォトマスク3枚分の製造プロセスを追加するだけで、メモリ回路領域絶縁層6aに対するオーバーエッチングを抑制しつつ、メモリ回路領域ER1にロジックゲート形成層25が残存せずに全て除去されたメモリ回路領域ER1を形成でき、かくしてフォトマスク3枚分の製造プロセスに留められる分、コスト低減を図ることができる。 Thus, in the method of manufacturing the semiconductor integrated circuit device 1, overetching of the memory circuit region insulating layer 6a is suppressed by adding a manufacturing process for three photomasks to a general peripheral circuit manufacturing process. However, it is possible to form the memory circuit region ER1 in which the logic gate formation layer 25 does not remain in the memory circuit region ER1, and thus the entire memory circuit region ER1 is removed. .
　（４）他の実施の形態
　なお、本発明は、本実施形態に限定されるものではなく、本発明の要旨の範囲内で種々の変形実施が可能であり、例えば、メモリトランジスタの数や、周辺回路の数等は種々の数としてもよく、また、メモリウエルMWやロジックウエルLW1,LW2の導電型もN型またはP型のいずれであってもよい。 (4) Other Embodiments The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the present invention. For example, the number of memory transistors, The number of peripheral circuits and the like may be various numbers, and the conductivity type of the memory well MW and the logic wells LW1 and LW2 may be either N-type or P-type.
　また、上述した実施の形態においては、所定の膜厚でなるロジックゲート絶縁層17がロジックウエルLW2表面に形成された高耐圧周辺回路領域ER4と、高耐圧周辺回路領域ER4のロジックゲート絶縁層17の膜厚よりも膜厚が薄いロジックゲート絶縁層7がロジックウエルLW1表面に形成された低耐圧周辺回路領域ER3とを有した周辺回路領域ER2を形成する場合について述べたが、本発明はこれに限らず、高耐圧周辺回路領域ER4または低耐圧周辺回路領域ER3のいずれか一方だけを有した周辺回路領域ER2を形成するようにしてもよい。 In the above-described embodiment, the high-voltage peripheral circuit region ER4 in which the logic gate insulating layer 17 having a predetermined thickness is formed on the surface of the logic well LW2, and the logic gate insulating layer 17 in the high-voltage peripheral circuit region ER4. Although the case where the peripheral circuit region ER2 having the low breakdown voltage peripheral circuit region ER3 formed on the surface of the logic well LW1 is formed with the logic gate insulating layer 7 whose thickness is thinner than the thickness of the above-described film is described in the present invention, However, the peripheral circuit region ER2 having only one of the high withstand voltage peripheral circuit region ER4 and the low withstand voltage peripheral circuit region ER3 may be formed.
　因みに、上述した実施の形態における周辺回路3,4としては、メモリトランジスタ2と同一エリアに形成されるセンスアンプや、カラムデコーダ、ロウデコーダ等その他種々の周辺回路（直接周辺回路）の他に、メモリトランジスタとは異なるエリアに形成されるCPUや、ASIC、入出力回路等その他種々の周辺回路を適用してもよい。 Incidentally, as the peripheral circuits 3 and 4 in the above-described embodiment, in addition to various peripheral circuits (direct peripheral circuits) such as a sense amplifier, a column decoder, and a row decoder formed in the same area as the memory transistor 2, Various other peripheral circuits such as a CPU, an ASIC, and an input / output circuit formed in a different area from the memory transistor may be applied.
　また、上述した実施の形態においては、図４Ａおよび図４Ｂに示すように、メモリゲート10を形成した後にロジックウエルLW1,LW2を形成するようにした場合について述べたが、本発明はこれに限らず、図２Ａおよび図２Ｂに示したように、メモリゲート10を形成する前のメモリウエルMWを形成する工程と同じ工程にてロジックウエルLW1,LW2を形成し、その後、図２Ｃに示すようにONO膜の形成工程に移行してもよい。 In the above-described embodiment, the case where the logic wells LW1 and LW2 are formed after the memory gate 10 is formed as shown in FIGS. 4A and 4B has been described. However, the present invention is not limited to this. First, as shown in FIGS. 2A and 2B, the logic wells LW1 and LW2 are formed in the same process as the process of forming the memory well MW before forming the memory gate 10, and then, as shown in FIG. 2C. You may move to the ONO film formation process.
　また、上述した実施の形態においては、ロジックゲート形成層をエッチングした際に生じる反応ガスの変化を計測して当該反応ガスの変化を目安にロジックゲート形成層のエッチング量を判定する自動終点検出法として、メモリ回路領域ER1のロジックゲート形成層25をエッチングする際に発生するプラズマ発光強度の変化を計測し、当該プラズマ発光強度の変化を目安にロジックゲート形成層25のエッチング量を判定する自動終点検出法を適用した場合について述べたが、本発明はこれに限らず、メモリ回路領域ER1のロジックゲート形成層25をエッチングする際に発生する反応ガスの成分変化を計測し、当該反応ガスの成分変化を目安にロジックゲート形成層25のエッチング量を判定する自動終点検出法等、その他種々の自動終点検出法を適用してもよい。 In the above-described embodiment, an automatic end point detection method for measuring a change in the reaction gas generated when the logic gate formation layer is etched and determining an etching amount of the logic gate formation layer based on the change in the reaction gas. As an automatic end point, the change in the plasma emission intensity generated when the logic gate formation layer 25 in the memory circuit region ER1 is etched is measured, and the etching amount of the logic gate formation layer 25 is determined based on the change in the plasma emission intensity. Although the case where the detection method is applied has been described, the present invention is not limited to this, the change in the component of the reaction gas generated when the logic gate formation layer 25 in the memory circuit region ER1 is etched is measured, and the component of the reaction gas Various other automatic end point detection methods such as the automatic end point detection method that determines the etching amount of the logic gate forming layer 25 based on the change are suitable. It may be.
　また、上述した実施の形態においては、メモリ回路領域ER1のロジックゲート形成層25に対して自動終点検出法を用いたドライエッチングを行った後、さらに予め設定したエッチング時間を基にドライエッチングすることによって、メモリ回路領域絶縁層6aのオーバーエッチングを抑制しつつ、メモリ回路領域ER1の全てのロジックゲート形成層25を確実に除去するようにした場合について述べたが、本発明はこれに限らず、メモリ回路領域絶縁層6aのオーバーエッチングを抑制しつつ、メモリ回路領域ER1の全てのロジックゲート形成層25を確実に除去し得れば、メモリ回路領域ER1のロジックゲート形成層25に対して自動終点検出法を用いたドライエッチングのみを行うようにしてもよい。 In the above-described embodiment, after performing dry etching using the automatic end point detection method on the logic gate formation layer 25 in the memory circuit region ER1, further dry etching is performed based on a preset etching time. In the above, the case where all the logic gate forming layers 25 in the memory circuit region ER1 are surely removed while suppressing over-etching of the memory circuit region insulating layer 6a has been described, but the present invention is not limited thereto, If all the logic gate formation layers 25 in the memory circuit area ER1 can be surely removed while suppressing over-etching of the memory circuit area insulating layer 6a, an automatic end point with respect to the logic gate formation layers 25 in the memory circuit area ER1 Only dry etching using the detection method may be performed.
　1　半導体集積回路装置
　2　メモリトランジスタ
　2a　メモリゲート構造体
　3,4　周辺回路
　3a,4a　ロジックゲート構造体
　10　メモリゲート
　15,18　ロジックゲート
　6　メモリゲート絶縁層
　6a　メモリ回路領域絶縁層
　7,17　ロジックゲート絶縁層
　9　上部絶縁層
　EC　電荷蓄積層
　ER1　メモリ回路領域
　ER2　周辺回路領域
　P3　メモリ回路領域加工レジスト
　LP1,LP2,LP3　周辺回路領域加工レジスト 1 Semiconductor integrated circuit device 2 Memory transistor 2a Memory gate structure 3,4 Peripheral circuit 3a, 4a Logic gate structure 10 Memory gate 15,18 Logic gate 6 Memory gate insulation layer 6a Memory circuit area insulation layer 7,17 Logic gate insulation Layer 9 Upper insulating layer EC Charge storage layer ER1 Memory circuit area ER2 Peripheral circuit area P3 Memory circuit area processing resist LP1, LP2, LP3 Peripheral circuit area processing resist

Claims (6)

  1. 　メモリゲート絶縁層、電荷蓄積層、上部絶縁層、およびメモリゲートの順で積層されたメモリゲート構造体がメモリウエル上に形成されるメモリ回路領域と、ロジックゲート絶縁層を介してロジックゲートがロジックウエル上に形成される周辺回路領域とを備える半導体集積回路装置の製造方法であって、
    　前記メモリゲート構造体の形成領域以外の前記メモリウエル上にメモリ回路領域絶縁層が形成された前記メモリ回路領域と、前記ロジックウエル上に前記ロジックゲート絶縁層が形成された前記周辺回路領域とに亘って層状のロジックゲート形成層を形成するロジックゲート形成層形成工程と、
    　前記周辺回路領域の前記ロジックゲート形成層をメモリ回路領域加工レジストにより覆い、外部に露出した前記メモリ回路領域の前記ロジックゲート形成層を除去することにより、前記メモリ回路領域絶縁層上および前記メモリゲート構造体周辺の前記ロジックゲート形成層を除去するロジックゲート形成層除去工程と、
    　露光によってパターニングされた周辺回路領域加工レジストを形成し、前記メモリ回路領域の前記メモリゲート構造体および前記メモリ回路領域絶縁層と、前記周辺回路領域のロジックゲート形成予定位置とを前記周辺回路領域加工レジストで覆い、前記ロジックゲート形成層を除去することにより、前記周辺回路領域の前記ロジックゲート形成予定位置に前記ロジックゲート形成層を残存させて前記ロジックゲートを形成するロジックゲート形成工程と、
    　前記周辺回路領域加工レジストを除去する除去工程と
    　を備えることを特徴とする半導体集積回路装置の製造方法。     A memory circuit region in which a memory gate structure in which a memory gate insulating layer, a charge storage layer, an upper insulating layer, and a memory gate are stacked in this order is formed on the memory well, and the logic gate is logic via the logic gate insulating layer A method for manufacturing a semiconductor integrated circuit device comprising a peripheral circuit region formed on a well,
    The memory circuit region in which a memory circuit region insulating layer is formed on the memory well other than the region in which the memory gate structure is formed, and the peripheral circuit region in which the logic gate insulating layer is formed on the logic well. A logic gate forming layer forming step of forming a layered logic gate forming layer,
    The logic gate forming layer in the peripheral circuit region is covered with a memory circuit region processing resist, and the logic gate forming layer in the memory circuit region exposed to the outside is removed, whereby the memory circuit region insulating layer and the memory gate are removed. A logic gate forming layer removing step of removing the logic gate forming layer around the structure;
    Peripheral circuit region processing resist patterned by exposure is formed, and the memory gate structure and the memory circuit region insulating layer in the memory circuit region and a logic gate formation planned position in the peripheral circuit region are processed in the peripheral circuit region processing A logic gate forming step of forming the logic gate by covering the substrate with a resist and removing the logic gate forming layer, thereby leaving the logic gate forming layer in the logic gate forming scheduled position in the peripheral circuit region;
    A removal step of removing the peripheral circuit region processing resist. A method of manufacturing a semiconductor integrated circuit device, comprising:
  2. 　前記ロジックゲート形成層形成工程の前には、
    　前記メモリ回路領域の加工専用の第1フォトマスクを用いてパターニングされたレジストにより、前記メモリ回路領域の半導体基板に不純物を注入し、メモリウエルを形成する第1フォトマスク加工工程と、
    　前記メモリゲート絶縁層、前記電荷蓄積層、前記上部絶縁層、およびメモリゲート形成層を形成した後、前記メモリ回路領域の加工専用の第2フォトマスクを用いてパターニングした別のレジストにより前記メモリゲート形成層をパターニングすることにより、前記メモリゲートを形成する第2フォトマスク加工工程とを備え、
    　前記ロジックゲート形成層除去工程には、前記メモリ回路領域の加工専用の第3フォトマスクを用いたパターニングにより前記メモリ回路領域加工レジストを形成する第3フォトマスク加工工程を含み、
    　前記メモリ回路領域に前記ロジックゲート形成層を残存させずに前記メモリゲートを形成するために専用のフォトマスクを用いた専用フォトマスク工程が、前記第1フォトマスク加工工程、前記第2フォトマスク加工工程、および前記第3フォトマスク加工工程の合計3工程である
    　ことを特徴とする請求項１記載の半導体集積回路装置の製造方法。     Before the logic gate forming layer forming step,
    A first photomask processing step of implanting impurities into the semiconductor substrate of the memory circuit region by a resist patterned using a first photomask dedicated to processing of the memory circuit region, and forming a memory well;
    After the memory gate insulating layer, the charge storage layer, the upper insulating layer, and the memory gate forming layer are formed, the memory gate is formed by another resist patterned using a second photomask dedicated to processing the memory circuit region. A second photomask processing step of forming the memory gate by patterning a formation layer,
    The logic gate formation layer removal step includes a third photomask processing step of forming the memory circuit region processing resist by patterning using a third photomask dedicated to processing the memory circuit region,
    A dedicated photomask process using a dedicated photomask for forming the memory gate without leaving the logic gate formation layer in the memory circuit region includes the first photomask processing process and the second photomask processing process. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a total of three processes including a process and the third photomask processing process are performed.
  3. 　前記ロジックゲート形成層除去工程の後に、前記メモリ回路領域加工レジストをマスクとして利用し前記メモリ回路領域の前記メモリウエルにエクステンション領域を形成するエクステンション領域形成工程を備える
    　ことを特徴とする請求項１または２記載の半導体集積回路装置の製造方法。     The extension region forming step of forming an extension region in the memory well of the memory circuit region using the memory circuit region processing resist as a mask after the logic gate forming layer removing step. 3. A method of manufacturing a semiconductor integrated circuit device according to 2.
  4. 　前記ロジックゲート形成層形成工程にて前記ロジックゲート形成層が形成される、前記メモリ回路領域絶縁層の膜厚が4［nm］以下である
    　ことを特徴とする請求項１～３のうちいずれか１項記載の半導体集積回路装置の製造方法。     4. The film thickness of the memory circuit region insulating layer in which the logic gate forming layer is formed in the logic gate forming layer forming step is 4 [nm] or less. A method for manufacturing a semiconductor integrated circuit device according to claim 1.
  5. 　前記ロジックゲート形成層除去工程では、
    　前記ロジックゲート形成層をドライエッチングした際に生じる反応ガスの変化を計測して当該反応ガスの変化を目安に前記ロジックゲート形成層のエッチング量を判定する自動終点検出法を用いて、前記ロジックゲート形成層を除去する
    　ことを特徴とする請求項１～４のうちいずれか１項記載の半導体集積回路装置の製造方法。     In the logic gate formation layer removal step,
    By using an automatic end point detection method for measuring a change in a reaction gas generated when dry-etching the logic gate formation layer and determining an etching amount of the logic gate formation layer based on the change in the reaction gas, the logic gate 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the formation layer is removed.
  6. 　前記ロジックゲート形成層除去工程では、
    　等方性エッチングを含んだエッチングを行うことにより、前記メモリ回路領域の前記ロジックゲート形成層を除去する
    　ことを特徴とする請求項１～５のうちいずれか１項記載の半導体集積回路装置の製造方法。     In the logic gate formation layer removal step,
    6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the logic gate forming layer in the memory circuit region is removed by performing etching including isotropic etching. Method.
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