JP2005166714A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device which uses a method for removing a hard mask without damaging a gate pattern formed on a semiconductor substrate. <P>SOLUTION: In the manufacturing method of the semiconductor device, (1) multilayer films 3, 5, 7 and 9 for forming the gate pattern are formed on the semiconductor substrate 1, and (2) the hard mask 11 patterned in a prescribed shape is formed on the multilayer film. (3) The hard masks 11 are made as masks and the multilayer films 5, 7 and 9 are etched so as to form the gate pattern. (4) Protection materials 15 are buried in recessed parts formed by etching in such a way that surfaces of the hard masks 11 are exposed so that the side wall of the gate pattern is covered. (5) The hard masks 11 are removed. Since the side wall of the gate pattern is protected by the protection materials 15 before the hard masks 11 are removed, the hard masks 11 can be removed without damaging the gate pattern. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device using a hard mask, and is particularly suitable for manufacturing a semiconductor device having a two-layer gate structure.

In recent years, miniaturization of highly integrated gate processing is required in a semiconductor device having a two-layer gate structure such as a flash memory.
FIG. 3 is a cross-sectional view of a general flash memory 51. The flash memory 51 includes a semiconductor substrate 53, a source / drain region 55 formed in the semiconductor substrate 53, a lower gate oxide film 57, a floating gate 59, an interlayer gate oxide formed sequentially between the source / drain regions 55. A two-layer gate comprising a film 60 and a control gate 61 is provided, and an interlayer insulating film 62 is formed so as to cover them. By applying a voltage to the control gate 61, a tunnel current is generated through the lower gate oxide film 57, and electrons are injected into the floating gate 59 by this current.

  The two-layer gate is generally formed by the following method. First, thin films for forming a lower gate oxide film 57, a floating gate 59, an interlayer gate oxide film 60, and a control gate 61 are sequentially formed on the semiconductor substrate 53. Next, a mask (not shown) patterned in a predetermined shape is formed thereon, and plasma is sequentially applied to the control gate 61, the interlayer gate oxide film 60, and the floating gate 59 in a self-alignment manner using the mask. A two-layer gate is formed by dry etching.

  As described above, in the step of forming the two-layer gate, the multilayer film is etched at the same time, so that the thickness of the layer to be dry-etched is increased. For this reason, for example, when a resist mask is used as an etching mask for forming a gate pattern, it is generally necessary to increase the thickness of the resist mask in order to ensure plasma resistance, which makes fine processing difficult. Therefore, a method is used in which a photolithography technique is used to once form a pattern of an oxide film and the like, and etching is performed using the oxide film as a hard mask.

A conventional manufacturing method of a two-layer gate using a hard mask will be described with reference to FIG. 4 (see, for example, Patent Document 1).
First, a silicon oxide film 64 of about 10 nm is formed on the semiconductor substrate 63. Thereafter, a first polysilicon layer 65 is formed to a thickness of about 120 nm by using a low pressure CVD method. If necessary, this film is doped with phosphorus to lower the resistance value. Thereby, the structure shown in FIG. 4A is obtained.

  Next, a so-called ONO film (oxide / nitride / oxide film) 67 serving as an interlayer gate insulating film is formed. This ONO film is composed of three layers: silicon oxide obtained by thermally oxidizing the surface of the first polysilicon layer 65, silicon nitride film formed by the CVD method, and silicon oxide obtained by oxidizing the silicon nitride surface. Constitute. Further, a second polysilicon layer 69 is formed by using a low pressure CVD method. Thereby, the structure shown in FIG. 4B is obtained.

  Next, a hard mask layer 71 made of a composite film of a silicon nitride film and a silicon oxide film is formed on the second polysilicon layer 69, and the hard mask is formed using the resist mask 73 as a mask using photolithography and etching techniques. 71 is patterned. Thereby, the structure shown in FIG. 4C is obtained.

Next, using the hard mask 71, the second polysilicon layer 69, the ONO film 67, and the first polysilicon layer 65 are etched by the RIE method, the resist mask 73 is removed, and impurity implantation is performed for source / drain. A region 75 is formed, and an interlayer insulating film 77 is formed so as to cover the whole. Thereby, the structure shown in FIG. 4D is obtained. The hard mask 71 is not removed and becomes a part of the interlayer insulating film 77.
JP 2000-243937 A

  However, if the hard mask 71 is left as a part of the interlayer insulating film 77, the thickness of the interlayer insulating film 77 increases, and after the formation of the interlayer insulating film 77, contact holes for forming extraction electrodes from the source / drain regions 75 are formed. It becomes difficult to create. In addition, after forming a two-layer gate, it is necessary to selectively perform oxide film etching or ion implantation when forming a source between adjacent two-layer gates for forming a transistor. When the distance between the two-layer gates is 0.2 μm or less, it is difficult to selectively perform only the source region using a photolithography process. In order to solve these problems, it is necessary to remove the hard mask. However, when removing the silicon oxide and silicon nitride used as the hard mask 71, an acid such as hydrofluoric acid or phosphoric acid is generally used. However, in this case, there is a problem that side etching occurs in the ONO film 67.

  The present invention provides a method of manufacturing a semiconductor device using a method of removing a hard mask without damaging a gate pattern formed on a semiconductor substrate.

  The method for manufacturing a semiconductor device of the present invention includes (1) forming a multilayer film for forming a gate pattern on a semiconductor substrate, (2) forming a hard mask patterned in a predetermined shape on the multilayer film, (3) The gate pattern is formed by etching the multilayer film using the hard mask as a mask, and (4) at least the sidewall of the gate pattern is covered with the recess formed by the etching so that the hard mask surface is exposed. (5) removing the hard mask, and (6) forming a source / drain region corresponding to the gate pattern on the semiconductor substrate.

  Since the side walls of the gate pattern are protected with a protective material before removing the hard mask, the hard mask can be removed without damaging the gate pattern.

According to the present invention, since the hard mask can be removed without damaging the gate pattern formed on the semiconductor substrate, it is possible to reduce problems in manufacturing the semiconductor device.
Further, according to the present invention, since the interlayer insulating film can be formed after removing the hard mask, the thickness of the interlayer insulating film can be reduced. As a result, it becomes easy to form a contact hole for forming an extraction electrode from the source / drain region after forming the interlayer insulating film.

  The method for manufacturing a semiconductor device according to the first embodiment of the present invention includes (1) forming a multilayer film for forming a gate pattern on a semiconductor substrate, and (2) patterning the multilayer film in a predetermined shape. (3) A gate pattern is formed by etching the multilayer film using the hard mask as a mask, and (4) a recess formed by etching so that the hard mask surface is exposed. A step of embedding a protective material so as to cover at least the sidewall of the gate pattern, (5) removing the hard mask, and (6) forming a source / drain region corresponding to the gate pattern on the semiconductor substrate.

  First, the step (1), that is, the step of forming a multilayer film for forming a gate pattern on a semiconductor substrate will be described.

  In this specification, “on the semiconductor substrate” includes a contact with the semiconductor substrate, a contact with the semiconductor substrate through a protective layer, an insulating film, or the like, or an upper side without contact with the semiconductor substrate. It is. The same applies to other films and layers.

  As the semiconductor substrate, for example, an elemental semiconductor substrate such as Si or Ge, or a compound semiconductor substrate such as GaAs, GaN, GaP, InP, ZnO, or ZnSe can be used. These may be single crystals or polycrystalline. The semiconductor substrate may be doped n-type or p-type, and an n-type or p-type well may be formed in a region where the semiconductor device is formed. In particular, it is preferable to use a p-type silicon single crystal substrate.

  The multilayer film includes, for example, a gate insulating film and a conductive film, or includes a first gate insulating film, a first conductive film, a second gate insulating film, and a second conductive film. When the former multilayer film is formed, the gate pattern can be formed by patterning a conductive film by etching. For example, a MOSFET or DRAM can be manufactured as a semiconductor device. When the latter multilayer film is formed, the gate pattern can be formed by patterning the second conductive film, the second gate insulating film, and the first conductive film by etching. As a semiconductor device, for example, a flash memory or the like The nonvolatile semiconductor memory device can be manufactured.

  As the gate insulating film, for example, a silicon oxide film, a silicon nitride film, an ONO film, or the like can be used. As the conductive film, for example, a metal film such as Al, a polysilicon film, a silicide film, a polycide film, or the like can be used. An impurity such as phosphorus may be added to the polysilicon film in order to reduce its electric resistance. These films can be formed by a known method such as a CVD method.

  Next, the step (2), that is, the step of forming a hard mask patterned into a predetermined shape on the multilayer film will be described.

The hard mask can be formed by forming a thin film made of a material for forming the hard mask on the multilayer film and patterning the thin film by photolithography and etching techniques. The hard mask can be formed of a material having plasma resistance. For example, the hard mask can be formed of a material containing silicon oxide or silicon nitride as a main component.
The predetermined shape is, for example, the shape of the gate pattern of the semiconductor device.

  Next, the step (3), that is, a step of forming a gate pattern by etching a multilayer film using a hard mask as a mask will be described.

When the photoresist remains on the hard mask, the resist may be removed by ashing or the like before the step (3), or may be removed after the step (3).
Etching can be performed by, for example, the RIE method. Further, the entire multilayer film may be etched or a part thereof may be etched. For example, when the multilayer film includes a first gate insulating film, a first conductive film, a second gate insulating film, and a second conductive film, etching can be performed while leaving the first gate insulating film.

  Next, the step (4), that is, a step of embedding a protective material so as to cover at least the side wall of the gate pattern in the recess formed by etching so that the hard mask surface is exposed will be described.

As the protective material, for example, a resin such as a resin resist can be used, and it is particularly preferable to use a resin that can be removed by O ₂ plasma. In addition to the resin, inorganic materials such as PSG and BPSG and organic materials such as MSQ may be used. The protective material is preferably a material having a low etching selectivity with respect to the hard mask, that is, a material that is not easily eroded by etching. When such a material is used, the hard mask can be removed in a process described later without the protective material being eroded.

As a method of embedding the protective material, (a) a method of embedding the protective material in a recess formed by etching so as to cover the hard mask, and (b) a method of etching back the protective material so that the hard mask surface is exposed. Can be used.
Further, a protective material may be embedded so as to cover the side wall of the gate pattern at a height below the hard mask surface. “Covering the side wall of the gate pattern” includes a case where a part of the side wall is covered. For example, the gate pattern includes a first gate insulating film, a first conductive film, a second gate insulating film, and a second conductive film. In the case where the second gate insulating film is easily eroded by etching, the side walls of the second gate insulating film are covered with a protective material.

  Next, the step (5), that is, the step of removing the hard mask will be described.

As a method for removing the hard mask, a method that does not damage the uppermost layer of the multilayer film, has little erosion to the protective material, and effectively removes the hard mask can be preferably used.
For example, when the hard mask contains silicon oxide as a main component, the hard mask can be removed by wet etching using hydrofluoric acid. In the case where the hard mask contains silicon nitride as a main component, the hard mask can be removed by wet etching using phosphoric acid.
In order to effectively perform this step, the hard mask is, for example, the first gate insulating film, the first conductive film, the second gate insulating film, and the second conductive film with respect to the uppermost layer of the multilayer film. When it consists of, it is preferable to form with a material with a large etching selectivity with respect to a 2nd electrically conductive film.

  After removing the hard mask, the protective material may or may not be removed. That is, after removing the protective material, a post-process such as formation of an interlayer insulating film may be performed, or a part of the interlayer insulating film may be formed of the protective material without removing the protective material. In the case where the protective material is not removed, it is preferable to use a material suitably used for the interlayer insulating film such as BPSG as the protective material. Further, before embedding the protective material, a process described later, that is, a gate is formed on the semiconductor substrate. It is preferable to perform a step of forming source / drain regions corresponding to the pattern.

  Further, after the step (5), before the step of embedding the protective material or before the step of forming the multilayer film, a step of forming source / drain regions corresponding to the gate pattern on the semiconductor substrate may be provided.

The source / drain regions can be formed, for example, by performing ion implantation of boron, phosphorus, arsenic or the like in a self-aligning manner using the gate pattern as a mask.
All the processes may be interchanged without departing from the object of the present invention, and everything that can remove the hard mask while protecting the gate pattern according to the principle of the present invention is included in the scope of the present invention.

  1 and 2 are process diagrams showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. The method for manufacturing a semiconductor device according to the present embodiment will be described with reference to these drawings.

  First, a silicon oxide film 3 of about 10 nm that becomes a gate oxide film is formed on the surface of the silicon substrate 1 by thermal oxidation. Next, a first polysilicon layer 5 serving as a floating gate having a two-layer gate structure is formed to a thickness of about 120 nm by using a low pressure CVD method. If necessary, this film is doped with phosphorus to lower the resistance value. Thereby, the structure shown in FIG. 1A is obtained.

  Next, a so-called ONO film (oxide / nitride / oxide film) 7 to be an interlayer gate insulating film is formed. The ONO film 7 includes three layers of silicon oxide obtained by thermally oxidizing the surface of the first polysilicon layer 5, a silicon nitride film formed by a CVD method, and a silicon oxide obtained by oxidizing the silicon nitride surface. The total thickness of the three layers is about 20 nm. Next, a second polysilicon layer 9 to be a control gate is formed with a film thickness of about 250 nm using a low pressure CVD method. Thereby, the structure shown in FIG. 1B is obtained.

  Next, a silicon oxide film 11 serving as a hard mask is formed with a thickness of 80 nm or more by plasma CVD, and the silicon oxide film 11 is patterned using the resist mask 13 as a mask by a photolithography process. Thereby, the structure shown in FIG. 1C is obtained. The hard mask 11 may be formed using silicon nitride, which is a material having a high etching selectivity with respect to the polysilicon layer 9.

  Next, etching is performed using a hard mask 11 made of a silicon oxide film. This etching is self-aligned etching, and the second polysilicon layer 9, the ONO film 7, and the first polysilicon layer 5 are continuously etched by the RIE method. After the etching, the resist mask 13 used for patterning the hard mask 11 is removed by ashing. Thereby, the structure shown in FIG. 1D is obtained.

  Next, a resist is applied to a thickness of about 500 nm with a coater, and baking is performed at about 100 ° C. for 60 seconds with a hot plate, and the protective material 15 is embedded in the recess formed between the two-layer gates in the above process. At this time, the protective material 15 is embedded so as to completely cover the surface of the hard mask 11. The protective material 15 protects the ONO film 7 when removing the hard mask. As a result, the structure shown in FIG.

  Next, the protective material 15 is etched back by the RIE method so that the surface of the hard mask 11 is completely exposed to obtain the structure shown in FIG. At this time, the surface of the second polysilicon layer 9 is protected from plasma by the hard mask 11.

  Next, the hard mask 11 made of silicon oxide is removed by wet etching using hydrofluoric acid to obtain the structure shown in FIG. At this time, since the protective material 15 is buried between the plurality of two-layer gates, side etching does not occur in the ONO film 7.

Next, the protective material 15 is removed by O ₂ plasma, arsenic ion implantation is performed in a self-aligned manner using the two-layer gate as a mask, thereby forming a source / drain region 17 and an interlayer insulating film 19. The structure shown in FIG. 2H is obtained, and the manufacture of the semiconductor device according to this example is completed.

It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device. It is process sectional drawing which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Silicon oxide film 5 1st polysilicon layer 7 ONO film 9 2nd polysilicon layer 11 Silicon oxide film 13 Resist mask 15 Protective material 17 Source / drain region 19 Interlayer insulating film 51 Flash memory 53 Semiconductor substrate 55 Source substrate Drain region 57 Lower gate oxide film 59 Floating gate 60 Interlayer gate oxide film 61 Control gate 62 Interlayer insulating film 63 Semiconductor substrate 64 Silicon oxide film 65 First polysilicon layer 67 ONO film 69 Second polysilicon layer 71 Hard mask 73 Resist mask 75 Source / drain region 77 Interlayer insulating film

Claims (7)

  (1) A multilayer film for forming a gate pattern is formed on a semiconductor substrate, (2) a hard mask patterned into a predetermined shape is formed on the multilayer film, and (3) a hard mask as a mask, A gate pattern is formed by etching the multilayer film, and (4) a protective material is embedded in the recess formed by etching so as to cover at least the side wall of the gate pattern so that the hard mask surface is exposed. A method for manufacturing a semiconductor device comprising a step of removing a hard mask.   The multilayer film is formed by laminating the first gate insulating film, the first conductive film, the second gate insulating film, and the second conductive film in this order, and the gate pattern includes the second conductive film, the second gate insulating film, and the first conductive film. The manufacturing method of Claim 1 formed by etching 1 electrically conductive film.   The manufacturing method according to claim 2, wherein the hard mask is formed of a material having a high etching selectivity with respect to the second conductive film.   The manufacturing method according to claim 1, wherein the hard mask is formed of a material mainly composed of silicon oxide or silicon nitride.   Step (4) is a step of (a) embedding a protective material in a recess formed by etching so as to cover the hard mask, and (b) performing an etch-back of the protective material so that the hard mask surface is exposed. Item 5. The production method according to any one of Items 1 to 4.   The manufacturing method according to any one of claims 1 to 5, further comprising a step of removing the protective material after the step (5).   The manufacturing method according to claim 1, further comprising forming a source / drain region corresponding to the gate pattern on the semiconductor substrate.

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