JP2007141962A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of achieving a high yield and high reliability while suppressing electric short-circuit defects apt to occur between sets of wiring adjacent to each other, and to provide its manufacturing method. <P>SOLUTION: The semiconductor storage device is provided with a memory cell 10, a dummy cell 14, and a well contact 12. The memory cell 10 has a memory cell active region 20 having a minute plane pattern width and a memory cell element isolation region 18. The well contact 12 has a well contact active region 34 having a plane pattern width wider than that of the memory cell active region 20. Each plane pattern width of a dummy cell active region 38 and a dummy cell element isolation region 40 partitions the dummy cell active region 38, and is optimized in the dummy cell 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a structure of a word line and a dummy cell portion in the semiconductor memory device and a manufacturing method thereof.

  In the memory cell array of the semiconductor memory device, there is a region where the periodicity of the planar pattern width of the active region cannot be maintained unlike the memory cell portion for storing data (see, for example, Patent Document 1). Here, the active region of the memory cell portion generally has a channel region of a MOS transistor and a source region and a drain region disposed in a pair with the channel region therebetween.

By the way, as the region where the periodicity cannot be maintained, for example, an active region such as a well contact portion in the memory cell array or a guard ring portion at the end of the memory cell array corresponds to this. In these portions, the well contact portion considering the size of the contact portion and the alignment margin, and the active region having a wider plane pattern width than the memory cell portion in consideration of the variation in the plane pattern size at the memory cell array end. Needed.

In the situation described above, between the well contact portion and the memory cell portion provided in the memory cell array, or between the guard ring portion and the memory cell portion, each planar pattern width of each active region and the element isolation region partitioning the active region is obtained. In order to adjust the difference, a dummy cell portion which is not used as a normal memory cell is provided. In the periphery of the dummy cell portion, the periodicity of the planar pattern width of the active region is disturbed, so that the exposure resolution in the photolithography process tends to be lowered.

Therefore, Patent Document 1 discloses that the planar pattern widths of element isolation regions and word lines (corresponding to the pattern widths of band-shaped element isolation regions or word lines in Patent Document 1) are the same width or the same width. The method for avoiding the disturbance of the periodicity of the planar pattern width by making the above is described. However, as described above, it is difficult to simply apply this method when plane patterns having different widths necessarily exist in the memory cell array.

Further, conventionally, the same planar pattern as that of the memory cell portion is adopted also in the dummy cell portion, and the planar pattern width of the element isolation region provided in the dummy cell portion is directed from the memory cell portion to the well contact portion or the guard ring portion. By gradually widening according to the above, the problem of the resolution reduction of the exposure is dealt with.

By the way, in the memory cell region of the electrically rewritable nonvolatile semiconductor memory device, in order to increase the coupling capacitance between the floating gate electrode and the control gate electrode, not only the upper surface of the floating gate electrode but also its side wall portion. Is also used as a capacitor element region. Therefore, in the memory cell region, the upper end portion of the element isolation film adjacent to the floating gate electrode is lower than the upper end portion of the floating gate electrode, and a step portion is generated above the floating gate electrode and the element isolation film. It has a structure.

On the other hand, in the element isolation region of the dummy cell portion described above, the planar pattern width of the region is wider than that of the memory cell portion. Therefore, a recess is generated at the upper end portion of the conductive polysilicon for the control gate electrode provided above the element isolation region. Further, in the gate wiring for the control gate electrode (for example, WSi) provided on the upper portion of the conductive polysilicon, the thickness of the gate wiring is formed thicker in accordance with the depth of the recess as compared with the periphery of the recess. The

In the concave portion as described above, when the gate line and the conductive polysilicon provided thereunder are processed to form a word line (that is, a control gate electrode), a processing residue of the gate line and the conductive polysilicon is generated. As a result, there is a very high risk of causing an electrical short circuit failure between adjacent word lines.
JP 2000-49316 A

The present invention provides a semiconductor memory device and a method for manufacturing the same that can suppress electrical short-circuit defects that are likely to occur between adjacent wirings, and can achieve high yield and high reliability.

One embodiment of the present invention includes a semiconductor substrate, a first active region having a first planar pattern width provided on a surface side of the semiconductor substrate, and a first active region spaced apart from the first active region on the surface side of the semiconductor substrate. And a second active region having a second planar pattern width wider than the first planar pattern width, and between the first active region and the second active region on the surface side of the semiconductor substrate A third active region having a third planar pattern width, a first gate electrode formed on the first active region via a first insulating film, and a first insulation on the second active region. A second gate electrode formed through the film, a third gate electrode formed on the third active region through the first insulating film, and provided between the first active region and having an upper end portion Provided adjacent to the first element isolation region and the third active region. A second element isolation region having an upper end, and a second insulation provided on the first gate electrode, on the second gate electrode, on the third gate electrode, and on the second element isolation region. Each of the first gate electrode, the second gate electrode, and the third gate electrode and an upper end portion of the second element isolation region are located on the same plane, and the semiconductor substrate. The distance from the back surface of the first element isolation region to the upper end portion of the first element isolation region is shorter than the distance from the back surface of the semiconductor substrate to the upper end portion of the second element isolation region.

Another embodiment of the present invention includes a step of forming a first insulating film on a surface of a semiconductor substrate, a step of forming a gate electrode layer on the first insulating film, and a step of forming a gate electrode layer on the gate electrode layer. Forming a second insulating film; patterning the second insulating film; using the patterned second insulating film as a mask; the gate electrode layer; the first insulating film; and part of the semiconductor substrate A first element isolation region groove adjacent to the first active planned region having the first planar pattern width, and a second active having a second planar pattern width wider than the first planar pattern width Forming a second element isolation region groove adjacent to a predetermined region; embedding an insulator in the first and second element isolation region grooves; and the first and second element isolation region grooves. The insulators embedded in the interior of each The height of the upper end portion of the insulator embedded in the first and second element isolation region trenches from the back surface of the semiconductor substrate is set to the height of the semiconductor substrate at the upper end portion of the gate electrode layer. Forming the same height from the back surface, and further removing the insulator embedded in the first element isolation region trench and removing the insulator embedded in the first element isolation region trench Forming a height of an upper end portion of the object from the back surface of the semiconductor substrate between the upper end portion of the gate electrode and the upper end portion of the first insulating film.

  According to the present invention, it is possible to provide a semiconductor memory device and a manufacturing method thereof that can suppress electrical short-circuit defects that are likely to occur between adjacent wirings, and can achieve high yield and high reliability.

Examples of the present invention will be described below.

A semiconductor memory device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS.

In the first embodiment, the first active region having the first planar pattern width is the memory cell active region 20 of the memory cell unit 10, and the first element isolation region is provided between the memory cell active regions 20. This is a memory cell element isolation region 18. The second active region having the second planar pattern width is the well contact active region 34 of the well contact portion 12. The third active region is located between the first active region (memory cell active region 20) and the second active region (well contact active region 34), and constitutes a third active region (dummy cell) constituting the dummy cell portion 14. Active region 38). The second element isolation region is a dummy cell element isolation region 40 adjacent to the third active region (dummy cell active region 38).

Here, the memory cell active region 20 includes a channel region of a MOS transistor and a source region and a drain region that are disposed in a pair in the gate length direction with the channel region therebetween. The first insulating film and the second insulating film are an inter-gate insulating film 26 between a control gate and a floating gate such as an oxide film 22 and an ONO (Oxide-Nitride-Oxide) film, respectively. The oxide film 22 is used as a tunnel oxide film in the memory cell unit 10.

1A and 1B are diagrams showing main parts of a memory cell array of a semiconductor memory device that is Embodiment 1 of the present invention, where FIG. 1A is a plan view thereof, and FIG. 1B is taken along line AA in FIG. It is sectional drawing.

As shown in FIG. 1, the semiconductor memory device includes a memory cell unit 10 for storing data, a well contact unit 12 for controlling the potential of a well provided in a semiconductor substrate 16, a memory cell unit 10, A dummy cell portion 14 is provided between the well contact portion 12 and not used as a memory cell.

The memory cell unit 10 includes a memory cell active region 20 and a memory cell element isolation region 18 having a fine planar pattern width. The well contact portion 12 has a well contact active region 34 having a wider planar pattern width than the memory cell active region 20.

In the dummy cell section 14, as described below, the planar pattern widths of the dummy cell active region 38 and the dummy cell element isolation region 40 partitioning the dummy cell active region 38 are optimized. That is, in the dummy cell portion 14, the pattern resolution in the photolithography process is not lowered between the memory cell portion 10 and the well contact portion 12 that disturbs the periodicity of the periodic plane pattern of the memory cell portion 10. The plane pattern width is adjusted.

The dummy cell portion 14 is provided with a portion where the planar pattern width of the dummy cell element isolation region 40 is wider than the planar pattern width of the memory cell element isolation region 18.

The memory cell unit 10 has an oxide film 22 on the surface of the memory cell active region 20 separated by the memory cell element isolation region 18 on the semiconductor substrate 16 (in the memory cell unit of the first embodiment, functions as a tunnel oxide film). The floating gate electrode 24 is formed through the gap. A conductive polysilicon 28 and a gate wiring 30 are sequentially formed on the floating gate electrode 24 via an inter-gate insulating film 26 such as an ONO (Oxide-Nitride-Oxide) film. A control gate electrode 31 (that is, a word line) is composed of the laminated film of the conductive polysilicon 28 and the gate wiring 30. The gate wiring 30 is made of, for example, WSi.

Here, the memory cell element isolation region 18 is formed by embedding a memory cell element isolation film 50 such as an oxide film in the memory cell element isolation trench 48. The distance from the back surface of the semiconductor substrate 16 to the upper end portion of the memory cell element isolation film 50 embedded in the memory cell element isolation groove 48 of the memory cell portion is from the back surface of the semiconductor substrate 16 to the upper end portion of the floating gate electrode 24. It is configured to be shorter than the distance. The intergate insulating film 26 provided on the floating gate electrode 24 is provided so as to be in contact with the side wall of the floating gate electrode 24, and at the same time, the conductive polysilicon 28 provided on the intergate insulating film 26 includes two adjacent polysilicons. It is formed so as to be buried between the floating gate electrodes 24, that is, also on the memory cell element isolation region 18.

As a result, in the memory cell 32 (described in FIG. 1A) in the memory cell unit 10, since the facing area increases between the floating gate electrode 24 and the control gate electrode 31, a larger coupling between both gates. Capacity can be obtained.

Here, the memory cell 32 shown in FIG. 1A is paired with a channel region (below the control gate electrode 31 of the memory cell active region 20) provided on the surface of the semiconductor substrate 16 and a pair in the gate length direction across the channel region. A memory cell active region 20 having a source region 32A and a drain region 32B to be disposed is provided. Further, the memory cell 32 is formed on the memory cell active region 20 via an oxide film 22 and on the floating gate electrode 24 via an inter-gate insulating film 26 such as an ONO film. The memory cell transistor has a control gate electrode 31.

Further, the well contact portion 12 includes a well contact active region 34 having a wider planar pattern width than the memory cell active region 20 on the semiconductor substrate 16. Further, the well contact portion 12 is formed on the well contact active region 34 via the oxide film 22 and is not used for the memory operation. The well contact portion dummy electrode 36 is formed on the well contact portion dummy electrode 36. A control gate electrode 31 formed through an intergate insulating film 26 such as a film passes therethrough. The well contact active region 34 is in contact at any position (not shown) in order to fix the well potential.

The dummy cell part 14 is located between the well contact part 12 and the memory cell part 10 and has a plurality of dummy cell active regions 38 having different plane pattern widths. It has a similar cross-sectional structure. The dummy cell section 14 includes a plurality of dummy cell element isolation regions 40 (consisting of dummy cell element isolation grooves 49 and dummy cell element isolation films 51 embedded therein) each having a different planar pattern width. Normally, the dummy cell portion 14 is provided with a portion where the planar pattern width of the dummy cell element isolation region 40 is wider than the planar pattern width of the memory cell element isolation region 18 of the memory cell portion 10.

Here, in the dummy cell portion 14, the upper end portion of the dummy cell portion dummy electrode 42 (not used for the memory operation) is positioned substantially on the same plane as the upper end portion of the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49. Is formed. Therefore, the intergate insulating film 26 formed so as to cover both surfaces of the dummy cell element isolation region 40 and the dummy cell portion dummy electrode 42 has a substantially flat film structure. Further, the conductive polysilicon 28 and the gate wiring 30 sequentially provided on the flat inter-gate insulating film 26 also have a flat film structure.

However, in the dummy cell portion 14, the upper end portion of the dummy cell portion dummy electrode 42 needs to be formed so as to be completely flush with the upper end portion of the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49. Not necessarily. That is, the level difference may be reduced to such an extent that the film thickness of the gate wiring 30 (for example, WSi) becomes substantially uniform.

  Next, a method for manufacturing the semiconductor memory device of Example 1 will be described. 2 to 6 are diagrams for explaining the steps of the manufacturing method and correspond to FIG. 1 described above. In each drawing, (a) is a plan view showing the state of the main part of the semiconductor memory device in each step, and (b) is a cross-sectional view taken along line AA in (a).

As shown in FIG. 2, an insulating film 23 made of an oxide film, a conductive film 25 made of conductive polysilicon, a nitride film 44, and an oxide film 46 are deposited on the semiconductor substrate 16 in this order. Thereafter, the oxide film 46 is patterned by the RIE method using a resist mask (not shown) formed by a photolithography process. Here, in the memory cell unit 10, the insulating film 23 is used as a tunnel insulating film. Moreover, each film thickness of the insulating film 23 and the electrically conductive film 25 is respectively about 7-9 nanometer (here 8 nanometer) and about 150 nanometer, respectively.

Next, after removing the resist mask, the nitride film 44, the conductive film 25, the insulating film 23, and the semiconductor substrate 16 are sequentially etched by the RIE method using the previously processed oxide film 46 as a mask. The memory cell element isolation trenches 48 and the dummy cell element isolation trenches 49 having different pattern widths are formed in 16.

Here, the pattern width of the oxide film 46 in the memory cell portion 10 and the dummy cell portion 14 is about 55 nanometers, for example, while the pattern width of the oxide film 46 in the well contact portion 12 is about 180 nanometers, for example. It is. The pattern width of the memory cell element isolation groove 48 of the memory cell unit 10 is, for example, around 55 nanometers, while the pattern width of the dummy cell element isolation groove 49 of the dummy cell unit 14 is, for example, as it goes to the well contact unit 12 It is about 60 nanometers, about 90 nanometers, and about 120 nanometers. The depth of the memory cell element isolation groove 48 and the dummy cell element isolation groove 49 from the semiconductor substrate surface is, for example, about 200 nanometers.

  Next, as shown in FIG. 3, for example, an oxide film is formed so as to fill the memory cell element isolation trench 48 and the dummy cell element isolation trench 49 and further cover the surface of the nitride film 44, and then, for example, CMP (Chemical Mechanical Polishing) ) Method, the surface of the semiconductor memory device in this state covered with the oxide film is flattened and etched to the top of the nitride film 44 on the conductive film 25. Thereafter, the memory cell element isolation groove 48 and the dummy cell element isolation film 51 made of an oxide film embedded in the memory cell element isolation groove 48 and the dummy cell element isolation groove 49, respectively, by the RIE method using the nitride film 44 as a mask. Is etched back so as to be positioned on substantially the same plane as the upper end of the conductive film 25.

In the embodiment of FIG. 2, the oxide film 46 is used as a processing mask for the nitride film 44, but a resist film may be used as a processing mask instead of the oxide film 46.

Next, as shown in FIG. 4, a resist mask 52 is formed so as to cover the surfaces of the nitride film 44 of the dummy cell part 14 and the well contact part 12 and the dummy cell element isolation film 51 of the dummy cell part 14. Using this resist mask 52, the memory cell element isolation film 50 embedded in the memory cell element isolation trench 48 of the memory cell portion 10 is transferred from the back surface of the semiconductor substrate 16 to the upper end portion of the memory cell element isolation film 50 by RIE. Etchback is performed so that the distance between the back surface of the semiconductor substrate 16 and the upper end portion of the conductive film 25 of the memory cell portion 10 is shorter than the distance between the back surface of the semiconductor substrate 16 and the upper surface of the conductive film 25.

At this time, in the dummy cell portion 14 covered with the resist mask 52, the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49 is not etched. As a result, the memory cell of the memory cell portion 10 is exposed from the back surface of the semiconductor substrate 16. The distance to the upper end portion of the element isolation film 50 is configured to be shorter than the distance from the back surface of the semiconductor substrate 16 to the upper end portion of the dummy cell element isolation film 51 of the dummy cell portion 14. The memory cell element isolation region 18 and the dummy cell element isolation region 40 formed as described above are generally called element isolation regions having an STI (Shallow Trench Isolation) structure.

  After removing the resist mask 52 and the nitride film 44, as shown in FIG. 5, for example, an oxide film, a nitride film, or the like is formed so as to cover the surfaces of the conductive film 25, the memory cell element isolation region 18, and the dummy cell element isolation region 40. Oxide films are deposited in this order, for example, with a thickness of 5 nm, 8 nm, and 5 nm, respectively. In FIG. 5, an inter-gate insulating film 26 is a film (ONO film) in which these oxide films, nitride films, and oxide films are stacked.

Next, as shown in FIG. 6, conductive polysilicon 28 having a thickness of about 100 nanometers and a gate wiring 30 having a thickness of about 100 nanometers doped with impurities so as to cover the surface of the intergate insulating film 26 are formed. Deposited in this order. The gate wiring 30 is formed using, for example, WSi.

Here, the conductive film 25 previously shown in FIG. 5 has the following final form in each of the memory cell portion 10, the well contact portion 12, and the dummy cell portion 14. That is, the conductive film 25 of the memory cell unit 10 becomes the floating gate electrode 24. Further, the conductive film 25 of the well contact portion 12 becomes a well contact portion dummy electrode 36 that is not used for the memory operation. Further, the conductive film 25 of the dummy cell portion 14 becomes a dummy cell portion dummy electrode 42 that is not used for the memory operation. The insulating film 23 is made of, for example, an oxide film 22 and is used as a tunnel oxide film particularly in the memory cell unit 10.

Here, in the dummy cell portion 14, the upper end portion of the dummy cell portion dummy electrode 42 and the upper end portion of the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49 are formed on substantially the same plane. As a result, both the conductive polysilicon 28 and the gate wiring 30 formed thereon have a substantially flat film structure.

However, in the dummy cell portion 14, the upper end portion of the dummy cell portion dummy electrode 42 needs to be formed so as to be completely flush with the upper end portion of the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49. Not necessarily. That is, it is only necessary that the step is reduced to such an extent that the film thickness of the gate wiring 30 is almost uniform.

Thereafter, according to the normal manufacturing process of the semiconductor memory device, if the control gate electrode 31 made of the gate wiring 30 and the conductive polysilicon 28 is processed as a word line, the semiconductor memory device in the state shown in FIG. It becomes.

In the semiconductor memory device and the manufacturing method thereof according to the first embodiment configured as described above, in the dummy cell portion 14, the upper end portion of the dummy cell element dummy electrode 42 and the upper end portion of the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49 are used. The part is formed so as to be located on substantially the same plane. As a result, both the conductive polysilicon 28 and the gate wiring 30 formed thereon have a substantially flat film structure, and no processing residue is generated between adjacent word lines when these are processed as word lines. .

In the memory cell portion 10, conductive polysilicon is also disposed on the side wall portion of the floating gate electrode 24 via the inter-gate insulating film 26, so that the side wall portion of the floating gate electrode 24 is also controlled with the floating gate electrode 24. It can be used as a coupling capacitance component between the gate electrode 31 and the gate electrode 31.

Therefore, according to the first embodiment of the present invention, it is possible to provide a semiconductor memory device and a method for manufacturing the same that can suppress electrical short-circuit defects that are likely to occur between adjacent word lines and can achieve high yield and high reliability.

Second Embodiment A semiconductor memory device and a manufacturing method thereof according to the present invention will be described with reference to FIGS.

In each drawing of the second embodiment, parts corresponding to those shown in FIGS. 1 to 6 used in the description of the semiconductor memory device of the first embodiment and the manufacturing method thereof are denoted by the same reference numerals and symbols. .

In the first embodiment, the present invention is applied to the well contact portion 12 and its peripheral portion. In the second embodiment, the present invention is applied to the guard ring portion 13 and its peripheral portion.

In the second embodiment, the first active region having the first planar pattern width is the memory cell active region 20 of the memory cell unit 10, and the first element isolation region is provided between the memory cell active regions 20. This is a memory cell element isolation region 18. The second active region having the second planar pattern width is the guard ring active region 35 of the guard ring portion 13. The third active region is located between the first active region (memory cell active region 20) and the second active region (guard ring active region 35), and constitutes a third active region (dummy cell) constituting the dummy cell portion 14. The second element isolation region is a dummy cell element isolation region 40 adjacent to the third active region (dummy cell active region 38).

Here, the memory cell active region 20 includes a channel region of a MOS transistor and a source region 32A and a drain region 32B arranged in a pair in the gate length direction with the channel region therebetween. The first insulating film and the second insulating film are formed of floating gates such as an oxide film 22 (which functions as a tunnel oxide film in the memory cell unit 10) and an ONO (Oxide-Nitride-Oxide) film, respectively, and a control gate. An inter-gate insulating film 26 between them.

7A and 7B are diagrams showing the main part of the memory cell array of the semiconductor memory device according to the second embodiment of the present invention, where FIG. 7A is a plan view thereof, and FIG. 7B is along the line AA of FIG. It is sectional drawing.

As shown in FIG. 7, the semiconductor memory device includes a memory cell unit 10 for storing data, a guard ring unit 13 for reducing variations in pattern dimensions at the end of the memory cell array, a memory cell unit 10 and a guard ring unit. 13 and a dummy cell portion 14 that is not used as a memory cell.

The memory cell unit 10 includes a memory cell active region 20 and a memory cell element isolation region 18 having a fine planar pattern width. The guard ring portion 13 has a guard ring active region 35 having a wider planar pattern width than the memory cell active region 20.

In the dummy cell section 14, as described below, the planar pattern widths of the dummy cell active region 38 and the dummy cell element isolation region 40 partitioning the dummy cell active region 38 are optimized. That is, in the dummy cell portion 14, the pattern resolution of the photolithography process is not lowered between the memory cell portion 10 and the guard ring portion 13 that disturbs the periodicity of the periodic plane pattern of the memory cell portion 10. The plane pattern width is adjusted.

The dummy cell portion 14 is provided with a portion where the planar pattern width of the dummy cell element isolation region 40 is wider than the planar pattern width of the memory cell element isolation region 18.

The memory cell unit 10 includes a floating gate electrode 24 formed on the surface of a memory cell active region 20 separated by a memory cell element isolation region 18 on a semiconductor substrate 16 via an oxide film 22. Here, the oxide film 22 functions as a tunnel oxide film in the memory cell unit 10. Further, the memory cell unit 10 includes conductive polysilicon 28 and a gate wiring 30 which are sequentially formed on the floating gate electrode 24 via an inter-gate insulating film 26 such as an ONO film. The control gate electrode 31 is composed of a laminated film of the conductive polysilicon 28 and the gate wiring 30. Further, the gate wiring 30 is formed using, for example, WSi.

Here, the memory cell element isolation region 18 is formed by embedding a memory cell element isolation film 50 such as an oxide film in the memory cell element isolation trench 48. The distance from the back surface of the semiconductor substrate 16 to the upper end portion of the memory cell element isolation film 50 embedded in the memory cell element isolation trench 48 is shorter than the distance from the back surface of the semiconductor substrate 16 to the upper end portion of the floating gate electrode 24. It is configured. Further, the intergate insulating film 26 provided on the floating gate electrode 24 is provided so as to be in contact with the side wall of the floating gate electrode 24, and at the same time, the conductive polysilicon 28 provided on the intergate insulating film 26 is adjacent. It is formed so as to be buried between the two floating gate electrodes 24, that is, also on the memory cell element isolation region 18.

As a result, in the memory cell 32 (described in FIG. 7A) in the memory cell unit 10, since the opposing area increases between the floating gate electrode 24 and the control gate electrode 31, a larger coupling between both gates. Capacity can be obtained.

Here, the memory cells 32 shown in FIG. 7A are paired in the gate length direction with a channel region (below the control gate electrode 31 in the memory active region 20) provided on the surface of the semiconductor substrate 16 interposed therebetween. A memory cell active region 20 having a source region 32A and a drain region 32B. Further, the memory cell 32 is formed on the memory cell active region 20 via an oxide film 22 and on the floating gate electrode 24 via an inter-gate insulating film 26 such as an ONO film. The memory cell transistor has a control gate electrode 31.

The guard ring portion 13 includes a guard ring active region 35 that is separated by the dummy cell element isolation region 40 and the guard ring element isolation region 41 on the semiconductor substrate 16 and has a wider planar pattern width than the memory cell active region 20. Yes. Further, the guard ring portion 13 includes a guard ring portion dummy electrode 37 formed on the guard ring active region 35 via the oxide film 22, and an inter-gate insulating film 26 such as an ONO film on the guard ring portion dummy electrode 37. The control gate electrode 31 formed via the is passing therethrough. The guard ring portion dummy electrode 37 is not used for the memory operation.

The dummy cell unit 14 includes a plurality of dummy cell active regions 38 that are located between the guard ring unit 13 and the memory cell unit 10 and have different plane pattern widths. Further, the dummy cell portion 14 has a cross-sectional structure similar to that of the memory cell portion 10 on the dummy cell active region 38. The dummy cell section 14 includes dummy cell element isolation regions 40 (consisting of dummy cell element isolation grooves 49 and dummy cell element isolation films 51 embedded therein) each having a different planar pattern width. Normally, the dummy cell portion 14 is provided with a portion where the planar pattern width of the dummy cell element isolation region 40 is wider than the planar pattern width of the memory cell element isolation region 18 of the memory cell portion 10.

Here, in the dummy cell portion 14, the upper end portion of the dummy cell portion dummy electrode 42 is formed so as to be substantially flush with the upper end portion of the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49. Therefore, the intergate insulating film 26 formed so as to cover both surfaces of the dummy cell element isolation region 40 and the dummy cell portion dummy electrode 42 has a substantially flat film structure. Furthermore, the conductive polysilicon 28 and the gate wiring 30 sequentially provided on the substantially flat inter-gate insulating film 26 also have a substantially flat film structure as a result.

However, in the dummy cell portion 14, the upper end portion of the dummy cell portion dummy electrode 42 needs to be formed so as to be completely flush with the upper end portion of the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49. Not necessarily. It is only necessary that the step is reduced to such an extent that the film thickness of the gate wiring 30 (for example, WSi) becomes substantially uniform.

Next, a method for manufacturing the semiconductor memory device of Example 2 will be described. 8 to 12 are diagrams for explaining the steps of the manufacturing method and correspond to FIG. 7 described above. In each drawing, (a) is a plan view showing the state of the main part of the semiconductor memory device in each step, and (b) is a cross-sectional view taken along line AA in (a).

As shown in FIG. 8, an insulating film 23 made of an oxide film, a conductive film 25 made of conductive polysilicon, a nitride film 44, and an oxide film 46 are deposited on the semiconductor substrate 16 in this order. Thereafter, the oxide film 46 is processed by the RIE method using a resist mask (not shown) formed by a photolithography process. Here, the insulating film 23 is used as a tunnel insulating film in the memory cell unit 10. Moreover, each film thickness of the insulating film 23 and the electrically conductive film 25 is respectively about 7-9 nanometer (here 8 nanometer) and about 150 nanometer, respectively.

Next, after removing the resist mask, the nitride film 44, the conductive film 25, the insulating film 23, and the semiconductor substrate 16 are sequentially etched by the RIE method using the previously processed oxide film 46 as a mask. A memory cell element isolation groove 48, a dummy cell element isolation groove 49, and a guard ring element isolation groove 53 having different pattern widths are formed therein.

Here, the pattern width of the oxide film 46 in the memory cell portion 10 and the dummy cell portion 14 is about 55 nanometers, for example, while the pattern width of the oxide film 46 in the guard ring portion 13 is about 500 nanometers, for example. is there. The pattern width of the memory cell element isolation groove 48 of the memory cell unit 10 is, for example, around 55 nanometers, while the pattern width of the dummy cell element isolation groove 49 of the dummy cell unit 14 is about, for example, approximately toward the guard ring unit 13. It is about 60 nanometers, about 90 nanometers, and about 120 nanometers. The depth of the memory cell element isolation groove 48, the dummy cell element isolation groove 49, and the guard ring element isolation groove 53 from the semiconductor substrate surface is, for example, about 200 nanometers.

  Next, as shown in FIG. 9, for example, an oxide film is formed so as to fill the memory cell element isolation groove 48, the dummy cell element isolation groove 49, and the guard ring element isolation groove 53 and further cover the surface of the nitride film 44. Thereafter, the surface of the semiconductor memory device in this state covered with an oxide film is flattened by, for example, a CMP method, and etched to the top of the nitride film 44 on the conductive film 25. Thereafter, the memory cell element isolation groove 48, the dummy cell element isolation groove 49, and the guard ring element isolation groove 53 respectively embedded in the memory cell element isolation groove 48 and the dummy cell element isolation film 51 by the RIE method using the nitride film 44 as a mask. Then, the guard ring element isolation film 54 is etched back so that the upper end portion thereof is positioned substantially on the same plane as the upper end portion of the conductive film 25.

Next, as shown in FIG. 10, the resist mask 52 covers the surfaces of the dummy cell portion 14, the nitride film 44 of the guard ring portion 13, the dummy cell element isolation film 51 of the dummy cell portion 14, and the guard ring element isolation film 54. Form. Using this resist mask 52, the memory cell element isolation film 50 embedded in the memory cell element isolation trench 48 of the memory cell portion 10 is transferred from the back surface of the semiconductor substrate 16 to the upper end portion of the memory cell element isolation film 50 by RIE. Etchback is performed so that the distance is shorter than the distance from the back surface of the semiconductor substrate 16 to the upper end of the floating gate electrode 24.

At this time, in the dummy cell portion 14 and the guard ring portion 13 covered with the resist mask 52, the dummy cell element isolation film 49 and the guard ring element isolation film embedded in the dummy cell element isolation groove 49 and the guard ring element isolation groove 53, respectively. As a result, the distance from the back surface of the semiconductor substrate 16 to the upper end portion of the memory cell element isolation film 50 embedded in the memory cell element isolation groove 48 of the memory cell unit 10 is The dummy cell element 14 and the guard ring element 13 have a dummy cell element isolation groove 49, a dummy cell element isolation film 51 embedded in the guard ring element isolation groove 53, and a distance shorter than the upper end of the guard ring element isolation film 54. Is done.

In addition, the memory cell element isolation region 18, the dummy cell element isolation region 40, and the guard ring element isolation region 41 formed as described above are generally referred to as an element isolation region having an STI (Shallow Trench Isolation) structure.

  After removing the resist mask 52 and the nitride film 44, as shown in FIG. 11, the conductive film 25 made of conductive polysilicon, the memory cell element isolation region 18, the dummy cell element isolation region 40, and the guard ring element isolation region 41. For example, an oxide film, a nitride film, and an oxide film are deposited in this order in thicknesses of 5 nm, 8 nm, and 5 nm, respectively. In FIG. 11, an inter-gate insulating film 26 is a film (ONO film) in which these oxide films, nitride films, and oxide films are stacked.

Next, as shown in FIG. 12, conductive polysilicon 28 having a thickness of about 100 nanometers doped with impurities so as to cover the surface of the inter-gate insulating film 26 and a gate wiring 30 having a thickness of about 100 nanometers ( For example, here WSi) is deposited in this order. The gate wiring 30 is formed using, for example, WSi.

Here, the conductive film 25 previously shown in FIG. 11 has the following final form in each of the memory cell portion 10, the guard ring portion 13, and the dummy cell portion 14. That is, the conductive film 25 of the memory cell unit 10 becomes the floating gate electrode 24. Further, the conductive film 25 of the guard ring portion 13 serves as a guard ring portion dummy electrode 37 that is not used for the memory operation. Further, the conductive film 25 of the dummy cell portion 14 becomes a dummy cell portion dummy electrode 42 that is not used for the memory operation. The insulating film 23 is made of, for example, an oxide film 22 and is used as a tunnel oxide film particularly in the memory cell unit 10.

Here, in the dummy cell portion 14 and the guard ring portion 13, dummy cells embedded in the dummy cell portion dummy electrode 42, the upper end portions of the guard ring portion dummy electrode 37, the dummy cell element isolation groove 49, and the guard ring element isolation groove 53, respectively. The element isolation film 51 and the guard ring element isolation film 54 are formed so as to be positioned on substantially the same plane. As a result, both the conductive polysilicon 28 and the gate wiring 30 formed thereon have a substantially flat film structure.

However, in the dummy cell portion 14, the upper end portion of the dummy cell portion dummy electrode 42 needs to be formed so as to be completely flush with the upper end portion of the dummy cell element isolation film 51 embedded in the dummy cell element isolation groove 49. Not necessarily. It is only necessary that the step is reduced to such an extent that the film thickness of the gate wiring 30 is almost uniform.

Thereafter, if the control gate electrode 31 formed of the laminated film of the gate wiring 30 and the conductive polysilicon 28 is processed as a word line in accordance with the normal manufacturing process of the semiconductor memory device, the state shown in FIG. A semiconductor memory device is obtained.

In the semiconductor memory device and the manufacturing method thereof according to the second embodiment configured as described above, in the dummy cell portion 14 and the guard ring portion 13, each upper end portion of the dummy cell portion dummy electrode 42 and the guard ring portion dummy electrode 37 and the dummy cell element. The isolation groove 49 and the dummy cell element isolation film 51 embedded in each of the guard ring element isolation grooves 53 and the upper end portion of the guard ring element isolation film 54 are formed so as to be located on substantially the same plane. As a result, both the conductive polysilicon 28 and the gate wiring 30 formed thereon have a substantially flat film structure, and no processing residue is generated between adjacent word lines when these are processed as word lines. .

In the memory cell portion 10, conductive polysilicon is also disposed on the side wall portion of the floating gate electrode 24 via the inter-gate insulating film 26, so that the side wall portion of the floating gate electrode 24 is also controlled with the floating gate electrode 24. It can be used as a coupling capacitance component between the gate electrode 31 and the gate electrode 31.

Therefore, according to this embodiment, it is possible to suppress an electrical short-circuit failure that is likely to occur between adjacent word lines, and to realize a semiconductor memory device having a high yield and high reliability and a method for manufacturing the same.

  The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. In the above-described embodiments, the case where the word lines are provided on a plurality of active regions having different widths has been described. However, the present invention is not limited to such a case, and the present invention can also be applied when forming other wirings such as bit lines. Can do.

Further, for example, in the first and second embodiments, the nonvolatile semiconductor memory device having the floating gate electrode and the manufacturing method thereof have been described. However, the present invention is also applied to a volatile semiconductor memory device such as a DRAM. Is possible. In that case, the tunnel oxide film and the floating gate electrode used in the first and second embodiments may be replaced with a gate insulating film and a gate electrode normally used in a DRAM.

  In the first and second embodiments, when the element isolation region having the STI structure is formed in the dummy cell portion in the memory cell array, the element isolation region of the peripheral circuit transistor can be formed in the same process. Thereby, the number of manufacturing processes of the semiconductor memory device can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the principal part of the memory cell array of the semiconductor memory device which is Example 1 of this invention, (a) is the top view, (b) is sectional drawing along line AA of (a). . 2A and 2B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 1, in which FIG. 2A and 2B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 1, in which FIG. 2A and 2B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 1, in which FIG. 2A and 2B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 1, in which FIG. 2A and 2B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 1, in which FIG. 4A and 4B are diagrams showing a main part of a memory cell array of a semiconductor memory device that is Embodiment 2 of the present invention, where FIG. 5A is a plan view thereof, and FIG. . 8A and 8B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 7, in which FIG. 8A and 8B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 7, in which FIG. 8A and 8B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 7, in which FIG. 8A and 8B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 7, in which FIG. 8A and 8B are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. 7, in which FIG.

Explanation of symbols

10 memory cell portion 12 well contact portion 14 dummy cell portion 16 semiconductor substrate 18 memory cell element isolation region 20 memory cell active region 22 oxide film 23 insulating film 24 floating gate electrode 25 conductive film 26 intergate insulating film 28 conductive polysilicon 30 gate Wiring 31 Control gate electrode 32 Memory cell 32A Source region 32B Drain region 34 Well contact active region 36 Well contact part dummy electrode 38 Dummy cell active region 40 Dummy cell element isolation region 42 Dummy cell part dummy electrode 48 Memory cell element isolation groove 49 Dummy cell element isolation groove 50 Memory cell element isolation film 51 Dummy cell element isolation film

Claims (5)

A semiconductor substrate;
A first active region having a first planar pattern width provided on the surface side of the semiconductor substrate;
A second active region provided on the surface side of the semiconductor substrate and spaced apart from the first active region and having a second planar pattern width wider than the first planar pattern width;
A third active region provided between the first active region and the second active region on the surface side of the semiconductor substrate and having a third planar pattern width;
A first gate electrode formed on the first active region via a first insulating film;
A second gate electrode formed on the second active region via a first insulating film;
A third gate electrode formed on the third active region via a first insulating film;
A first element isolation region provided between the first active regions and having an upper end;
A second element isolation region provided adjacent to the third active region and having an upper end;
A second insulating film provided on the first gate electrode, on the second gate electrode, on the third gate electrode, and on the second element isolation region;
The upper end portions of the first gate electrode, the second gate electrode, and the third gate electrode and the upper end portion of the second element isolation region are positioned on the same plane, and the first gate electrode, the second gate electrode, and the third gate electrode A semiconductor memory device, wherein a distance to an upper end portion of one element isolation region is shorter than a distance from a back surface of the semiconductor substrate to an upper end portion of the second element isolation region.   2. The semiconductor memory device according to claim 1, wherein the first and second element isolation regions have an STI structure. The first active region is a memory cell active region, the second active region is either a well contact active region or a guard ring active region, and the third active region is a dummy cell active region. The semiconductor memory device according to claim 2, wherein: Forming a first insulating film on the surface of the semiconductor substrate;
Forming a gate electrode layer on the first insulating film;
Forming a second insulating film on the gate electrode layer;
Patterning the second insulating film;
Using the patterned second insulating film as a mask, the gate electrode layer, the first insulating film, and a part of the semiconductor substrate are removed and adjacent to the first active planned region having the first planar pattern width Forming a first element isolation region groove and a second element isolation region groove adjacent to a second active planned region having a second planar pattern width wider than the first planar pattern width;
Embedding an insulator inside the first and second element isolation region trenches;
The insulator embedded in the first and second element isolation region grooves is partially removed, and the insulator embedded in the first and second element isolation region grooves, respectively. Forming a height from the back surface of the semiconductor substrate to be the same as a height from the back surface of the semiconductor substrate of the upper end portion of the gate electrode layer;
The insulator embedded in the first element isolation region trench is further removed, and the height of the upper end portion of the insulator embedded in the first element isolation region trench from the back surface of the semiconductor substrate is determined. And a step of forming the gate electrode so as to be positioned between the upper end portion of the gate electrode and the upper end portion of the first insulating film. The first insulating film is a first silicon oxide film, the gate electrode layer is a floating gate electrode layer, and the second insulating film is a silicon nitride film, or a silicon nitride film and a second silicon oxide film And the first active planned region is a memory cell active planned region, and the second active planned region is a dummy cell active planned region,
And forming an inter-gate insulating film on the first element isolation region trench, on the floating gate electrode layer, and on the second element isolation region trench;
The method of manufacturing a semiconductor memory device according to claim 4, further comprising: forming a control gate electrode layer on the inter-gate insulating film.

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