CN109216347B - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Download PDF

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Publication number
CN109216347B
CN109216347B CN201810516388.9A CN201810516388A CN109216347B CN 109216347 B CN109216347 B CN 109216347B CN 201810516388 A CN201810516388 A CN 201810516388A CN 109216347 B CN109216347 B CN 109216347B
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active region
region
dummy
guard
semiconductor device
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CN109216347A (en
Inventor
朴志勋
申重植
李秉一
禹钟昊
郑恩宅
车俊昊
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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Abstract

A semiconductor device includes: a substrate having a first region including a memory cell and a second region including a transistor for driving the memory cell; and a device isolation region disposed within the substrate to define an active region of the substrate. The active region includes a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
Technical Field
The present inventive concept relates to semiconductor devices.
Background
With the increasing demand for high performance, high speed, and/or multi-functionality in electronic devices, the integration of semiconductor devices in electronic devices is increasing. With the trend of high integration of semiconductor devices, the patterns forming the semiconductor devices have become compact. Therefore, it is becoming increasingly important to prevent defects in the manufacturing process of semiconductor devices.
Disclosure of Invention
An aspect of the inventive concept may provide a semiconductor device having increased reliability.
According to an aspect of the present disclosure, a semiconductor device may include: a substrate having a first region including a memory cell and a second region including a transistor for driving the memory cell; and a device isolation region disposed within the substrate to define an active region of the substrate, wherein the active region may include: a first guard active region surrounding the first region; a second guard active region surrounding a portion of the second region; and at least one dummy active region disposed between the first guard active region and the second guard active region.
According to an aspect of the present disclosure, a semiconductor device may include: a substrate having a first region including a cell active region having a memory cell disposed therein and a second region disposed at least one side of the first region, wherein the second region may include at least one dummy active region extending in one direction along a boundary between the first region and the second region.
According to an aspect of the present disclosure, a semiconductor device may include: a gate electrode structure including gate electrodes spaced apart from each other and stacked on the substrate in a first direction perpendicular to the substrate, and extending in a second direction perpendicular to the first direction to have different lengths; a guard active region disposed within the substrate to surround the gate electrode structure; and at least one dummy active region disposed on at least one side of the guard active region in the second direction, the at least one dummy active region being disposed within the substrate to extend parallel to the guard active region.
Drawings
The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Fig. 1 is a schematic block diagram of a semiconductor device according to an example embodiment;
fig. 2 is a schematic layout diagram of a semiconductor device according to an example embodiment;
fig. 3 is a schematic layout of a semiconductor device according to an example embodiment;
FIG. 4 is a schematic cross-sectional view taken along line IV-IV' of FIG. 3;
fig. 5 is a schematic layout diagram of a semiconductor device according to an example embodiment;
FIG. 6 is a schematic cross-sectional view taken along line VI-VI' of FIG. 5;
fig. 7 and 8 are schematic layout diagrams of a semiconductor device according to example embodiments; and
fig. 9A to 9I are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.
In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. Although the various figures show variations of the exemplary embodiments and may involve the use of languages such as "in one embodiment," the figures are not necessarily intended to be mutually exclusive of each other. Rather, as will be seen from the context of the following detailed description, certain features depicted and described in different figures may be combined with other features from other figures to produce various embodiments when the figures and their descriptions are considered as a whole.
Detailed Description
Fig. 1 is a schematic block diagram of a semiconductor device according to an example embodiment.
Referring to fig. 1, a semiconductor device 10 may include a memory cell array 20 and control logic 30. The semiconductor device 10 may be in the form of a semiconductor chip or die formed, for example, from a semiconductor wafer. The term "semiconductor device" as used herein may also refer to a semiconductor package that includes a package substrate, one or more semiconductor chips, and an encapsulant.
The memory cell array 20 may include a plurality of memory blocks, and each memory block may include a plurality of memory cells. The memory cells may be connected to the row decoder 32 via a string selection line SSL, a plurality of word lines WL, and a ground selection line GSL, and may be connected to the page buffer 34 via a bit line BL. In example embodiments, a plurality of memory cells arranged in a row may be connected to a single word line WL, and a plurality of memory cells arranged in a column may be connected to a single bit line BL.
Control logic 30 may include a row decoder 32, a page buffer 34, and control circuitry 36.
The row decoder 32 may decode the input address to generate and transmit a driving signal for the word line WL. The row decoder 32 may supply the word line voltages generated by the voltage generating circuits in the control circuit 36 to the selected word line WL and the unselected word line WL, respectively, in response to control of the control circuit 36.
The page buffer 34 may be connected to the memory cell array 20 via the bit line BL to read information stored in the memory cells. The page buffer 34 may temporarily store data to be stored in the memory cell according to an operation mode, or may sense data stored in the memory cell. The page buffer 34 may include a column decoder and a sense amplifier. The column decoder may selectively activate the bit lines BL of the memory cell array 20, and the sense amplifier may sense the voltages of the bit lines BL selected by the column decoder during a read operation to read data stored in the selected memory cells.
Control circuitry 36 may control the operation of row decoder 32 and page buffer 34. The control circuit 36 may receive an external control signal and an external voltage and may operate in response to the received control signal. The control circuit 36 may include a voltage generation circuit that generates voltages (e.g., program voltage, read voltage, erase voltage, etc.) required for internal operations using external voltages. Control circuitry 36 may control read, write, and/or erase operations in response to control signals. Further, the control circuit 36 may include input/output (I/O) circuitry. The I/O circuit may receive DATA and transmit the DATA to the page buffer 34 in a program operation, and may output the DATA received from the page buffer 34 to the outside in a read operation.
Fig. 2 is a schematic layout diagram of a semiconductor device according to an example embodiment.
Referring to fig. 2, the semiconductor device 10 may include a memory CELL region CELL, and a row decoder region DEC, a page buffer region PB, and other circuit regions PERI forming peripheral circuit regions.
The memory CELL region CELL may be a region in which the memory CELL array 20 described above with reference to fig. 1 is disposed. The row decoder area DEC may have the row decoder 32 of fig. 1 disposed therein. The page buffer region PB may have the page buffer 34 of fig. 1 disposed therein. The other circuit area PERI may have other circuitry disposed therein, including the control circuit 36 of fig. 1. The arrangement relation of the respective areas shown in fig. 2 is provided by way of example only, but the arrangement of the respective areas is not limited thereto.
According to some embodiments, the row decoder area DEC may be disposed at least one side of the memory CELL area CELL in one direction thereof (e.g., x-direction). The page buffer region PB may be disposed on at least one side of the memory CELL region CELL in one direction thereof (for example, in the y direction). Accordingly, the word line WL (refer to fig. 1) may extend from the memory CELL region CELL toward the row decoder region DEC in the x-direction, and the bit line BL (refer to fig. 1) may extend from the memory CELL region CELL toward the page buffer region PB in the y-direction.
Other circuit areas PERI may be disposed in the vicinity of the memory CELL area CELL, the row decoder area DEC, and the page buffer area PB, and I/O circuits, high voltage generation circuits, circuits for testing, and the like may be disposed in the other circuit areas PERI.
Fig. 3 is a schematic layout diagram of a semiconductor device according to an example embodiment. Fig. 3 is an enlarged view of the area "a" of fig. 2. Fig. 4 is a schematic cross-sectional view taken along line IV-IV' of fig. 3.
Referring to fig. 3 and 4, the semiconductor device 100 may include: a substrate 101 having a memory CELL region CELL as a first region and a peripheral circuit region CKT as a second region; and a device isolation region 120 disposed within the substrate 101 in the peripheral circuit region CKT to define an active region of the substrate 101. The memory CELL region CELL may be the same region as the memory CELL region CELL shown in fig. 2, and the peripheral circuit region CKT may be a region including the row decoder region DEC, the page buffer region PB, and the other circuit region PERI shown in fig. 2. The memory CELL area CELL includes memory CELLs each configured to store one or more bits of data. The memory CELLs in the memory CELL region CELL are used to read and write data to the semiconductor device 100 by storing data, and are configured to be accessed by one or more portions of other circuit regions PERI, thereby transmitting data to or from an external device, such as an external controller or host outside the semiconductor device 100. Each memory cell may include an active region and a memory element and a gate for accessing the memory cell. Fig. 3 and 4 show regions including boundaries between the memory CELL region CELL and the peripheral circuit region CKT on corners of the memory CELL region CELL (e.g., at edge regions of the memory CELL region CELL) (e.g., as viewed from a top view). For convenience of description, the boundary between the memory CELL region CELL and the peripheral circuit region CKT may be defined by the boundary of the CELL active region CACT (e.g., the boundary beyond which the memory CELLs of the memory CELL region are no longer disposed).
The active regions of the semiconductor device 100 may include a CELL active region CACT disposed in the memory CELL region CELL, first and second guard active regions GB1 and GB2 disposed in the peripheral circuit region CKT, first to third dummy active regions DM1 to DM3 and a circuit active region PACT, and first to third active regions 110a, 110b, and 110c. For example, as shown in fig. 4, each of these active areas may be located at the same vertical height. In this specification, the term "dummy" is used to refer to a component within a semiconductor device that appears as a pattern having the same or similar structure and shape as other components without actual function. For example, the dummy active region may not be connected to any gate or bit line for communication within the semiconductor device 100, or the dummy active region may be connected to a dummy gate or dummy bit line in such a way that data related to the active region is ignored by peripheral circuitry of the semiconductor device 100, or is not transmitted to or from devices external to the semiconductor device 100, or is ignored by such external devices. Thus, the dummy components as described herein are not used to transfer data for a logic operation or a storage operation. Fig. 3 and 4 show only the configuration of the substrate 101 of the semiconductor device 100.
The substrate 101 may have an upper surface extending in x-axis and y-axis directions. The substrate 101 may include a semiconductor material, such as a group IV semiconductor material, a group III-V compound semiconductor material, or a group II-VI oxide semiconductor material. For example, the group IV semiconductor material may include silicon, germanium, or silicon germanium. The substrate 101 may be a bulk wafer or an epitaxial layer.
The device isolation regions 120 may be formed of an insulating material. The device isolation regions 120 may be formed of, for example, oxide, nitride, or a combination thereof. The device isolation regions 120 may be formed using, for example, a Shallow Trench Isolation (STI) process.
The CELL active area CACT may extend to the entirety of the memory CELL area CELL as shown in fig. 2, and the memory CELL area CELL may be formed as a single CELL active area CACT. In one embodiment, the cell active area CACT is defined by the boundary of a first well (e.g., PW) formed at the bottom of the cell active area. The circuit active area PACT may be an active area of the peripheral circuit area CKT to form a transistor.
The first guard active region GB1 and the second guard active region GB2 may be disposed outside the memory CELL region CELL in one direction (e.g., the x-direction). The first guard active region GB1 may surround the memory CELL region CELL, and the second guard active region GB2 may surround a portion of the peripheral circuit region CKT. For example, the first guard active region GB1 may be spaced apart from the memory CELL region CELL by a distance toward the peripheral circuit region CKT with respect to the entirety of the memory CELL region CELL having a quadrangular shape to surround the memory CELL region CELL. For example, the second guard active region GB2 may surround all or a portion of the row decoder region DEC. Accordingly, each of the first and second guard active regions GB1 and GB2 may have a quadrangular ring shape. For example, each of the first guard active region GB1 and the second guard active region GB2 may have a quadrangular bar shape surrounding at least a portion of the memory CELL region CELL and the row decoder region DEC. Each of the first guard active region GB1 and the second guard active region GB2 may be referred to as a guard ring. Further, each of the first guard active region GB1 and the second guard active region GB2 may be connected to one or more plugs for connection to a power source (e.g., positive voltage, negative voltage, or ground).
The first guard active region GB1 may be an active region closest to the memory CELL region CELL, except for the first dummy active region DM 1. The second guard active region GB2 may be an active region closest to the first guard active region GB1 in a direction away from the memory CELL region CELL, except for the second dummy active region DM2 and the third dummy active region DM 3. The second guard active region GB2 may surround at least the transistor closest to the memory CELL region CELL in the x-direction (e.g., the transistor of the circuit active region PACT).
As shown in fig. 4, the memory CELL region CELL may include a first well PW including impurities of a first conductivity type, and a second well DNW surrounding the first well PW and including impurities of a second conductivity type. For example, the first conductivity type may be p-type and the second conductivity type may be n-type. The substrate 101 may include an impurity of the first conductivity type, and a concentration thereof may be lower than that of the impurity contained in the first well PW. The second well DNW may include and vertically overlap the first guard active region GB1. In an example embodiment, at least one region of the first guard active region GB1 adjacent to the upper surface of the substrate 101 may include impurities having a higher concentration than impurities included in the lower region of the second well DNW. The peripheral circuit region CKT may include a third well NW containing an impurity of the second conductivity type, and may further include other wells disposed in other regions not shown and containing an impurity of the first conductivity type. The second guard active region GB2 may include impurities having the same conductivity type as the substrate 101. In example embodiments, at least one region of the second guard active region GB2 adjacent to the upper surface of the substrate 101 may include impurities having a higher concentration than impurities included in the lower region of the substrate 101. In the present exemplary embodiment, the first and second guard active regions GB1 and GB2 may include impurities of different conductivity types. However, the inventive concept is not limited thereto.
In an example embodiment, the first well PW may further include a guard active region. The guard active region may be disposed in the memory CELL region CELL, or may be disposed between the first guard active region GB1 and the memory CELL region CELL. In an example embodiment, the guard active region may also be adjacent to another edge region, not shown, of the memory CELL region CELL.
The first to third dummy active regions DM1 to DM3 may have a line shape extending in one direction (e.g., y-direction) and formed on one plane. The first to third dummy active regions DM1 to DM3 may be spaced apart from a boundary between the memory CELL region CELL and the peripheral circuit region CKT (e.g., an outer surface of the CELL active region CACT), and the first to third dummy active regions DM1 to DM3 may extend along the outer surface in at least one direction. The first to third dummy active regions DM1 to DM3 may be spaced apart from each other in the x-direction and may extend parallel to each other in the y-direction.
The first dummy active region DM1 may be disposed between the memory CELL region CELL and the first guard active region GB1 in the x-direction, and the second dummy active region DM2 and the third dummy active region DM3 may be disposed between the first guard active region GB1 and the second guard active region GB2 in the x-direction. As shown in fig. 3, an end of the first dummy active region DM1 may be disposed in a region surrounded by the first guard active region GB 1. However, the inventive concept is not limited thereto. In an example embodiment, the first dummy active region DM1 may also be bent along the first guard active region GB1 to extend in the x-direction under the memory CELL region CELL. The second and third dummy active regions DM2 and DM3 may extend farther than the first dummy active region DM 1. However, the inventive concept is not limited thereto.
The widths W1 of the first to third dummy active regions DM1 to DM3 may range from 500nm to 3 μm, for example, and may be substantially the same as each other. However, the inventive concept is not limited thereto. The distance L1 between the cell active area CACT and the first guard active area GB1 may for example range from 1 μm to 7 μm. The distance L2 between the first guard active region GB1 and the second guard active region GB2 may for example range from 1 μm to 7 μm. In certain embodiments, L2 is greater than L1. The distance L3 between the first dummy active region DM1 and the first guard active region GB1 may be less than 3 μm, and the distance L4 between the third dummy active region DM3 and the second guard active region GB2 may also be less than 3 μm. In the present example embodiment, a first dummy active region DM1 may be disposed between the cell active region CACT and the first guard active region GB1, and a second dummy active region DM2 and a third dummy active region DM3 may be disposed between the first guard active region GB1 and the second guard active region GB2 such that a length of the device isolation region 120 therebetween in the x-direction may be less than 3 μm. In certain embodiments, L1 is greater than L3 and L4. For this reason, in the example embodiment, the number of the first to third dummy active regions DM1 to DM3 may be modified according to the distances L1 and L2 and the width W1. As described above, the arrangement of the first to third dummy active regions DM1 to DM3 can prevent a dishing effect from occurring in the device isolation region 120 during the manufacturing process of the semiconductor device 100 and prevent the edge regions of the first and second guard active regions GB1 and GB2 from being damaged. This will be described in more detail below with reference to fig. 9D.
The first to third active regions 110a to 110c may be disposed around the first guard active region GB1 and the second guard active region GB2 in the peripheral circuit region CKT. The first to third active regions 110a to 110c may also correspond to dummy active regions. The size, shape, and arrangement of the first to third active regions 110a to 110c are not limited to those shown in the drawings, and may be modified according to example embodiments.
Fig. 5 is a schematic layout diagram of a semiconductor device according to an example embodiment. Fig. 5 shows only the main components of the semiconductor device. Fig. 6 is a cross-sectional view taken along line VI-VI' of fig. 5.
Referring to fig. 5 and 6, the semiconductor device 100a may include: a substrate 101 having a memory CELL region CELL as a first region and a peripheral circuit region CKT as a second region; and a device isolation region 120 defining an active region of the substrate 101. Regarding the device isolation region 120 and the active region, the same description as that described above with reference to fig. 3 and 4 may be applied.
In the memory CELL region CELL, the semiconductor device 100a may further include: gate electrodes 131, 132, 133, 134, 135, 136, 137, and 138, collectively represented by gate electrode stack 130, are stacked on substrate 101 to form a gate electrode structure; a channel CH passing through the gate electrode stack 130; a gate contact CT connected to the gate electrode of the gate electrode stack 130; and isolation regions 194 extending through the gate electrode stack 130 in the x-direction.
The gate electrodes 131 to 138 may be disposed along sidewalls of each channel CH and may be spaced apart from each other in one direction perpendicular to the substrate 101. The gate electrode stack 130 may provide a contact region CP extending toward a boundary of the memory CELL region CELL to have different lengths to form a stepped portion having a stepped shape. The gate electrode stack 130 may be connected to the gate contact CT in the contact region CP to be connected to the upper wiring structure. As shown in fig. 6, each gate electrode of the gate electrode stack 130 may have a shape whose thickness increases at an end portion so that the gate electrode of the gate electrode stack 130 may be stably connected to the gate contact CT. However, the inventive concept is not limited thereto.
The gate electrodes 131 to 138 may form gates of a Ground Selection Transistor (GST), a plurality of Memory Cells (MC), and a String Selection Transistor (SST). The gate electrode stack 130 may extend to form WL, SSL, and GSL of fig. 1, and WL may be commonly connected to adjacent memory cell strings arranged in x-direction and y-direction in a predetermined unit. According to an example embodiment, the gate electrodes of the uppermost SST and the lowermost GST may be provided in one or two or more amounts, respectively, and may have the same or different structure from the gate electrode of each MC. A portion of the gate electrode stack 130 (e.g., a gate electrode adjacent to a gate electrode of GST or SST) may be a dummy gate electrode.
The gate electrode of the gate electrode stack 130 may include a metal material, such as tungsten (W). According to an example embodiment, the gate electrode stack 130 may include polysilicon doped with impurities or undoped impurities or metal silicide. In an example embodiment, the gate electrode of the gate electrode stack 130 may further include a diffusion barrier layer.
A plurality of interlayer insulating layers 140 may be disposed between the gate electrodes 131 to 138. The interlayer insulating layers 140 may also be spaced apart from each other in the z-direction and may extend in the x-direction, similar to the gate electrodes of the gate electrode stack 130. The interlayer insulating layer 140 may include an insulating material such as silicon oxide or silicon nitride.
The channels CH may be arranged in rows and columns on the substrate 101 and may be spaced apart from each other. For example, the channels CH may be arranged to form a grid pattern or a zigzag pattern in one direction. The channel CH may have inclined sidewalls that are narrowed toward the substrate 101 according to the aspect ratio of the channel CH. Each channel CH may have a channel region 152 disposed therein. According to an example embodiment, the channel region 152 may have a ring shape surrounding the channel insulating layer 192 therein, and may also have a pillar shape such as a cylinder or a prism without the channel insulating layer 192. The channel region 152 may be connected to the epitaxial layer 107 at a lower portion thereof. Channel region 152 may comprise a semiconductor material such as polysilicon or monocrystalline silicon, and the semiconductor material may not be doped with impurities, or may comprise p-type or n-type impurities. The channels CH arranged on a straight line in the x-direction may be respectively connected to different BLs according to the arrangement of the upper wiring structure connected to the channel pads 158. Further, a portion of the channel CH may be a dummy channel that is not connected to the BL.
A first gate dielectric layer 154 and a second gate dielectric layer 156 may be disposed between each gate electrode of the gate electrode stack 130 and the channel region 152. Each of the first gate dielectric layer 154 and the second gate dielectric layer 156 may include at least one of a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel region 152. The first gate dielectric layer 154 may extend perpendicular to the substrate 101, as in the channel region 152, and the second gate dielectric layer 156 may surround each gate electrode of the gate electrode stack 130. For example, the first gate dielectric layer 154 may include a tunneling layer and a charge storage layer, and the second gate dielectric layer 156 may include at least a portion of a blocking layer. However, the first gate dielectric layer 154 and the second gate dielectric layer 156 may be modified according to example embodiments. Further, in example embodiments, the first gate dielectric layer 154 may include all of a tunneling layer, a charge storage layer, and a blocking layer. Here, the second gate dielectric layer 156 may be omitted.
The epitaxial layer 107 may be disposed on the substrate 101 on a lower end of each channel CH, and may be disposed on a side surface of at least one of the gate electrodes 131 to 138. The epitaxial layer 107 may be formed in a recessed region of the substrate 101. The upper surface of the epitaxial layer 107 may be higher than the upper surface of the lowermost gate electrode 131 and may be lower than the lower surface of the gate electrode 132 disposed over the lowermost gate electrode 131. However, the epitaxial layer 107 is not limited to the epitaxial layer shown in fig. 6. Even when the aspect ratio of the channel CH increases, the channel region 152 can be stably electrically connected to the substrate 101 through the epitaxial layer 107, and characteristics of GST between memory cell strings can be uniform through the epitaxial layer 107. In an example embodiment, the epitaxial layer 107 may be omitted. Here, the channel region 152 may be directly connected to the substrate 101.
Each channel pad 158 may be disposed on the channel region 152 in each channel CH. Each channel pad 158 may cover an upper surface of the channel insulating layer 192 and may be electrically connected to the channel region 152. The channel pad 158 may comprise, for example, polysilicon doped with impurities.
As shown in fig. 5, the isolation regions 194 may be disposed between the channels CH at intervals, and may be connected to the substrate 101 through the gate electrode stack 130 and the interlayer insulating layer 140. The isolation region 194 may have a line shape extending in the x-direction, and may include a common source line (CLS).
In the peripheral circuit region CKT, the semiconductor device 100a may further include a circuit gate electrode PG disposed on the circuit active region PACT, dummy gate electrodes DG disposed on the first to third dummy active regions DM1 to DM3, first to third gate regions 160a, 160b and 160c disposed on the first to third active regions 110a to 110c, and first to third contact plugs MC1 to MC3 connected to the first and second guard active regions GB1 and GB2 and the circuit active region PACT.
The circuit gate electrode PG may intersect the circuit active region PACT in a region of the substrate 101 surrounded by the second guard active region GB 2. The circuit active area PACT and the circuit gate electrode PG may form a transistor. The transistor may be the transistor of the peripheral circuit region CKT closest to the boundary of the memory CELL region CELL. As shown in fig. 6, the circuit gate electrode PG may include a gate stack structure 160, and the gate stack structure 160 includes a circuit gate insulating layer 162 and first to third circuit electrode layers 164 to 168 sequentially stacked on the substrate 101.
The circuit gate insulating layer 162 may include an insulating material such as silicon dioxide (SiO 2 ). The first to third circuit electrode layers 164 to 168 may be formed of a conductive material, may be formed of different materials, or may be formed using different processes. For example, the first circuit electrode layer 164 and the second circuit electrode layer 166 may be formed of polysilicon, and the third circuit electrode layer 168 may be formed of metal or metal silicide. In the example embodiment, the configuration of the first to third circuit electrode layers 164 to 168 is not limited thereto, and the number and materials of the first to third circuit electrode layers 164 to 168 may be modified. The spacer layer 170 may be disposed on opposite side surfaces of the gate stack 160 and may include, for example, silicon nitride or silicon oxide. The impurity regions 108 may be disposed on opposite side surfaces of the gate stack 160 in the substrate 101. The impurity region 108 may include, for example, an impurity of a first conductivity type different from the third well NW, and may serve as a drain/source region of the transistor. The circuit active area PACT and the circuit gate electrode PG may have a third contact plug MC3 connected thereto.
The dummy gate electrode DG may be disposed on the first to third dummy active regions DM1 to DM 3. The dummy gate electrode DG may have a shape depending on the pattern of the first to third dummy active regions DM1 to DM3 and may extend in the y direction. Accordingly, a portion of the dummy gate electrode DG may be disposed between the boundary of the memory CELL region CELL in which the gate electrode structure is disposed and the first guard active region GB1, and another portion of the dummy gate electrode DG may be disposed between the first guard active region GB1 and the second guard active region GB 2. The width W2 of the dummy gate electrode DG may be greater than the width W1 of the first to third dummy active regions DM1 to DM 3. However, the inventive concept is not limited thereto. In the example embodiment, the width W2 of the dummy gate electrode DG may also be the same as the width W1 of the first to third dummy active regions DM1 to DM 3. The dummy gate electrode DG may have a structure of the gate stack structure 160, and may further include a spacer layer 170 disposed on opposite side surfaces of the gate stack structure 160 from each other. The dummy gate electrode DG may not be connected to the contact plug, and/or may not have the impurity region 108 disposed adjacent thereto, unlike in the circuit gate electrode PG. Thus, in some embodiments, the dummy gate electrode DG and the dummy active regions DM1 to DM3 are not configured to function as transistors.
As shown in fig. 5, the first to third gate regions 160a to 160c may be disposed on the first to third active regions 110a to 110c, and may have a greater width than the first to third active regions 110a to 110 c. The first to third gate regions 160a to 160c may each be a dummy gate electrode such as a dummy gate electrode DG. The first to third gate regions 160a to 160c may have the same structure as the gate stack structure 160, and the spacer layer 170 may be formed on opposite side surfaces of each of the first to third gate regions 160a to 160 c. In example embodiments, the sizes, shapes, and arrangements of the first to third gate regions 160a to 160c may be modified, and the first to third gate regions 160a to 160c may have arrangements different from the first to third active regions 110a to 110 c.
The first and second contact plugs MC1 and MC2 may be connected to the first and second guard active regions GB1 and GB2, respectively. Plug doped regions 105a and 105b including impurities may be provided within the substrate 101, to which the first contact plug MC1 and the second contact plug MC2 are connected. The plug doping region 105a disposed under the first contact plug MC1 may include a relatively high concentration of impurities having the same conductivity type as the impurities included in the second well DNW, and the plug doping region 105b disposed under the second contact plug MC2 may include a relatively high concentration of impurities having the same conductivity type as the impurities included in the substrate 101. In an example embodiment, the plug doped regions 105a and 105b may also be omitted. Nevertheless, the first guard active region GB1 and the second guard active region GB2 differ from the first to third dummy active regions DM1 to DM3 at least in the following: the first and second guard active regions are connected to the first and second contact plugs MC1 and MC2 (e.g., for connection to a power source) and include optional plug doped regions 105a and 105b. In some embodiments, the dummy active regions DM1 to DM3 are not connected to the contact plugs and do not include plug doped regions.
Fig. 7 and 8 are schematic layout diagrams of a semiconductor device according to example embodiments.
Referring to fig. 7, unlike the example embodiments of fig. 3 and 5, the semiconductor device 100b may include a first dummy active region DM1a and a second dummy active region DM2a, each of which includes a plurality of quadrilateral patterns. According to the present exemplary embodiment, each of the first and second dummy active regions DM1a and DM2a may include a quadrangular pattern disposed in one row in the y-direction. Each quadrilateral pattern may be square or rectangular. In an example embodiment, the length L5 of the quadrangular pattern forming each of the first and second dummy active areas DM1a and DM2a may be modified. In an example embodiment, each of the first and second dummy active regions DM1a and DM2a may further include a quadrangular pattern having different lengths.
Referring to fig. 8, unlike the example embodiments of fig. 3, 5 and 7, the semiconductor device 100c may not include the first dummy active regions DM1 and DM1a (refer to fig. 3, 5 and 7). For example, the dummy active region may not be disposed between the cell active region CACT and the first guard active region GB1 in the x-direction. Here, the distance L1a between the unit active region CACT and the first guard active region GB1 may be less than, for example, 3 μm, but is not limited thereto. In the present exemplary embodiment, the second dummy active region DM2 and the third dummy active region DM3 disposed between the first guard active region GB1 and the second guard active region GB2 may increase the density of the active regions between the cell active region CACT and the circuit active region PACT to prevent the above-described dishing effect from occurring even when the dummy active regions are not disposed between the cell active region CACT and the first guard active region GB 1. In an example embodiment, the third active region 110c may also be omitted.
Fig. 9A to 9I are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. Fig. 9A to 9I show regions corresponding to the regions shown in fig. 6.
Referring to fig. 9A, first to third wells PW, DNW, and NW may be formed in the substrate 101, and a circuit gate insulating layer 162 and a first circuit electrode layer 164 may be formed on the substrate 101.
The first to third wells PW, DNW, and NW may be formed by implanting impurities into the substrate 101 using an ion implantation process. The first well PW may be formed by implanting impurities of a first conductivity type (e.g., p-type) into the substrate 101, and the second well DNW and the third well NW may be formed by implanting impurities of a second conductivity type (e.g., n-type) into the substrate 101. The second well DNW and the third well NW may include impurities having different concentrations. The peripheral circuit region CKT may include wells of various conductivity types, and a well disposed in a region not shown and including an impurity of a first conductivity type may be formed in the present process stage.
The circuit gate insulating layer 162 and the first circuit electrode layer 164 may be sequentially formed on the substrate 101. The circuit gate insulating layer 162 and the first circuit electrode layer 164 may be formed using an Atomic Layer Deposition (ALD) or a Chemical Vapor Deposition (CVD) process.
The peripheral circuit region CKT may include a region in which a high voltage transistor is disposed and a region in which a low voltage transistor is disposed. A process of removing a portion of the upper portion of the substrate 101 in a region where the high voltage transistor is disposed may be performed before the circuit gate insulating layer 162 is formed. In this case, the circuit gate insulating layer 162 may be formed to have different thicknesses in a region in which a high voltage transistor is disposed and a region in which a low voltage transistor is disposed. The circuit gate insulating layer 162 may be formed of, for example, silicon oxide, and the first circuit electrode layer 164 may be formed of, for example, polysilicon. However, the inventive concept is not limited thereto.
Referring to fig. 9B, portions of the circuit gate insulating layer 162, the first circuit electrode layer 164, and the substrate 101 may be removed to form a trench TE.
Using an additional masking layer, the region in which the trench TE is to be formed may be exposed. An etching process may then be used to form the trench TE. The trench TE may be formed using an anisotropic etching process (e.g., a plasma etching process). The depth of the trench TE may vary depending on the characteristics of the semiconductor device and may, for example, range fromTo- >The sidewalls of the trench TE may not be perpendicular to the upper surface of the substrate 101. For example, the width of the trench TE may decrease toward the lower surface of the substrate 101. However, the inventive concept is not limited thereto. After forming the trench TE, an additional ion implantation process for enhancing insulating properties may be performed.
Referring to fig. 9C, a device isolation layer 120P may be formed to fill the trench TE.
The device isolation layer 120P may include an oxide, such as at least one of High Temperature Oxide (HTO), high Density Plasma (HDP) oxide, tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), and Undoped Silicate Glass (USG). For example, the device isolation layer 120P may include an upper TEOS layer and a lower USG layer. The device isolation layer 120P may have a thickness that is sufficiently increased to completely fill the trench TE. After forming the device isolation layer 120P, an additional annealing process for highly densification of the device isolation layer 120P may be performed.
In an example embodiment, a trench liner layer may also be formed within each trench TE prior to forming the device isolation layer 120P. The trench liner layer may comprise, for example, silicon oxide or silicon nitride.
Referring to fig. 9D, a planarization process allowing the device isolation layer 120P to fill only the trench TE may be performed to form the device isolation region 120.
The planarization process may be, for example, a Chemical Mechanical Polishing (CMP) process. The planarization process may be performed using the first circuit electrode layer 164 as a CMP stop layer, and a portion of the first circuit electrode layer 164 may be polished and removed during the planarization process.
After the planarization process, the device isolation regions 120 filling the trenches TE may be formed. The device isolation region 120 may define active regions of the substrate 101, such as a cell active region CACT, a circuit active region PACT, a first guard active region GB1, a second guard active region GB2, a first dummy active region DM1, a second dummy active region DM2, and a third dummy active region DM3. The first to third dummy active regions DM1 to DM3 can prevent a dishing effect from occurring between the cell active region CACT and the first guard active region GB1 and between the first guard active region GB1 and the second guard active region GB2 during the planarization process.
Referring to fig. 9E, a second circuit electrode layer 166 and a third circuit electrode layer 168 may be sequentially formed on the first circuit electrode layer 164 and the device isolation region 120.
The second circuit electrode layer 166 may be formed of polysilicon, and the third circuit electrode layer 168 may be formed of metal or metal silicide. However, the inventive concept is not limited thereto. For example, the third circuit electrode layer 168 may include a tungsten silicide layer.
Referring to fig. 9F, the circuit gate insulating layer 162 and the first to third circuit electrode layers 164 to 168 may be patterned to form the gate stack structure 160, and the spacer layer 170 and the impurity region 108 may be formed on opposite sides of the gate stack structure 160 from each other.
Using the additional mask layer, portions of the circuit gate insulating layer 162 and the first to third circuit electrode layers 164 to 168 may be removed using an etching process to form the gate stack structure 160. Subsequently, a spacer layer 170 may be formed on sidewalls of the gate stack 160 opposite to each other. According to an example embodiment, the spacer layer 170 may also include multiple layers.
Subsequently, an ion implantation process may be performed to form the impurity region 108. According to example embodiments, the impurity region 108 may be formed in other process stages, and may also be formed using an ion implantation process after forming the mask, so that a region including the memory CELL region CELL may not be exposed. In example embodiments, in the present process stage, impurity regions may be formed in the first and second guard active regions GB1 and GB 2.
In this process stage, circuit gate electrodes PG and dummy gate electrodes DG, each including a gate stack structure 160, may be formed. The width W2 of the dummy gate electrode DG in the x-direction may be greater than the width W1 of the first to third dummy active regions DM1 to DM 3. However, the inventive concept is not limited thereto.
Referring to fig. 9G, the sacrificial layers 181, 182, 183, 184, 185, 186, 187, and 188 and the interlayer insulating layer 140, which are denoted together by the sacrificial layer stack 180, may be alternately stacked on the substrate 101, and portions of the sacrificial layer stack 180 and the interlayer insulating layer 140 may be removed so that the sacrificial layers 181 to 188 may extend in the memory CELL region CELL to have different lengths in the x direction.
The sacrificial layer stack 180 may be replaced by the gate electrode stack 130 through a subsequent process. The sacrificial layer stack 180 may be formed of a material that can be etched using an etch selectivity with respect to the interlayer insulating layer 140. For example, the interlayer insulating layer 140 may include at least one of silicon oxide and silicon nitride, and the sacrificial layer stack 180 may be formed of a material selected from silicon, silicon oxide, silicon carbide, and silicon nitride and different from the interlayer insulating layer 140. In an example embodiment, the thicknesses of all of the interlayer insulating layers 140 may not be the same. The thickness and number of the interlayer insulating layer 140 and the sacrificial layers 181 to 188 may be modified. Before or during forming the sacrificial layer stack 180 and the interlayer insulating layer 140, an additional insulating layer may be formed in the peripheral circuit region CKT to cover the circuit gate electrode PG and the dummy gate electrode DG.
The photolithography process and the etching process for the sacrificial layer stack 180 may be repeated such that the upper sacrificial layer of the sacrificial layer stack 180 may extend to have a shorter length than the lower sacrificial layer of the sacrificial layer stack 180. Accordingly, the sacrificial layer stack 180 may have a stepped shape. Subsequently, a process of forming the sacrificial layer stack 180 to have a relatively increased thickness at an end of each of the sacrificial layers thereof may be performed.
Subsequently, an upper insulating layer 190 may be formed to cover the upper surface of the stacked structure of the sacrificial layer stack 180 and the interlayer insulating layer 140. In the peripheral circuit region CKT, the upper insulating layer 190 may include a plurality of layers.
Referring to fig. 9H, a channel CH may be formed through the stacked structure of the sacrificial layer stack 180 and the interlayer insulating layer 140 in the memory CELL region CELL. Subsequently, an epitaxial layer 107, a first gate dielectric layer 154, a channel region 152, a channel insulating layer 192, and a channel pad 158 may be formed in each channel CH.
The channel CH may be formed by anisotropically etching portions of the sacrificial layer stack 180 and the interlayer insulating layer 140, and may have a hole shape. Due to the thickness of the stacked structure, the sidewalls of the channel CH may not be perpendicular to the upper surface of the substrate 101. In an example embodiment, the channel CH may recess a portion of the substrate 101. A portion of the channel CH may be a dummy channel, and the dummy channel may be formed even in regions where the sacrificial layers 181 to 188 extend to have different lengths.
The epitaxial layer 107 may be formed using a Selective Epitaxial Growth (SEG) process. Epitaxial layer 107 may comprise a single layer or multiple layers. Epitaxial layer 107 may include polysilicon, monocrystalline silicon, polycrystalline germanium, or monocrystalline germanium doped with or without impurities. The first gate dielectric layer 154 may be formed to have a uniform thickness using an ALD or CVD process. Channel regions 152 may be formed on the first gate dielectric layer 154 within each channel CH. The channel insulating layer 192 may be formed to fill each channel CH, and may be an insulating material. In an example embodiment, a conductive material may fill the space within the channel region 152 instead of the channel insulating layer 192. The channel pad 158 may be formed of a conductive material (e.g., polysilicon).
Referring to fig. 9I, the sacrificial layer stack 180 may be removed, and the second gate dielectric layer 156 and the gate electrode stack 130 may be formed in a region from which the sacrificial layer stack 180 is removed.
First, a portion of the stacked structure of the sacrificial layer stack 180 and the interlayer insulating layer 140 may be anisotropically etched to form an isolation region 194, as shown in fig. 5. The isolation region 194 may have a trench shape extending in the x-direction. The sacrificial layer stack 180 exposed by the isolation region 194 may be selectively removed with respect to the interlayer insulating layer 140 using, for example, a wet etching process. Accordingly, portions of the sidewalls of the first gate dielectric layer 154 in each channel CH between portions of each of the interlayer insulating layers 140 may be exposed.
The second gate dielectric layer 156 may be formed in a region from which the sacrificial layer stack 180 is removed, and a space within the second gate dielectric layer 156 may be filled with a conductive material to form the gate electrode stack 130. The gate electrode stack 130 may include metal, polysilicon, or metal silicide.
Subsequently, an insulating layer having a spacer shape and a conductive layer filling a space between the insulating layers may be formed in the isolation region 194. In an example embodiment, the isolation region 194 may be filled with only an insulating material, and the impurity region may be formed in the substrate 101 under the isolation region 194.
Referring to fig. 5 and 6, a gate contact CT connected to a gate electrode of the gate electrode stack 130 and first to third contact plugs MC1 to MC3 may be formed.
The gate contact CT and the first to third contact plugs MC1 to MC3 may be formed simultaneously or sequentially. First, a contact hole may be formed through the upper insulating layer 190, and a conductive material may be deposited in the contact hole to form the gate contact CT and the first to third contact plugs MC1 to MC3. A process of implanting impurities into the substrate 101 through the contact hole may be performed before depositing the conductive material. Accordingly, the plug doped regions 105a and 105b may be formed in upper regions of the first and second guard active regions GB1 and GB2 connected to the first and second contact plugs MC1 and MC 2.
As described above, according to example embodiments of the inventive concepts, a semiconductor device having improved reliability may be provided by providing a dummy active region around an edge of a memory cell region.
Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept, which is defined by the appended claims.
The present application claims the benefit of priority from korean patent application No. 10-2017-0086335 filed in the korean intellectual property office on 7 th 2017, the disclosure of which is incorporated herein by reference in its entirety.

Claims (23)

1. A semiconductor device, comprising:
a substrate having a first region including a memory cell and a second region including a transistor for driving the memory cell; and
a device isolation region disposed within the substrate to define an active region of the substrate,
wherein the active region comprises:
a first guard active region surrounding the first region;
a second guard active region surrounding a portion of the second region; and
At least one dummy active region disposed between the first and second guard active regions, and
wherein at least one first contact plug is connected to the first guard active region, at least one second contact plug is connected to the second guard active region, and the at least one dummy active region is not directly under any contact plug.
2. The semiconductor device of claim 1, wherein the substrate comprises:
a first well disposed in the first region, the first well including an impurity of a first conductivity type; and
a second well disposed within the substrate to surround the first well, the second well including the first guard active region, and the second well including an impurity of a second conductivity type.
3. The semiconductor device of claim 1, wherein the second guard active region surrounds at least a transistor of the second region that is closest to the first region.
4. The semiconductor device of claim 1, wherein the second guard active region is closest to the first guard active region among the active regions disposed in the second region, except for the at least one dummy active region.
5. The semiconductor device of claim 1, wherein the substrate comprises a third well disposed in the second region, the third well disposed adjacent to the second guard active region.
6. The semiconductor device of claim 1, wherein the first guard active region and the second guard active region comprise impurities of different conductivity types.
7. The semiconductor device of claim 1, wherein the active region further comprises a cell active region disposed in the first region, and at least one dummy active region is further disposed between the cell active region and the first guard active region.
8. The semiconductor device of claim 1, wherein the at least one dummy active region is spaced apart from and extends along a boundary between the first region and the second region.
9. The semiconductor device of claim 1, wherein each dummy active region of the at least one dummy active region has a line shape in a plane.
10. The semiconductor device of claim 1, wherein each dummy active region of the at least one dummy active region has a plurality of quadrilateral patterns arranged in a row on a plane.
11. The semiconductor device of claim 1, wherein the at least one dummy active region comprises a plurality of regions that are spaced apart from one another and that extend in parallel in one direction.
12. The semiconductor device of claim 1, further comprising:
and a dummy gate electrode disposed on a first dummy active region of the at least one dummy active region.
13. The semiconductor device of claim 12, wherein the dummy gate electrode extends in one direction along the first dummy active region.
14. The semiconductor device of claim 12, wherein a width of the dummy gate electrode is greater than a width of the first dummy active region.
15. The semiconductor device of claim 12, wherein the dummy gate electrode comprises a first electrode layer and a second electrode layer sequentially stacked on the substrate, the first electrode layer comprising polysilicon, the second electrode layer comprising a metal or metal silicide.
16. The semiconductor device of claim 1, further comprising:
a channel region extending vertically in the first region; and
gate electrodes spaced apart from each other and stacked along the channel region, the gate electrodes extending toward a boundary between the first region and the second region to have different lengths.
17. The semiconductor device of claim 16, wherein the gate electrode extends in a first direction and the at least one dummy active region extends in a second direction perpendicular to the first direction.
18. The semiconductor device of claim 1, wherein a distance between the first guard active region or the second guard active region and the at least one dummy active region adjacent to the first guard active region or the second guard active region is less than 3 μιη.
19. The semiconductor device of claim 1, wherein each of the first guard active region and the second guard active region has a quadrilateral ring shape.
20. A semiconductor device, comprising:
a substrate having a first region including a cell active region having a memory cell disposed therein and a second region disposed on at least one side of the first region,
wherein the second region comprises at least one dummy active region extending in one direction along a boundary between the first region and the second region,
Wherein the second region further comprises:
a first guard active region surrounding the first region; and
a second guard active region disposed around the first guard active region to surround a portion of the second region, and
one or more dummy active regions of the at least one dummy active region are disposed between the first guard active region and the second guard active region, and
wherein the semiconductor device further comprises a dummy gate electrode disposed on a first dummy active region of the at least one dummy active region.
21. The semiconductor device of claim 20, wherein the dummy gate electrode covers the first dummy active region and extends in the one direction.
22. A semiconductor device, comprising:
a gate electrode structure including gate electrodes spaced apart from each other and stacked on a substrate in a first direction perpendicular to the substrate, and extending to have different lengths in a second direction perpendicular to the first direction;
a first guard active region disposed within the substrate to surround the gate electrode structure;
At least one dummy active region disposed within the substrate to extend parallel to the first guard active region; and
a second guard active region, the at least one dummy active region being disposed between the first guard active region and the second guard active region in the second direction,
wherein the first guard active region and the second guard active region include impurities of different conductivity types.
23. The semiconductor device of claim 22, wherein the at least one dummy active region extends in a third direction perpendicular to the first direction and the second direction.
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